Analysis to Input Current Zero Crossing Distortion of Bridgeless Rectifier Operating under Different Power Factors

Jinqi Liu 1,* , Yizhou Liu 2, Yuan Zhuang 1 and Cong Wang 1 1 School of Mechanical electronic & Information Engineering, China University of Mining & Technology, Beijing 100083, China; zhuangy90@126.com (Y.Z.); wangc@cumtb.edu.cn (C.W.) 2 School of Mining Engineering Taiyuan University of Technology, Taiyuan 030024, China; liuyizhou@tyut.edu.cn * Correspondence: 15333003179@163.com; Tel.: +86-153-3300-3179


Introduction
Devices based on full-control Pulse Width Modulation (PWM) converter technology have been widely used to solve power quality problems, such as harmonic and reactive power contamination, which is caused by certain power electronic devices.Among them, the static var generator (SVG), static synchronous compensator (STATCOM), and active power filter (APF) are most popularly used in this area [1][2][3].However, adding these devices into the grid undoubtedly increases the use of physical devices and extra power loss [4].Therefore, increasing attention is being paid to the incorporation of reactive power compensation and other power quality functionality into fully controlled bidirectional converters used in renewable energy-based generation systems or Vehicle-to-grid (V2G) systems [5][6][7].
However, in many practical applications, including speed regulation with fan type loads, wind power integration, and plug-in electrical vehicle applications, only unidirectional power flow is required.In these situations, some fully controlled switches can be eliminated or replaced to simplify the system, which greatly reduces the complexity of system, saves costs, and improves the system reliability [8,9].Taking these considerations into account, many researchers have investigated the possibility of incorporating reactive power compensation (RPC) and harmonic current compensation (HCC) functionalities into general unidirectional power converters [10,11].
Bridgeless rectifiers, as a kind of unidirectional converter, have a simpler structure and lower power losses [12][13][14].Especially when multilevel medium-or high-voltage converters are formed by cascading bridgeless rectifiers, the advantages of fewer massive fully control switching devices, lower costs, and improved reliability become more significant.In [15], a cascaded bridgeless rectifier typology was proposed and a mechanism causing current zero-crossing distortion was discussed.However, a detailed theoretical analysis of the current distortion was not carried out, and the ability of bridgeless rectifiers operating under leading or lagging power factors was not mentioned.The input current distortion of bridgeless rectifiers under a unity power factor was analyzed theoretically in [16] and a control strategy based on specific lagging power factor was proposed, but there was no analysis of the input current distortion under leading or lagging power factor.In [17], some reactive power compensation functionality was integrated in bridgeless rectifiers, and the input current distortion characteristics given different power factors was analyzed to determine the reactive power compensation ability of bridgeless rectifiers.However, all analyses provided by [17] are based on the assumption that bridgeless rectifiers operate under synchronous driving mode.It will be seen from the later discussion that compared with synchronous driving mode, complementary driving mode induces fewer harmonics in the input current of bridgeless rectifiers, and therefore is a more suitable driving mode for bridgeless rectifiers under different power factors.
As mentioned above, the research of bridgeless rectifiers in most literature was performed based on the unity power factor.Only a few studies discuss the characteristics of bridgeless rectifiers operating under non-unity power factors.However, no studies have reported the effect of different driving modes on input current distortion when bridgeless rectifiers operate under non-unit power factors.In order to more effectively integrate RPC and HCC capabilities into a bridgeless rectifier, the harmonic characteristics of bridgeless rectifiers under different power factors in complementary driving mode are discussed in this paper.We concluded that the complementary drive mode is a better choice in terms of reducing the current distortion when bridgeless rectifiers operate under non-unity power factors.Meanwhile, this analysis is helpful for the design of bridgeless rectifiers and the selection of the corresponding parameters under non-unity power factors.Two driving modes for switches are discussed on the basis of the principle of bridgeless rectifiers in Section 2.Then, the characteristics of current zero-crossing distortion under different power factors are analyzed in Section 3. The limitation of filter inductance, input current amplitude, and the value of the power factor angle in the allowable range of the total harmonic distortion (THD) of the current are analyzed in Section 4. Finally, the accuracy of the proposed theoretical analysis is verified through simulation and experiment.

Effective Operation Mode and Mathematical Model
The circuit topology of a bridgeless rectifier is shown in Figure 1a, where u con is the alternating current (AC) side voltage of bridgeless rectifier and i s is the input current.The polarity of u con and i s shown in Figure 1a is defined as positive polarity.L is the AC side filter inductance, C is the direct current (DC) side of the filter capacitor, U dc is the DC side output voltage, and R is the equivalent load of bridgeless rectifier.
Energies 2018, 11, x 2 of 17 Bridgeless rectifiers, as a kind of unidirectional converter, have a simpler structure and lower power losses [12][13][14].Especially when multilevel medium-or high-voltage converters are formed by cascading bridgeless rectifiers, the advantages of fewer massive fully control switching devices, lower costs, and improved reliability become more significant.In [15], a cascaded bridgeless rectifier typology was proposed and a mechanism causing current zero-crossing distortion was discussed.However, a detailed theoretical analysis of the current distortion was not carried out, and the ability of bridgeless rectifiers operating under leading or lagging power factors was not mentioned.The input current distortion of bridgeless rectifiers under a unity power factor was analyzed theoretically in [16] and a control strategy based on specific lagging power factor was proposed, but there was no analysis of the input current distortion under leading or lagging power factor.In [17], some reactive power compensation functionality was integrated in bridgeless rectifiers, and the input current distortion characteristics given different power factors was analyzed to determine the reactive power compensation ability of bridgeless rectifiers.However, all analyses provided by [17] are based on the assumption that bridgeless rectifiers operate under synchronous driving mode.It will be seen from the later discussion that compared with synchronous driving mode, complementary driving mode induces fewer harmonics in the input current of bridgeless rectifiers, and therefore is a more suitable driving mode for bridgeless rectifiers under different power factors.
As mentioned above, the research of bridgeless rectifiers in most literature was performed based on the unity power factor.Only a few studies discuss the characteristics of bridgeless rectifiers operating under non-unity power factors.However, no studies have reported the effect of different driving modes on input current distortion when bridgeless rectifiers operate under non-unit power factors.In order to more effectively integrate RPC and HCC capabilities into a bridgeless rectifier, the harmonic characteristics of bridgeless rectifiers under different power factors in complementary driving mode are discussed in this paper.We concluded that the complementary drive mode is a better choice in terms of reducing the current distortion when bridgeless rectifiers operate under nonunity power factors.Meanwhile, this analysis is helpful for the design of bridgeless rectifiers and the selection of the corresponding parameters under non-unity power factors.Two driving modes for switches are discussed on the basis of the principle of bridgeless rectifiers in Section 2.Then, the characteristics of current zero-crossing distortion under different power factors are analyzed in Section 3. The limitation of filter inductance, input current amplitude, and the value of the power factor angle in the allowable range of the total harmonic distortion (THD) of the current are analyzed in Section 4. Finally, the accuracy of the proposed theoretical analysis is verified through simulation and experiment.

Effective Operation Mode and Mathematical Model
The circuit topology of a bridgeless rectifier is shown in Figure 1a, where ucon is the alternating current (AC) side voltage of bridgeless rectifier and is is the input current.The polarity of ucon and is shown in Figure 1a is defined as positive polarity.L is the AC side filter inductance, C is the direct current (DC) side of the filter capacitor, Udc is the DC side output voltage, and R is the equivalent load of bridgeless rectifier.Due to the unidirectional conduction property of the fast recovery diodes, the value of the AC side voltage ucon of the bridgeless rectifier depends on the switching state and the polarity of the input current.Thus, there are only four effective operation modes for bridgeless rectifiers as shown in Figures 1b-e, which are summarized in Table 1.

Mode
From Table 1, the expression of AC side voltage is obtained as: sgn( ) where S (S = 0, 1) refers to the switch function of bridgeless rectifier and sgn(  ) is the sign function.
Applying the Kirchhoff's voltage law (KVL) and Kirchhoff's circuit laws (KCL) to the topology shown in Figure 1, the steady-state mathematical model of the system can be obtained by ignoring AC-side power loss: sgn( ) sgn( )

Driving Mode of Two Switches
Since only one switch affects the commutation process during each half cycle of the input current and the two switches have the same source (or emitter) voltage, synchronous and complementary driving modes can be applied.
Figure 2 depicts a block diagram for complementary drive.The output of voltage regulator is shifted to satisfy the required power factor and then given as the input current.Complementary signal gS1, gS2 is generated in modulation as driving signals of switches S1, S2, respectively.Due to the unidirectional conduction property of the fast recovery diodes, the value of the AC side voltage u con of the bridgeless rectifier depends on the switching state and the polarity of the input current.Thus, there are only four effective operation modes for bridgeless rectifiers as shown in Figure 1b-e, which are summarized in Table 1.
From Table 1, the expression of AC side voltage is obtained as: where S (S = 0, 1) refers to the switch function of bridgeless rectifier and sgn(i s ) is the sign function.
Applying the Kirchhoff's voltage law (KVL) and Kirchhoff's circuit laws (KCL) to the topology shown in Figure 1, the steady-state mathematical model of the system can be obtained by ignoring AC-side power loss:

Driving Mode of Two Switches
Since only one switch affects the commutation process during each half cycle of the input current and the two switches have the same source (or emitter) voltage, synchronous and complementary driving modes can be applied.
Figure 2  The block diagram for a synchronous drive is shown in Figure 3, where S1 and S2 are driven by the same control signal.However, it is necessary to take the absolute value of the grid voltage and the input current, otherwise the current will be discontinuous in the negative half cycle.The corresponding waveform is shown in Figure 4. Its relevant parameters were selected as Usm = 311 V, f = 50 Hz, Udc = 400 V, R = 0.09 Ω, and L = 3 mH.When the polarity of is reverses from positive to negative, us also reverses its polarity.At this moment, if S1 and S2 are turned on, is runs through S2 and DS1 and increases, while its polarity is negative.When S1 and S2 are turned off, ucon = -udc, based on the boost characteristics of the rectifier, the voltage of the inductance drops, uL = us -ucon > 0. Thus, the polarity of is is negative and the amplitude decreases, which causes   * −   to become smaller.
The duty ratio dS1 of S1 and dS2 of S2 decreases as well.This control leads is in the cut-off state at the negative half cycle.

Adjustable phase shift
Current regulator  Synchronous driving mode significantly simplifies the implementation of the control circuit of the bridgeless rectifier and is more popularly used than complementary driving mode in practical applications.When a bridgeless rectifier operates under a unity power factor, there is no difference in the current distortion under the two different driving modes.However, when incorporating the reactive power compensation (RPC) and harmonic current compensation (HCC) functionalities into the bridgeless rectifier, the bridgeless rectifier is required to operate under non-unity power factors.In this situation, the two driving modes have different effects on the input current waveform.It will be seen that complementary driving mode is a better choice in terms of reducing the current distortion compared with synchronous driving, which is discussed in detail in Section 3. The block diagram for a synchronous drive is shown in Figure 3, where S 1 and S 2 are driven by the same control signal.However, it is necessary to take the absolute value of the grid voltage and the input current, otherwise the current will be discontinuous in the negative half cycle.The corresponding waveform is shown in Figure 4. Its relevant parameters were selected as U sm = 311 V, f = 50 Hz, U dc = 400 V, R = 0.09 Ω, and L = 3 mH.When the polarity of i s reverses from positive to negative, u s also reverses its polarity.At this moment, if S 1 and S 2 are turned on, i s runs through S 2 and D S1 and increases, while its polarity is negative.When S 1 and S 2 are turned off, u con = -u dc , based on the boost characteristics of the rectifier, the voltage of the inductance drops, u L = u s -u con > 0. Thus, the polarity of i s is negative and the amplitude decreases, which causes i * s − i s to become smaller.The duty ratio d S1 of S 1 and d S2 of S 2 decreases as well.This control leads i s in the cut-off state at the negative half cycle.The block diagram for a synchronous drive is shown in Figure 3, where S1 and S2 are driven by the same control signal.However, it is necessary to take the absolute value of the grid voltage and the input current, otherwise the current will be discontinuous in the negative half cycle.The corresponding waveform is shown in Figure 4. Its relevant parameters were selected as Usm = 311 V, f = 50 Hz, Udc = 400 V, R = 0.09 Ω, and L = 3 mH.When the polarity of is reverses from positive to negative, us also reverses its polarity.At this moment, if S1 and S2 are turned on, is runs through S2 and DS1 and increases, while its polarity is negative.When S1 and S2 are turned off, ucon = -udc, based on the boost characteristics of the rectifier, the voltage of the inductance drops, uL = us -ucon > 0. Thus, the polarity of is is negative and the amplitude decreases, which causes   * −   to become smaller.
The duty ratio dS1 of S1 and dS2 of S2 decreases as well.This control leads is in the cut-off state at the negative half cycle.

Adjustable phase shift
Current regulator  Synchronous driving mode significantly simplifies the implementation of the control circuit of the bridgeless rectifier and is more popularly used than complementary driving mode in practical applications.When a bridgeless rectifier operates under a unity power factor, there is no difference in the current distortion under the two different driving modes.However, when incorporating the reactive power compensation (RPC) and harmonic current compensation (HCC) functionalities into the bridgeless rectifier, the bridgeless rectifier is required to operate under non-unity power factors.In this situation, the two driving modes have different effects on the input current waveform.It will be seen that complementary driving mode is a better choice in terms of reducing the current distortion compared with synchronous driving, which is discussed in detail in Section 3.  The block diagram for a synchronous drive is shown in Figure 3, where S1 and S2 are driven by the same control signal.However, it is necessary to take the absolute value of the grid voltage and the input current, otherwise the current will be discontinuous in the negative half cycle.The corresponding waveform is shown in Figure 4. Its relevant parameters were selected as Usm = 311 V, f = 50 Hz, Udc = 400 V, R = 0.09 Ω, and L = 3 mH.When the polarity of is reverses from positive to negative, us also reverses its polarity.At this moment, if S1 and S2 are turned on, is runs through S2 and DS1 and increases, while its polarity is negative.When S1 and S2 are turned off, ucon = -udc, based on the boost characteristics of the rectifier, the voltage of the inductance drops, uL = us -ucon > 0. Thus, the polarity of is is negative and the amplitude decreases, which causes   * −   to become smaller.
The duty ratio dS1 of S1 and dS2 of S2 decreases as well.This control leads is in the cut-off state at the negative half cycle.

Adjustable phase shift
Current regulator  Synchronous driving mode significantly simplifies the implementation of the control circuit of the bridgeless rectifier and is more popularly used than complementary driving mode in practical applications.When a bridgeless rectifier operates under a unity power factor, there is no difference in the current distortion under the two different driving modes.However, when incorporating the reactive power compensation (RPC) and harmonic current compensation (HCC) functionalities into the bridgeless rectifier, the bridgeless rectifier is required to operate under non-unity power factors.In this situation, the two driving modes have different effects on the input current waveform.It will be seen that complementary driving mode is a better choice in terms of reducing the current distortion compared with synchronous driving, which is discussed in detail in Section 3. Synchronous driving mode significantly simplifies the implementation of the control circuit of the bridgeless rectifier and is more popularly used than complementary driving mode in practical applications.When a bridgeless rectifier operates under a unity power factor, there is no difference in the current distortion under the two different driving modes.However, when incorporating the reactive power compensation (RPC) and harmonic current compensation (HCC) functionalities into the bridgeless rectifier, the bridgeless rectifier is required to operate under non-unity power factors.In this situation, the two driving modes have different effects on the input current waveform.It will be seen that complementary driving mode is a better choice in terms of reducing the current distortion compared with synchronous driving, which is discussed in detail in Section 3.

Theory for Input Current Zero-Crossing Distortion
Due to the unidirectional power flow for the bridgeless rectifier, whenever the polarities of the current and voltage on the AC side of the rectifier switch, an input current distortion appears.The steady state AC side phasor diagram is shown in Figure 5, where U * con and I * s are the reference voltage and reference current on the AC side of the rectifier, respectively.When the rectifier is operating under a unity power factor, the input current I s is in phase with the source voltage U s , and the voltage across the input inductor U L is orthogonal to I s .According to the triangle law of vector addition, U con lags I s by θ, as shown in Figure 5.This lagging angle θ indicates that, during the period of θ after the current crosses zero, the input current i s and the AC-side voltage u con are required to have opposite polarities.However, due to the unidirectional power flow, the AC-side voltage and current of the bridgeless rectifier must have the same polarity.Hence, during this period, AC-side voltage u con can only be kept at zero, which makes the input current uncontrollable [18,19].Note that the heavier the loads, the more serious the input current zero-crossing distortion.

Theory for Input Current Zero-Crossing Distortion
Due to the unidirectional power flow for the bridgeless rectifier, whenever the polarities of the current and voltage on the AC side of the rectifier switch, an input current distortion appears.The steady state AC side phasor diagram is shown in Figure 5, where   * and   * are the reference voltage and reference current on the AC side of the rectifier, respectively.When the rectifier is operating under a unity power factor, the input current   is in phase with the source voltage   , and the voltage across the input inductor   is orthogonal to   .According to the triangle law of vector addition,   lags   by θ, as shown in Figure 5.This lagging angle θ indicates that, during the period of θ after the current crosses zero, the input current   and the AC-side voltage   are required to have opposite polarities.However, due to the unidirectional power flow, the AC-side voltage and current of the bridgeless rectifier must have the same polarity.Hence, during this period, AC-side voltage   can only be kept at zero, which makes the input current uncontrollable [18,19].Note that the heavier the loads, the more serious the input current zero-crossing distortion.From the above analysis, the current zero-crossing distortion is generated under leading, lagging, and unity power factor.As the leading or lagging angle increases, the current distortion becomes more severe.Notably, the distortion of the input current under a leading power factor is more severe than the distortion of the input current under a lagging power factor.Sections 3.2-3.4discuss the input current distortion under unity power factor, leading power factor, and lagging power factor in detail, respectively, and describe the input current distortion by piecewise function in each part.The grid voltage us, reference input current i*s, and reference voltage on the AC side of the rectifier u*con under a unity power factor can be expressed as follows: From the above analysis, the current zero-crossing distortion is generated under leading, lagging, and unity power factor.As the leading or lagging angle increases, the current distortion becomes more severe.Notably, the distortion of the input current under a leading power factor is more severe than the distortion of the input current under a lagging power factor.Sections 3.2-3.4discuss the input current distortion under unity power factor, leading power factor, and lagging power factor in detail, respectively, and describe the input current distortion by piecewise function in each part.

Theory for Input Current Zero-Crossing Distortion
Due to the unidirectional power flow for the bridgeless rectifier, whenever the polarities of the current and voltage on the AC side of the rectifier switch, an input current distortion appears.The steady state AC side phasor diagram is shown in Figure 5, where   * and   * are the reference voltage and reference current on the AC side of the rectifier, respectively.When the rectifier is operating under a unity power factor, the input current   is in phase with the source voltage   , and the voltage across the input inductor   is orthogonal to   .According to the triangle law of vector addition,   lags   by θ, as shown in Figure 5.This lagging angle θ indicates that, during the period of θ after the current crosses zero, the input current   and the AC-side voltage   are required to have opposite polarities.However, due to the unidirectional power flow, the AC-side voltage and current of the bridgeless rectifier must have the same polarity.Hence, during this period, AC-side voltage   can only be kept at zero, which makes the input current uncontrollable [18,19].Note that the heavier the loads, the more serious the input current zero-crossing distortion.From the above analysis, the current zero-crossing distortion is generated under leading, lagging, and unity power factor.As the leading or lagging angle increases, the current distortion becomes more severe.Notably, the distortion of the input current under a leading power factor is more severe than the distortion of the input current under a lagging power factor.Sections 3.2-3.4discuss the input current distortion under unity power factor, leading power factor, and lagging power factor in detail, respectively, and describe the input current distortion by piecewise function in each part.The grid voltage us, reference input current i*s, and reference voltage on the AC side of the rectifier u*con under a unity power factor can be expressed as follows: The grid voltage u s , reference input current i* s , and reference voltage on the AC side of the rectifier u* con under a unity power factor can be expressed as follows:

Distortion Characteristics of Input Current under Unity Power Factor
Energies 2018, 11, 2447 If i * s > 0 and u * con < 0 within the range of 0-θ, the u con cannot follow u * con .In this period, u con is clamped to zero, and u s = u L .Accordingly, i s is expressed as: When ωt = θ, the polarity of u * con is reversed from negative to positive, and u con has the ability to follow u * con , theoretically.However, as i * s > i s , in order to make i s follow i * s , u con is still maintained at zero until i s = i * s over a period of ωt > θ.Let i s = i * s when ωt = γ, as: Therefore, the piecewise function of the input current in a power frequency cycle is expressed as The RMS value of fundamental component of input current is where: The Root Mean Square (RMS) value of input current is: where I sm can be obtained based on conservation of power, as: THD of input current can be deduced as: Note that the above analytical methods can be applied to both driving modes.

Distortion Characteristics of Input Current under Leading Power Factor
Figure 7 shows the AC-side fundamental waveform of a system with a synchronous drive.When ωt = 0, the polarity of i * s is reversed from negative to positive, u con is zero, and the polarity of u s is negative, which leads to the negative increase in u s .The rate of increase of |i * s | is larger than that of |i s | in the heavy load.In order to make |i s | follow |i * s |, u con is clamped to zero until i s = i * s when ωt = γ.The amplitude of i * s is smaller in the underloading.i s = −i * s can be achieved within a certain period after reversing the polarity of i s .When u s approaches 0, the growth rate of |i s | decreases.The change rate of i s is 0 when ωt = θ, |i s | < |i * s |.Then u s reverses its polarity.To make |i s | follow |i * s |, u con is clamped to zero until i s = i * s .The current distortion process will end at this point.
Note that the above analytical methods can be applied to both driving modes.

Distortion Characteristics of Input Current under Leading Power Factor
Figure 7 shows the AC-side fundamental waveform of a system with a synchronous drive.When ωt = 0, the polarity of   * is reversed from negative to positive,   is zero, and the polarity of  Figure 8 shows the AC-side fundamental waveforms with complementary drive.When ω t = 0, the polarity of   * is reversed from negative to positive,   is zero, and the polarity of   is negative, which leads to the negative increase in   .At this moment, the polarity of   is negative.
As   * −   > 0, the current control loop causes the duty ratio dS1 of S1 to increase and the duty ratio dS2 of S2 to decrease.Based on the negative polarity of   , |  | decreases with the decrease in dS2.Once the polarity of   has reversed its polarity from negative to positive, the polarity of   reverses to negative again due to   = 0.This control places   in a discontinuous state when 0 < ωt < θ.When θ < ωt < γ and   > 0, in order to make   follow   * , ucon is clamped to zero until   =   * when ωt = γ.
The current distortion process will end at this point.The piecewise function expression of the input current is: Figure 8 shows the AC-side fundamental waveforms with complementary drive.When ωt = 0, the polarity of i * s is reversed from negative to positive, u con is zero, and the polarity of u s is negative, which leads to the negative increase in u s .At this moment, the polarity of i s is negative.As i * s − i s > 0, the current control loop causes the duty ratio d S1 of S 1 to increase and the duty ratio d S2 of S 2 to decrease.Based on the negative polarity of u s , |i s | decreases with the decrease in d S2 .Once the polarity of i s has reversed its polarity from negative to positive, the polarity of i s reverses to negative again due to u con = 0.This control places i s in a discontinuous state when 0 < ωt < θ.When θ < ωt < γ and u s > 0, in order to make i s follow i * s , u con is clamped to zero until i s = i * s when ωt = γ.The current distortion process will end at this point.

Distortion Characteristics of Input Current under Leading Power Factor
Figure 7 shows the AC-side fundamental waveform of a system with a synchronous drive.When ωt = 0, the polarity of   * is reversed from negative to positive,   is zero, and the polarity of   is negative, which leads to the negative increase in   .The rate of increase of |  * | is larger than that of |  | in the heavy load.In order to make Figure 8 shows the AC-side fundamental waveforms with complementary drive.When ω t = 0, the polarity of   * is reversed from negative to positive,   is zero, and the polarity of   is negative, which leads to the negative increase in   .At this moment, the polarity of   is negative.
As   * −   > 0, the current control loop causes the duty ratio dS1 of S1 to increase and the duty ratio dS2 of S2 to decrease.Based on the negative polarity of   , |  | decreases with the decrease in dS2.Once the polarity of   has reversed its polarity from negative to positive, the polarity of   reverses to negative again due to   = 0.This control places   in a discontinuous state when 0 < ωt < θ.When θ < ωt < γ and   > 0, in order to make   follow   * , ucon is clamped to zero until   =   * when ωt = γ.
The current distortion process will end at this point.The piecewise function expression of the input current is: The piecewise function expression of the input current is: Let i s = i * s at ωt k = γ.γ can be expressed as: Energies 2018, 11, 2447 8 of 16 The comparison shows that the current distortion becomes more severe under synchronous driving.Therefore, the complementary drive is a more appropriate choice under a leading power factor.

Distortion Characteristics of Input Current under Lagging Power Factor
When the angle of the lagging power factor is θ under a complementary drive, there are two phase relations between the AC-side voltage and the input current according to the value of |u L | and |u s sinθ|.In Figure 9, i s goes ahead of u con .Based on the above analysis, the piecewise function expression of i s is: The comparison shows that the current distortion becomes more severe under synchronous driving.Therefore, the complementary drive is a more appropriate choice under a leading power factor.

Distortion Characteristics of Input Current under Lagging Power Factor
When the angle of the lagging power factor is θ under a complementary drive, there are two phase relations between the AC-side voltage and the input current according to the value of |uL| and |ussinθ|.In Figure 9, is goes ahead of ucon.Based on the above analysis, the piecewise function expression of is is: sin( )  Let   =   * at ωtk = γ.γ can be expressed as: Let i s = i * s at ωt k = γ.γ can be expressed as: i s lags u con as shown in Figure 10, and its piecewise function expression is:  Based on cosine law, the angle φ of ucon that lags us can be deduced:   Based on cosine law, the angle ϕ of u con that lags u s can be deduced: Let i s = 0 when ωt k = γ, yielding:

Constrain of Input Current on Filter Inductance, Input Current Amplitude, and Power Factor Angel Based on THD
Based on the above analysis, the input current zero-crossing distortion is affected by filter inductance L, input current amplitude I sm , and power factor angle θ.Therefore, the allowable range of THD restricts the value of L, I sm , and θ.
At first, the limitation of THD on L and I sm was investigated.Taking θ = 0 • as an example, Figure 11 shows the relation between current THD and L and I sm when U sm = 311 V, f = 50 Hz, and U dc = 400 V.When L was chosen from 1-6 mH, and I sm was changed from 10 to 60 A, the degree of input current distortion was aggravated with the increase in L and I sm , and the maximum THD reached 6.96%.Figure 12 shows the contour line of THD with current and inductance when U sm = 311 V, f = 50 Hz, and U dc = 400 V.The values of L and I sm can be determined based on the allowable range.For example, the shaded area in Figure 12 is the limitation on L and I sm when THD < 1.4%.It is assumed that I sm = 40 A, so 2.5 mH inductance can be selected when the THD of the current requirements are satisfied.In this case, THD was about 1.25%.In practical applications, if the THD of the equipment current is above 5%, the equipment will not be allowed to connect to the grid.Hence, the contour line of current 5% THD should be drawn and the RPC and HCC functionalities of bridgeless rectifiers should be limited in practical applications.
Energies 2018, 11, x 10 of 17 the shaded area in Figure 12 is the limitation on L and Ism when THD < 1.4%.It is assumed that Ism = 40 A, so 2.5 mH inductance can be selected when the THD of the current requirements are satisfied.In this case, THD was about 1.25%.In practical applications, if the THD of the equipment current is above 5%, the equipment will not be allowed to connect to the grid.Hence, the contour line of current 5% THD should be drawn and the RPC and HCC functionalities of bridgeless rectifiers should be limited in practical applications.the shaded area in Figure 12 is the limitation on L and Ism when THD < 1.4%.It is assumed that Ism = 40 A, so 2.5 mH inductance can be selected when the THD of the current requirements are satisfied.In this case, THD was about 1.25%.In practical applications, if the THD of the equipment current is above 5%, the equipment will not be allowed to connect to the grid.Hence, the contour line of current 5% THD should be drawn and the RPC and HCC functionalities of bridgeless rectifiers should be limited in practical applications.If the value of L and I sm are determined in the design, the range of power factor angle θ can be determined based on the allowable range of THD.This also demonstrates the relation between THD and θ.Under the conditions where I sm = 92 A, U sm = 311 V, and L = 3 mH (θ less than zero refers to input current phase leading grid voltage phase), Figure 13 can be obtained.When the current phase leads the grid voltage phase, THD increases rapidly with the leading angle.When the current lags grid voltage by about 16 • , the theorical value of THD is closer to zero because the AC-side voltage and input current are in the same phase position at this moment, and no polarity opposite exists in this period, thus avoiding current zero-crossing distortion.When the current lags grid voltage more than 16 • , THD increases with the lagging angle, but the degree is less than that when the current leads the grid voltage.The range of the power factor angle can be determined from Figure 13 to ensure THD falls within the allowable range, which actually determines the reactive compensation capacity of the bridgeless rectifier.In conclusion, the mathematical analysis of the current distortion can be used to select filter inductance, input current amplitude, and power factor angle.

Simulation and Experimental Results
A simulation model of a bridgeless rectifier was set up based on MATLAB/Simulink (9.3.0.713579 (R2017b), MathWorks, Natick, MA, USA).The simulation main parameters are shown in Table 2.In order to reduce the current distortion, the complementary drive was adopted for the simulation.Figure 14 depicts the simulation waveforms of the grid voltage and input current under a unity power factor.Voltage and current are in phase, and the current is obviously distorted at the point.The distortion angle is 0.523 radians.The current THD shown in Figure 15 is 5.11%.The theoretical value of distortion angle is 0.5438 radians, and THD theoretical value was 5.01%.Therefore, the theoretical value is basically the same as the simulation result.

Simulation and Experimental Results
A simulation model of a bridgeless rectifier was set up based on MATLAB/Simulink (9.3.0.713579 (R2017b), MathWorks, Natick, MA, USA).The simulation main parameters are shown in Table 2.In order to reduce the current distortion, the complementary drive was adopted for the simulation.Figure 14 depicts the simulation waveforms of the grid voltage and input current under a unity power factor.Voltage and current are in phase, and the current is obviously distorted at the point.The distortion angle is 0.523 radians.The current THD shown in Figure 15 is 5.11%.The theoretical value of distortion angle is 0.5438 radians, and THD theoretical value was 5.01%.Therefore, the theoretical value is basically the same as the simulation result.In order to reduce the current distortion, the complementary drive was adopted for the simulation.Figure 14 depicts the simulation waveforms of the grid voltage and input current under a unity power factor.Voltage and current are in phase, and the current is obviously distorted at the point.The distortion angle is 0.523 radians.The current THD shown in Figure 15 is 5.11%.The theoretical value of distortion angle is 0.5438 radians, and THD theoretical value was 5.01%.Therefore, the theoretical value is basically the same as the simulation result.Figure 16 shows the theoretical value of THD and the simulation value of THD under different Ism.They are basically identical through comparison.Figure 17 depicts the simulation waveforms of the grid voltage and input current when the input current led the grid voltage by 20°.UL > |Ussinθ| when the angle that the input current lagged grid voltage was 5°, and the simulation waveforms of grid voltage and input current are shown in Figure 18.UL < |Ussinθ| when the input current lagged the grid voltage by 45°.The simulation waveforms of the grid voltage and input current are shown in Figure 19.The above simulation waveforms basically conform to the theoretical analysis.Figure 16 shows the theoretical value of THD and the simulation value of THD under different I sm .They are basically identical through comparison.Figure 17 depicts the simulation waveforms of the grid voltage and input current when the input current led the grid voltage by 20 • .U L > |U s sinθ| when the angle that the input current lagged grid voltage was 5 • , and the simulation waveforms of grid voltage and input current are shown in 18. U L < |U s sinθ| when the input current lagged the grid voltage by 45 • .The simulation waveforms of the grid voltage and input current are shown in Figure 19.The above simulation waveforms basically conform to the theoretical analysis.Figure 16 shows the theoretical value of THD and the simulation value of THD under different Ism.They are basically identical through comparison.Figure 17 depicts the simulation waveforms of the grid voltage and input current when the input current led grid voltage by 20°.UL > |Ussinθ| when the angle that the input current lagged grid voltage was 5°, and the simulation waveforms of grid voltage and input current are shown in Figure 18.UL < |Ussinθ| when the input current lagged grid voltage by 45°.The simulation waveforms the grid voltage and input current are shown in Figure 19.The above simulation waveforms basically conform to the theoretical analysis.Figure 20 shows the relation between theoretical value of THD and simulation value of THD with θ under the conditions of Ism = 92 A, Usm = 311 V, and L = 3 mH.The theoretical value is basically the same as the simulation result.It should be noted that the switching frequency and the higher harmonic of its multiple were ignored when the THD was calculated.However, the smaller the THD, the larger the proportion of higher harmonic in current distortion.Therefore, when THD is closer to zero, its theoretical value is slightly less than the simulation value.Figure 20 shows the relation between theoretical value of THD and simulation value of THD with θ under the conditions of Ism = 92 A, Usm = 311 V, and L = 3 mH.The theoretical value is basically the same as the simulation result.It should be noted that the switching frequency and the higher harmonic of its multiple were ignored when the THD was calculated.However, the smaller the THD, the larger the proportion of higher harmonic in current distortion.Therefore, when THD is closer to zero, its theoretical value is slightly less than the simulation value.Figure 20 shows the relation between theoretical value of THD and simulation value of THD with θ under the conditions of I sm = 92 A, U sm = 311 V, and L = 3 mH.The theoretical value is basically the same as the simulation result.It should be noted that the switching frequency and the higher harmonic of its multiple were ignored when the THD was calculated.However, the smaller the THD, the larger the proportion of higher harmonic in current distortion.Therefore, when THD is closer to zero, its theoretical value is slightly less than the simulation value.
Figure 20 shows the relation between theoretical value of THD and simulation value of THD with θ under the conditions of Ism = 92 A, Usm = 311 V, and L = 3 mH.The theoretical value is basically the same as the simulation result.It should be noted that the switching frequency and the higher harmonic of its multiple were ignored when the THD was calculated.However, the smaller the THD, the larger the proportion of higher harmonic in current distortion.Therefore, when THD is closer to zero, its theoretical value is slightly less than the simulation value.The down-scale prototype of a bridgeless rectifier was set up with TMS320F28335 as a core controller.The parameters of this prototype are provided in Table 3. IXFH46N65X2 46-A 650-V The down-scale prototype of a bridgeless rectifier was set up with TMS320F28335 as a core controller.The parameters of this prototype are provided in Table 3. IXFH46N65X2 46-A 650-V MOSFETs, and IDW15E65D2 30-A 650-V power silicon diodes were employed throughout.Aluminum electrolyte capacitors and input inductor with a Toroidal Ferrite Core and 117 turns of 0.1 × 200 Litzy wire were also adopted in this experiment, on DC side AC side, respectively.Complementary drive mode as adopted.The downscaled prototype is shown in Figure 21.
Energies 2018, 11, x 14 of 17 MOSFETs, and IDW15E65D2 30-A 650-V power silicon diodes were employed throughout.Aluminum electrolyte capacitors and input inductor with a Toroidal Ferrite Core and 117 turns of 0.1 × 200 Litzy wire were also adopted in this experiment, on DC side AC side, respectively.Complementary drive mode as adopted.The downscaled prototype is shown in Figure 21. Figure 22 shows the waveform of us and is under a unity power factor.The zero-crossing points of is coincided with us, and is distorted based approximately on the cosine law in the period after crossing the zero point.Figure 23 shows the zoomed-in waveforms of driving signals gS1 and is of us and S1.us > 0 during the distortion period of is, whereas S1 remains in conduction in order to make ucon approximate zero.All the above experiment results satisfy the theoretical analysis.
is (2A/div) us (50V/div) Figure 22 shows the waveform of u s and i s under a unity power factor.The zero-crossing points of i s coincided with u s , and i s distorted based approximately on the cosine law in the period after crossing the zero point.Figure 23 shows the zoomed-in waveforms of driving signals g S1 and i s of u s and S 1 .u s > 0 during the distortion period of i s , whereas S 1 remains in conduction in order to make u con approximate zero.All the above experiment results satisfy the theoretical analysis.
Figure 22 shows the waveform of us and is under a unity power factor.The zero-crossing points of is coincided with us, and is distorted based approximately on the cosine law in the period after crossing the zero point.Figure 23 shows the zoomed-in waveforms of driving signals gS1 and is of us and S1.us > 0 during the distortion period of is, whereas S1 remains in conduction in order to make ucon approximate zero.All the above experiment results satisfy the theoretical analysis.Figure 24 shows the experiment waveforms of us and is under a leading power factor.is stays near zero within a period after crossing zero.us gradually turns to sine waveform after crossing zero, which satisfies the proposed theoretical analysis.Figures 25 and 26 show the experiment waveforms of us and is when the angles is lag us by 8°and 40°, respectively.When the lagging angle is 8°, UL > |Ussinθ|.When it is 40°, UL < |Ussinθ|.These experimental waveforms basically conform to the theoretical analysis and simulation waveforms.Figure 24 shows the experiment waveforms of u s and i s under a leading power factor.i s stays near zero within a period after crossing zero.u s gradually turns to sine waveform after crossing zero, which satisfies the proposed theoretical analysis.Figures 25 and 26 show the experiment waveforms of u s and i s when the angles i s lag u s by 8 • and 40 • , respectively.When the lagging angle is 8 • , U L > |U s sinθ|.When it is 40 • , U L < |U s sinθ|.These experimental waveforms basically conform to the theoretical analysis and simulation waveforms.Figure 24 shows the experiment waveforms of us and is under a leading power factor.is stays near zero within a period after crossing zero.us gradually turns to sine waveform after crossing zero, which satisfies the proposed theoretical analysis.Figures 25 and 26 show the experiment waveforms of us and is when the angles is lag us by 8°and 40°, respectively.When the lagging angle is 8°, UL > |Ussinθ|.When it is 40°, UL < |Ussinθ|.These experimental waveforms basically conform to the theoretical analysis and simulation waveforms.

Conclusions
In order to more effectively integrate the RPC and HCC capabilities into the bridgeless rectifier, the input current harmonic characteristic of bridgeless rectifier under different power factors in two driving modes is discussed in this paper.Firstly, two driving modes are analyzed.Based on the above analysis, it is concluded that the complementary drive mode is a better choice in terms of reducing the current distortion when bridgeless rectifier operates under non-unity power factor.And then, the mechanism of input current zero-crossing distortion is analyzed.Furthermore, the input current during the distortion is expressed by the piecewise function when a bridgeless rectifier operates under complementary driving mode.Based on the piecewise function, the harmonic analysis is performed.Besides, when bridgeless rectifier operates under non-unity power factor, the above analysis makes the criteria of selecting parameters including the filter inductance, input current amplitude and power factor angle be further improved.Finally, the correctness and effectiveness of proposed theory is verified through the simulation and the experiment.

Conclusions
In order to more effectively integrate the RPC and HCC capabilities into the bridgeless rectifier, the input current harmonic characteristic of bridgeless rectifier under different power factors in two driving modes is discussed in this paper.Firstly, two driving modes are analyzed.Based on the above analysis, it is concluded that the complementary drive mode is a better choice in terms of reducing the current distortion when bridgeless rectifier operates under non-unity power factor.And then, the mechanism of input current zero-crossing distortion is analyzed.Furthermore, the input current during the distortion is expressed by the piecewise function when a bridgeless rectifier operates under complementary driving mode.Based on the piecewise function, the harmonic analysis is performed.Besides, when bridgeless rectifier operates under non-unity power factor, the above analysis makes the criteria of selecting parameters including the filter inductance, input current amplitude and power factor angle be further improved.Finally, the correctness and effectiveness of proposed theory is verified through the simulation and the experiment.

Figure 1 .
Figure 1.Main topology of the bridgeless rectifier and its four operation modes: (a) Main topology of the bridgeless rectifier; (b) Mode I; (c) Mode II; (d) Mode III; (e) Mode IV.

Figure 3 .
Figure 3. Block diagram for a synchronous drive.

Figure 4 .
Figure 4. Simulation current waveform on the alternating current (AC) side based on a synchronous drive without an absolute value module.

Figure 2 .
Figure 2. Block diagram of the complementary drive.

Figure 3 .
Figure 3. Block diagram for a synchronous drive.

Figure 4 .
Figure 4. Simulation current waveform on the alternating current (AC) side based on a synchronous drive without an absolute value module.

Figure 3 .
Figure 3. Block diagram for a synchronous drive.

Figure 3 .
Figure 3. Block diagram for a synchronous drive.

Figure 4 .
Figure 4. Simulation current waveform on the alternating current (AC) side based on a synchronous drive without an absolute value module.

Figure 4 .
Figure 4. Simulation current waveform on the alternating current (AC) side based on a synchronous drive without an absolute value module.

Figure 5 .
Figure 5. Phasor diagram on the AC side under unity power factor.

Figure 6
Figure 6 displays an AC-side phasor diagram under a unity power factor.Considering the symmetry, only the half-cycle waveform is analyzed.

Figure 6 .
Figure 6.Expected waveforms and actual waveforms of the AC-side fundamental voltage and current of bridgeless rectifier under a unity power factor.

Figure 5 .
Figure 5. Phasor diagram on the AC side under unity power factor.

Figure 6
Figure 6 displays an AC-side phasor diagram under a unity power factor.Considering the symmetry, only the half-cycle waveform is analyzed.

Figure 5 .
Figure 5. Phasor diagram on the AC side under unity power factor.

Figure 6
Figure 6 displays an AC-side phasor diagram under a unity power factor.Considering the symmetry, only the half-cycle waveform is analyzed.

Figure 6 .
Figure 6.Expected waveforms and actual waveforms of the AC-side fundamental voltage and current of bridgeless rectifier under a unity power factor.

Figure 6 .
Figure 6.Expected waveforms and actual waveforms of the AC-side fundamental voltage and current of bridgeless rectifier under a unity power factor.

Figure 7 .
Figure 7. Expected waveforms and actual waveforms of the AC-side fundamental voltage and current with synchronous drive under a leading power factor.

Figure 8 .
Figure 8. Expected waveforms and actual waveforms of AC side fundamental voltage and current with complementary drive under leading power factor.

Figure 7 .
Figure 7. Expected waveforms and actual waveforms of the AC-side fundamental voltage and current with synchronous drive under a leading power factor.

Figure 7 .
Figure 7. Expected waveforms and actual waveforms of the AC-side fundamental voltage and current with synchronous drive under a leading power factor.

Figure 8 .
Figure 8. Expected waveforms and actual waveforms of AC side fundamental voltage and current with complementary drive under leading power factor.

Figure 8 .
Figure 8. Expected waveforms and actual waveforms of AC side fundamental voltage and current with complementary drive under leading power factor.

Figure 9 .
Figure 9. Expected waveforms and actual waveforms of AC-side fundamental voltage and current under a lagging power factor (UL > |Ussinθ|).

Figure 9 .
Figure 9. Expected waveforms and actual waveforms of AC-side fundamental voltage and current under a lagging power factor (U L > |U s sinθ|).

Figure 10 .
Figure 10.Expected waveforms and actual waveforms of AC side fundamental voltage and current under lagging power factor (UL < |Ussinθ|).

Figure 10 .
Figure 10.Expected waveforms and actual waveforms of AC side fundamental voltage and current under lagging power factor (U L < |U s sinθ|).

Figure 11 .
Figure 11.Three-dimensional (3D) diagram of current total harmonic distortion (THD) under a unity power factor.

Figure 12 .
Figure 12.Contour line of current THD under a unity power factor.If the value of L and Ism are determined in the design, the range of power factor angle θ can be determined based on the allowable range of THD.This also demonstrates the relation between THD and θ.Under the conditions where Ism = 92 A, Usm = 311 V, and L = 3 mH (θ less than zero refers to

Figure 11 .
Figure 11.Three-dimensional (3D) diagram of current total harmonic distortion (THD) under a unity power factor.

Figure 11 .
Figure 11.Three-dimensional (3D) diagram of current total harmonic distortion (THD) under a unity power factor.

Figure 12 .
Figure 12.Contour line of current THD under a unity power factor.If the value of L and Ism are determined in the design, the range of power factor angle θ can be determined based on the allowable range of THD.This also demonstrates the relation between THD and θ.Under the conditions where Ism = 92 A, Usm = 311 V, and L = 3 mH (θ less than zero refers to input current phase leading grid voltage phase), Figure 13 can be obtained.When the current phase

Figure 12 .
Figure 12.Contour line of current THD under a unity power factor.

Figure 13 .
Figure 13.Relations between THD and power factor angle θ.

Figure 13 .
Figure 13.Relations between THD and power factor angle θ.

Figure 14 .
Figure 14.Simulation waveforms of grid voltage and input current under unity power factor.Figure 14.Simulation waveforms of grid voltage and input current under unity power factor.

Figure 14 . 17 Figure 15 .
Figure 14.Simulation waveforms of grid voltage and input current under unity power factor.Figure 14.Simulation waveforms of grid voltage and input current under unity power factor.Energies 2018, 11, x 12 of 17

Figure 16 .Figure 15 .
Figure 16.Theoretical and simulation THD under a unity power factor.

Figure 16 .Figure 16 .
Figure 16.Theoretical and simulation THD under a unity power factor.

Figure 19 .
Figure 19.Simulation waveforms of grid voltage and input current when is lags us by 45°.

Figure 18 .Figure 18 .Figure 19 .
Figure 18.Simulation waveforms of grid voltage and input current when i s lags u s by 5 • .

Figure 19 .
Figure 19.Simulation waveforms of grid voltage and input current when i s lags u s by 45 • .

Figure 20 .
Figure 20.Relationship between theoretical THD and simulation THD with power factor angle θ.

Figure 20 .
Figure 20.Relationship between theoretical THD and simulation THD with power factor angle θ.

Figure 22 .
Figure 22.Experiment waveforms of grid voltage and input current under unity power factor.Figure 22.Experiment waveforms of grid voltage and input current under unity power factor.

Figure 22 .Figure 23 .
Figure 22.Experiment waveforms of grid voltage and input current under unity power factor.Figure 22.Experiment waveforms of grid voltage and input current under unity power factor.Energies 2018, 11, x 15 of 17

Figure 24 .
Figure 24.Experiment waveforms of grid voltage and input current under leading power factor.

Figure 23 .
Figure 23.Zoomed-in experiment waveforms of grid voltage and input current under unity power factor.

Energies 2018, 11 , x 15 of 17 tFigure 23 .
Figure 23.Zoomed-in experiment waveforms of grid voltage and input current under unity power factor.

Figure 24 .Figure 24 .
Figure 24.Experiment waveforms of grid voltage and input current under leading power factor.

Figure 24 .Figure 25 .
Figure 24.Experiment waveforms of grid voltage and input current under leading power factor.

Figure 25 .Figure 26 .
Figure 25.Experiment waveforms of grid voltage and input current when is lags us by 8°.Figure 25.Experiment waveforms of grid voltage and input current when is lags us by 8 • .Energies 2018, 11, x 16 of 17

Figure 26 .
Figure 26.Experiment waveforms of grid voltage and input current when i s lags u s by 40 • .

Table 1 .
Four operation modes of bridgeless rectifiers.

Table 1 .
Four operation modes of bridgeless rectifiers.
depicts a block diagram for complementary drive.The output of voltage regulator is shifted to satisfy the required power factor and then given as the input current.Complementary signal g S1 , g S2 is generated in modulation as driving signals of switches S 1 , S 2 , respectively.
is negative, which leads to the negative increase in   .The rate of increase of |  * | is larger than that of |  | in the heavy load.In order to make |  | follow |  * |,   is clamped to zero until   =   * when ωt = γ.The amplitude of   * is smaller in the underloading.  = −  * can be achieved within a certain period after reversing the polarity of is.When us approaches 0, the growth rate of |  | decreases.The change rate of is is 0 when ωt = θ, |  | < |  * |.Then us reverses its polarity.To make |  | follow |  * |,   is clamped to zero until   =   * .The current distortion process will end at this point.

Table 2 .
Main parameters of the simulation.

Table 2 .
Main parameters of the simulation.
Simulation waveforms of grid voltage and input current under leading power factor.Figure17.Simulation waveforms of grid voltage and input current under leading power factor.Simulation waveforms of grid voltage and input current when is lags us by 5°.

Table 3 .
The main parameters of the experiments.

Table 3 .
The main parameters of the experiments.