A DC Short-Circuit Fault Ride Through Strategy of MMC-HVDC Based on the Cascaded Star Converter

: A modular multilevel converter based high voltage direct current (MMC-HVDC) with DC fault self-clearing is adopted to deal with the DC short-circuit fault. However, the constant power load characteristic of the sub-modules causes capacitor voltages to diverge and the converter to go out of hot standby. To address this problem, a novel DC short-circuit fault ride through strategy is proposed. According to the polarities of grid voltages, the working or blockage of the upper and lower bridge arms is chosen according to six sections to obtain a cascaded star converter. The capacitor voltages of MMC sub-modules are maintained and balanced through the control similar to the cascaded star converter. Moreover, in order not to change zero crossing, a cluster balancing control method by scaling the amplitudes of the modulated waves is proposed to balance the capacitor voltages between phase clusters. The strategy also achieves the DC Bus line-to-line equipotential and no fault current generated. With the switches of two modes (normal operation and fault ride through operation) after the fault is cleared, the power transfer of MMC-HVDC can be recovered quickly. Finally, the effectiveness of the proposed fault ride through strategy is demonstrated on the 21-level MMC-HVDC simulation model in PSCAD/EMTDC.


Introduction
Voltage sourced converter based high voltage direct current (VSC-HVDC), with the advantages of flexible control, power supply to the passive network, and high-quality output energy is widely applied in the fields of new energy grid connection, interconnection of asynchronous power grids, and long-distance electricity transmission with high capacity [1][2][3]. VSC includes two-level converter, three-level converter, and modular multilevel converter (MMC). MMC is a topology frequently used in the high-voltage large-capacity HVDC system, with the advantages of modular, extensible, and low losses and high-quality output waveform [4][5][6].
Due to the quick rise of DC fault current and difficulty in arc extinguishing, the application of DC circuit breakers is still not mature [7][8][9]. As a mechanical switch, a DC circuit breaker moves slowly, which undergoes 2-3 cycles [10,11]. And it is a too long time for switching devices of the converter to withstand high fault current impulse. Therefore, VSC-HVDC is mainly used on back-to-back occasions or occasions with underground cable, which limits the application and development of MMC-HVDC in long-distance power transmission and multi terminal direct current (MTDC).
It was proposed to replace the DC circuit breaker with the converter for its fast control capability. However, MMC with a half-bridge sub module (HBSM) cannot cut off DC fault current when the DC Figure 2 shows the uncontrolled circuit after blocking the converter when the relation of the grid voltages is e a > e b > e c . By use of the undirectional continuity of diode, capacitor is introduced into the fault path and provides reverse voltage to block fault current. The SM is equivalent to a capacitor and two diodes in series no matter which direction the current follows. Therefore, the SM with DC fault self-clearing has the ability to isolate the DC fault. When permanent fault happens, the short circuit will be blocked as long as sum of capacitor voltages of bridge arm is greater than the grid voltage. After the converter blocking, the SM capacitors don't discharge. So the MMC has an opportunity to be put on hot standby during system shutdown.
Energies 2018, 11, x 3 of 14 happens, the SMs of the converter are stopped from triggering. With the quick decline of bridge arm reactor freewheeling current, the MMC is close to an uncontrolled state. Figure 2 shows the uncontrolled circuit after blocking the converter when the relation of the grid voltages is ea > eb > ec. By use of the undirectional continuity of diode, capacitor is introduced into the fault path and provides reverse voltage to block fault current. The SM is equivalent to a capacitor and two diodes in series no matter which direction the current follows. Therefore, the SM with DC fault self-clearing has the ability to isolate the DC fault. When permanent fault happens, the short circuit will be blocked as long as sum of capacitor voltages of bridge arm is greater than the grid voltage. After the converter blocking, the SM capacitors don't discharge. So the MMC has an opportunity to be put on hot standby during system shutdown. In Figure 2, the structure of the full-bridge sub-module (FBSM) includes four insulated gate bipolar transistors (IGBTs), four antiparallel diodes and one capacitor. When the SM works, ±1 and 0 are output. Self-blocking sub-module (SBSM) has one less IGBT than FBSM, but which cannot generate −1 level when the SM works. Under normal operational conditions, T3 is always on, which is equivalent to HBSM. In fact, both FBSM and SBSM are equivalent to HBSM and do not require −1 level when the MMC-HVDC works normally. The equivalent circuits of FBSM and SBSM are the  happens, the SMs of the converter are stopped from triggering. With the quick decline of bridge arm reactor freewheeling current, the MMC is close to an uncontrolled state. Figure 2 shows the uncontrolled circuit after blocking the converter when the relation of the grid voltages is ea > eb > ec. By use of the undirectional continuity of diode, capacitor is introduced into the fault path and provides reverse voltage to block fault current. The SM is equivalent to a capacitor and two diodes in series no matter which direction the current follows. Therefore, the SM with DC fault self-clearing has the ability to isolate the DC fault. When permanent fault happens, the short circuit will be blocked as long as sum of capacitor voltages of bridge arm is greater than the grid voltage. After the converter blocking, the SM capacitors don't discharge. So the MMC has an opportunity to be put on hot standby during system shutdown.  Figure 2. The uncontrolled circuit after blocking the converter.
In Figure 2, the structure of the full-bridge sub-module (FBSM) includes four insulated gate bipolar transistors (IGBTs), four antiparallel diodes and one capacitor. When the SM works, ±1 and 0 are output. Self-blocking sub-module (SBSM) has one less IGBT than FBSM, but which cannot generate −1 level when the SM works. Under normal operational conditions, T3 is always on, which is equivalent to HBSM. In fact, both FBSM and SBSM are equivalent to HBSM and do not require −1 level when the MMC-HVDC works normally. The equivalent circuits of FBSM and SBSM are the In Figure 2, the structure of the full-bridge sub-module (FBSM) includes four insulated gate bipolar transistors (IGBTs), four antiparallel diodes and one capacitor. When the SM works, ±1 and 0 are output. Self-blocking sub-module (SBSM) has one less IGBT than FBSM, but which cannot generate −1 level when the SM works. Under normal operational conditions, T3 is always on, which is equivalent to HBSM. In fact, both FBSM and SBSM are equivalent to HBSM and do not require −1 level when the MMC-HVDC works normally. The equivalent circuits of FBSM and SBSM are the same when the MMC-HVDC are blocked. So many SM topologies similar to SBSM are proposed by scholars in order to simplify the circuit of the SM, for example CDSM, DCSM, SBSM, Hybrid SM, SDSM, SCSM, and so on. In this paper, the simplified SMs with DC fault self-clearing are referred to as 'no-negative-level sub module' (NNLSM).

Capacitor Voltage Divergence of MMC-HVDC Using the SM with DC Fault Self-Clearing
Since the capacitor of the SM with DC fault self-clearing cannot be charged for a long time, its voltage will be attenuated naturally. When the sum of capacitor voltages of bridge arm attenuates to less than the grid voltage, these capacitors are charged through the diode from the grid. The sum of capacitor voltages of the bridge arm will be maintained around the peak value of line voltage. Capacitance voltages of the SMs on a bridge arm actually have some differences. At this time, the current flowing into each SM on a bridge arm is equal, but the currents consumed by constant power loads in the SMs have some differences, resulting in capacitor voltage divergence phenomenon. These constant power loads are used for sub module control, protection, and state monitoring, as shown in Figure 3.
In addition to switching devices and a capacitor, a real circuit of an SM includes drive circuit boards, the sensors, bypass relay, control circuit board, and so on. The above components required by the low-voltage power supplies directly derived through the capacitor, and have the constant power characteristics. The above components can be equivalent to a constant power load in parallel with the capacitor in Figure 3. So capacitor voltage of a SM is written as follows during the blocked state: where U ci0 (i = 1, 2, 3, . . . , n) is the capacitor voltage of the SM before the converter is blocked, U ci is the capacitor voltage of the SM after the converter blocking, C i is the capacitance of the SM, i armi is the current flowing into the SM, and P SMi (i = 1, 2, 3, . . . , n) is power loss of the constant power load. Suppose power losses of the constant power loads and capacitances are equal between any two SMs on an upper or lower bridge arm. When the voltage difference between the two SMs exists at the initial time, the voltage difference as time goes on is accumulated as follows: where U ci , U cj (i, j = 1, 2, 3, . . . , n) are, respectively, the capacitor voltages of the two SMs after the converter blocking. ∆U c is the voltage difference between the two SMs after the converter blocking, ∆U c0 is the voltage difference between the two SMs at the initial time. It can be seen from Equation (2) that the voltage difference between any two SMs will gradually increase as time goes on. From Equation (1), the lower capacitor voltage of the SM makes the greater loss current for constant power load characteristics. On the contrary, the higher capacitor voltage of the SM makes the smaller the loss current. Capacitor voltage divergence accelerates under the integral action. same when the MMC-HVDC are blocked. So many SM topologies similar to SBSM are proposed by scholars in order to simplify the circuit of the SM, for example CDSM, DCSM, SBSM, Hybrid SM, SDSM, SCSM, and so on. In this paper, the simplified SMs with DC fault self-clearing are referred to as 'no-negative-level sub module' (NNLSM).

Capacitor Voltage Divergence of MMC-HVDC Using the SM with DC Fault Self-Clearing
Since the capacitor of the SM with DC fault self-clearing cannot be charged for a long time, its voltage will be attenuated naturally. When the sum of capacitor voltages of bridge arm attenuates to less than the grid voltage, these capacitors are charged through the diode from the grid. The sum of capacitor voltages of the bridge arm will be maintained around the peak value of line voltage. Capacitance voltages of the SMs on a bridge arm actually have some differences. At this time, the current flowing into each SM on a bridge arm is equal, but the currents consumed by constant power loads in the SMs have some differences, resulting in capacitor voltage divergence phenomenon. These constant power loads are used for sub module control, protection, and state monitoring, as shown in Figure 3.
In addition to switching devices and a capacitor, a real circuit of an SM includes drive circuit boards, the sensors, bypass relay, control circuit board, and so on. The above components required by the low-voltage power supplies directly derived through the capacitor, and have the constant power characteristics. The above components can be equivalent to a constant power load in parallel with the capacitor in Figure 3. So capacitor voltage of a SM is written as follows during the blocked state: where Uci0 (i = 1, 2, 3, …, n) is the capacitor voltage of the SM before the converter is blocked, Uci is the capacitor voltage of the SM after the converter blocking, Ci is the capacitance of the SM, iarmi is the current flowing into the SM, and PSMi (i = 1, 2, 3, …, n) is power loss of the constant power load. Suppose power losses of the constant power loads and capacitances are equal between any two SMs on an upper or lower bridge arm. When the voltage difference between the two SMs exists at the initial time, the voltage difference as time goes on is accumulated as follows: where Uci, Ucj (i, j = 1, 2, 3, …, n) are, respectively, the capacitor voltages of the two SMs after the converter blocking. Uc is the voltage difference between the two SMs after the converter blocking, Uc0 is the voltage difference between the two SMs at the initial time. It can be seen from Equation (2) that the voltage difference between any two SMs will gradually increase as time goes on. From Equation (1), the lower capacitor voltage of the SM makes the greater loss current for constant power load characteristics. On the contrary, the higher capacitor voltage of the SM makes the smaller the loss current. Capacitor voltage divergence accelerates under the integral action.   Figure 4. Due to the memory limitation of the computer, the constant power load is set relatively high to speed up the simulation process. In actual situation, the above phenomenon is completed within 30 s to 1 min. After the MMC with eight SMs on a bridge arm is blocked at 0.5 s, the capacitor voltages have been decreasing and diverging slowly due to power loss. After the sum of capacitor voltages of bridge arm decreases to peak value of line voltage around 1.2 s, capacitor voltage divergence accelerates. However, the sum of capacitor voltages of the bridge arm has being clamped around peak value of the line voltage. Since the AC breaker may be tripped for overvoltage or under voltage on some SMs, the MMC-HVDC will exit hot standby.

Simulation of capacitor voltage divergence is shown in
So when the permanent DC fault happens or the fault cannot be cleared in a short period of time, capacitor voltage divergence may happen. The SM with DC fault self-clearing has the ability to isolate the DC fault when DC fault happens, but the MMC-HVDC cannot keep hot standby for a long time, which is unfavorable to quick restarting following the clearance of DC faults. Simulation of capacitor voltage divergence is shown in Figure 4. Due to the memory limitation of the computer, the constant power load is set relatively high to speed up the simulation process. In actual situation, the above phenomenon is completed within 30 s to 1 min. After the MMC with eight SMs on a bridge arm is blocked at 0.5 s, the capacitor voltages have been decreasing and diverging slowly due to power loss. After the sum of capacitor voltages of bridge arm decreases to peak value of line voltage around 1.2 s, capacitor voltage divergence accelerates. However, the sum of capacitor voltages of the bridge arm has being clamped around peak value of the line voltage. Since the AC breaker may be tripped for overvoltage or under voltage on some SMs, the MMC-HVDC will exit hot standby.
So when the permanent DC fault happens or the fault cannot be cleared in a short period of time, capacitor voltage divergence may happen. The SM with DC fault self-clearing has the ability to isolate the DC fault when DC fault happens, but the MMC-HVDC cannot keep hot standby for a long time, which is unfavorable to quick restarting following the clearance of DC faults.

DC Short-Circuit Fault Ride Through Principle Based on the Cascaded Star Converter
In order to maintain and balance the capacitor voltages during the fault ride through, this paper proposes a DC short-circuit fault ride through strategy based on the cascaded star converter. The strategy is especially applicable to MMC-HVDC using the NNLSMs that cannot generate −1 level.
From Section 2, whether the SM with DC fault self-clearing works or not can determine the current flowing into the SM or off. This is equivalent to some virtual switches installed on the

DC Short-Circuit Fault Ride Through Principle Based on the Cascaded Star Converter
In order to maintain and balance the capacitor voltages during the fault ride through, this paper proposes a DC short-circuit fault ride through strategy based on the cascaded star converter. The strategy is especially applicable to MMC-HVDC using the NNLSMs that cannot generate −1 level.
From Section 2, whether the SM with DC fault self-clearing works or not can determine the current flowing into the SM or off. This is equivalent to some virtual switches installed on the three-phase upper and lower bridge arms of MMC. Figure 5 shows the equivalent topology of MMC using the SM with DC fault self-clearing during the fault ride through. S kp and S kn (k = a, b, c) represent the virtual switches of the upper and lower bridge arms. S kp and S kn cannot be on and off simultaneously. As small power is used to maintain and balance the capacitor voltages of the SMs, the controlled bridge arm current is near zero, which is equivalent to control the voltage of the upper or lower bridge arm near the grid voltage.
where u kn , u kp (k = a, b, c) are the output voltages of the k phase upper and lower bridge arms; e k (k = a, b, c) is the k phase grid voltage.
Energies 2018, 11, x 6 of 14 three-phase upper and lower bridge arms of MMC. Figure 5 shows the equivalent topology of MMC using the SM with DC fault self-clearing during the fault ride through. Skp and Skn (k = a, b, c) represent the virtual switches of the upper and lower bridge arms. Skp and Skn cannot be on and off simultaneously. As small power is used to maintain and balance the capacitor voltages of the SMs, the controlled bridge arm current is near zero, which is equivalent to control the voltage of the upper or lower bridge arm near the grid voltage.
where ukn, ukp (k = a, b, c) are the output voltages of the k phase upper and lower bridge arms; ek (k = a, b, c) is the k phase grid voltage. As the NNLSM only outputs +1 and 0 level, the output voltages of the upper and lower bridge arm only output positive voltage. In order to realize Equation (3), the switches are chosen as follows: where '1' represents turn-on and '0'represents turn-off.
After the DC fault is isolated, one phase upper or lower bridge arm works and the other is off according to the polarities of grid voltages. According to the phase voltage polarities, the control cases of the virtual switches Skp and Skn are shown in Figure 6. The control cases can be divided into six sections in one cycle. When the polarity is positive, all the IGBTs of the upper bridge arm are blocked and the output voltage of the lower bridge arm is controlled against grid voltage of the phase. When the polarity is negative, all the IGBTs of lower bridge arm are blocked and the output voltage of the upper bridge arm is controlled against grid voltage of the phase. As the NNLSM only outputs +1 and 0 level, the output voltages of the upper and lower bridge arm only output positive voltage. In order to realize Equation (3), the switches are chosen as follows: where '1' represents turn-on and '0'represents turn-off.
After the DC fault is isolated, one phase upper or lower bridge arm works and the other is off according to the polarities of grid voltages. According to the phase voltage polarities, the control cases of the virtual switches S kp and S kn are shown in Figure 6. The control cases can be divided into six sections in one cycle. When the polarity is positive, all the IGBTs of the upper bridge arm are blocked and the output voltage of the lower bridge arm is controlled against grid voltage of the phase. When the polarity is negative, all the IGBTs of lower bridge arm are blocked and the output voltage of the upper bridge arm is controlled against grid voltage of the phase. The third section is used as an example to analyze the state of the virtual switches during the fault ride through, shown in Figure 5. At this section, the grid voltage polarities of A, B, and C phase are positive, positive, and negative, respectively. At this time, Sap, Sbp, and Scn are equivalent to turn off, and San, Sbn, and Scp are equivalent to turn on.
The mathematical model of MMC-HVDC in the third section is rewritten as follows: where vk (k = a,b,c) is the output voltage of k phase bridge arm, Put Equations (3) and (4) into Equation (5), and for the balanced three-phase AC grid, the three equations in Equation (5) are added up to obtain Equation (6) as follows: For the DC bus pole-to-pole equipotential known from Equation (6), The MMC in the third section is equivalent to a cascaded star structure, as shown in Figure 5. Obviously, the short-circuit current does not exist. But the current of the DC bus is not completely zero. In order not to affect DC fault handling and ensure safety, a short-circuit branch can be also added at the outlet of the MMC. The branch switch K is turned off at the normal work of the MMC. Because the branch switch does not need to have arcing ability and its withstand current is very small, the cost is very low.
In the other sections, Equation (6) is similarly satisfied. So the MMC in six sections may be seen as a cascaded star structure under the fault ride through strategy.

Implementation of DC Short-Circuit Fault Ride Through Strategy Based on the Cascaded Star Converter
The control block diagram of the proposed DC short-circuit fault ride through strategy is shown in Figure 7 According to the polarity of grid voltages, the capacitor voltages of the SMs are chosen from the upper or lower bridge arms, and inputted to obtain ABCL u , as shown in Figure 8a. The third section is used as an example to analyze the state of the virtual switches during the fault ride through, shown in Figure 5. At this section, the grid voltage polarities of A, B, and C phase are positive, positive, and negative, respectively. At this time, S ap , S bp , and S cn are equivalent to turn off, and S an , S bn , and S cp are equivalent to turn on.
The mathematical model of MMC-HVDC in the third section is rewritten as follows: where v k (k = a,b,c) is the output voltage of k phase bridge arm, v k = S kn u kn − S kp u kp . Put Equations (3) and (4) into Equation (5), and for the balanced three-phase AC grid, the three equations in Equation (5) are added up to obtain Equation (6) as follows: For the DC bus pole-to-pole equipotential known from Equation (6), The MMC in the third section is equivalent to a cascaded star structure, as shown in Figure 5. Obviously, the short-circuit current does not exist. But the current of the DC bus is not completely zero. In order not to affect DC fault handling and ensure safety, a short-circuit branch can be also added at the outlet of the MMC. The branch switch K is turned off at the normal work of the MMC. Because the branch switch does not need to have arcing ability and its withstand current is very small, the cost is very low.
In the other sections, Equation (6) is similarly satisfied. So the MMC in six sections may be seen as a cascaded star structure under the fault ride through strategy.

Implementation of DC Short-Circuit Fault Ride Through Strategy Based on the Cascaded Star Converter
The control block diagram of the proposed DC short-circuit fault ride through strategy is shown in Figure 7. The result of u ABCL minus average capacitor voltage reference u cref * goes through a proportional-integral regulator PI, and d component of the grid current reference i d * is obtained for maintaining the total capacitor voltage of the working three-phase upper and lower bridge arms. u ABCL is the average capacitor voltage of the working three-phase upper and lower bridge arms.
According to the polarity of grid voltages, the capacitor voltages of the SMs are chosen from the upper or lower bridge arms, and inputted to obtain u ABCL , as shown in Figure 8a. u iLP1 , . . . , u iLPn (i = A, B, C) are the capacitor voltages of the SMs on the upper bridge arms. u iLN1 , . . . , u iLNn (i = A, B, C) are the capacitor voltages of the SMs on the lower bridge arms.
Direct current control is adopted to achieve the gird current control in Figure 7. In addition to controlling the total capacitor voltage of the working three-phase upper and lower bridge arm, the capacitor voltages of the SMs need balance. Cluster balancing control and individual balancing control are commonly adopted in the cascaded star converter. S are the switching signals used to control the switching devices of the SMs.
Cluster balancing control is used to balance the capacitor voltages between phase clusters. As is known from Figure 6, the main circuit structure changes according to the polarity of the three-phase grid voltages. The common cluster balancing control based on zero-sequence voltage or negative-sequence voltage [29,30] will change the phase angles of the modulation waves, which causes the bridge arms that cannot modulate the required voltage to withstand the grid voltage. Therefore, this paper proposes a novel cluster balancing control method in Figure 8b to slightly scale the amplitude of the modulated wave without changing the phase. u ABCL subtracts the average capacitor voltage of the working each-phase upper or lower bridge arm u AL , u BL , u CL , respectively. The results go through three proportional-integral regulators to obtain scaling factors of the modulated waves. This method results in a slight scaling of the amplitude and zero crossing positions of the modulated waves remain unchanged. The required power to maintain the capacitor voltages is small and the reassignment power required for cluster balancing control is even smaller. So the scaling does not cause the three-phase currents to grow too large. Direct current control is adopted to achieve the gird current control in Figure 7. In addition to controlling the total capacitor voltage of the working three-phase upper and lower bridge arm, the capacitor voltages of the SMs need balance. Cluster balancing control and individual balancing control are commonly adopted in the cascaded star converter. S are the switching signals used to control the switching devices of the SMs.
Cluster balancing control is used to balance the capacitor voltages between phase clusters. As is known from Figure 6, the main circuit structure changes according to the polarity of the three-phase grid voltages. The common cluster balancing control based on zero-sequence voltage or negative-sequence voltage [29,30] will change the phase angles of the modulation waves, which causes the bridge arms that cannot modulate the required voltage to withstand the grid voltage. Therefore, this paper proposes a novel cluster balancing control method in Figure 8b to slightly scale the amplitude of the modulated wave without changing the phase. ABCL u subtracts the average capacitor voltage of the working each-phase upper or lower bridge arm AL BL CL , , u u u , respectively.
The results go through three proportional-integral regulators to obtain scaling factors of the modulated waves. This method results in a slight scaling of the amplitude and zero crossing positions of the modulated waves remain unchanged. The required power to maintain the capacitor voltages is small and the reassignment power required for cluster balancing control is even smaller. So the scaling does not cause the three-phase currents to grow too large. Individual balancing control is used to balance the capacitor voltages of the SMs on one bridge arms, as shown in Figure 8c. The method is same as that of conventional three-phase cascaded star converter [31]. The average capacitor voltage of a working upper or lower bridge arm proportional-integral regulators to finely adjust pulse widths, respectively. After the DC fault is identified, all the SMs of MMC-HVDC using the SM with DC fault self-clearing are blocked first to clear the fault current quickly. Then the MMC-HVDC is switched to fault ride through mode. All the capacitor voltages during the fault ride through are maintained and balanced. And the MMC-HVDC has being connected to the grid and keeps hot standby. After the fault is cleared, the system is switched to the normal operational mode and the power transmission is recovered quickly. Individual balancing control is used to balance the capacitor voltages of the SMs on one bridge arms, as shown in Figure 8c. The method is same as that of conventional three-phase cascaded star converter [31]. The average capacitor voltage of a working upper or lower bridge arm u mL , (m = A, B, C) subtracts the capacitor voltages of the SMs, respectively. The results go through proportional-integral regulators to finely adjust pulse widths, respectively.
After the DC fault is identified, all the SMs of MMC-HVDC using the SM with DC fault self-clearing are blocked first to clear the fault current quickly. Then the MMC-HVDC is switched to fault ride through mode. All the capacitor voltages during the fault ride through are maintained and balanced. And the MMC-HVDC has being connected to the grid and keeps hot standby. After the fault is cleared, the system is switched to the normal operational mode and the power transmission is recovered quickly.

Simulation Verification
To verify the proposed DC short-circuit fault ride through strategy of MMC-HVDC based on the cascaded star converter, 21-level unilateral MMC-HVDC is built in PSCAD/EMTDC. Its SM topology adopts SBSM. The system parameters are shown in Table 1. The capacitor voltage of the SM is higher than the practical, because fewer SMs are used in the simulation model compared with that in the practical application in order to accelerate simulation. The simulation results are shown in Figure 9. A line-to-line short-circuit fault between P point and N point of DC bus is occurring at t = 2.401 s. After 2 ms, all the IGBTs of the MMC-HVDC are turned off for too large a current. The normal operational mode is closed. The DC short-circuit fault ride through strategy runs at t = 2.408 s. The interval time is in order to ensure the clearance of fault

Simulation Verification
To verify the proposed DC short-circuit fault ride through strategy of MMC-HVDC based on the cascaded star converter, 21-level unilateral MMC-HVDC is built in PSCAD/EMTDC. Its SM topology adopts SBSM. The system parameters are shown in Table 1. The capacitor voltage of the SM is higher than the practical, because fewer SMs are used in the simulation model compared with that in the practical application in order to accelerate simulation. The simulation results are shown in Figure 9. A line-to-line short-circuit fault between P point and N point of DC bus is occurring at t = 2.401 s. After 2 ms, all the IGBTs of the MMC-HVDC are turned off for too large a current. The normal operational mode is closed. The DC short-circuit fault ride through strategy runs at t = 2.408 s. The interval time is in order to ensure the clearance of fault current. The DC fault is relieved at 4 s, and the system is switched to the normal operational mode. The MMC-HVDC works in the constant DC voltage and active power mode under the normal operational mode.
After the line-to-line short-circuit fault happens, the DC current and the grid currents increase quickly, and the DC voltage is reduced to around zero in a short span of time. After all the IGBTs of the MMC-HVDC are turned off at t = 2.403 s, the DC fault current is reduced to zero quickly. Then after the DC fault ride through strategy runs at 2.408 s, the grid currents, the DC current and DC voltage still maintain near zero, which is shown in Figure 9a. This shows that the strategy does not cause short-circuit current. After the DC fault happens, the power transmission is cut off, as shown in Figure 9b. Because a little part of the power is absorbed to maintain and balance the capacitors voltages of the SMs, the active power fluctuates slightly around zero during the DC fault ride through. After the fault is relieved at 4 s, the transmission power of MMC-HVDC is recovered rapidly. The bridge arm current of A phase is on alternatively, following selection signal of the upper and lower bridge arm shown in Figure 9c. This phenomenon proves the existence of virtual switches. In Figure 9d, the capacitor voltages of the SMs balance and do not diverge during DC fault ride through. Due to the proposed cluster balancing control method, it takes a relatively short time to balance the capacitor voltages between phase clusters. Table 2 gives a detailed comparison with other strategies. After the line-to-line short-circuit fault happens, the DC current and the grid currents increase quickly, and the DC voltage is reduced to around zero in a short span of time. After all the IGBTs of the MMC-HVDC are turned off at t = 2.403 s, the DC fault current is reduced to zero quickly. Then after the DC fault ride through strategy runs at 2.408 s, the grid currents, the DC current and DC voltage still maintain near zero, which is shown in Figure 9a. This shows that the strategy does not cause short-circuit current. After the DC fault happens, the power transmission is cut off, as shown in Figure 9b. Because a little part of the power is absorbed to maintain and balance the capacitors voltages of the SMs, the active power fluctuates slightly around zero during the DC fault ride through. After the fault is relieved at 4 s, the transmission power of MMC-HVDC is recovered rapidly. The bridge arm current of A phase is on alternatively, following selection signal of the upper and lower bridge arm shown in Figure 9c. This phenomenon proves the existence of virtual switches. In Figure 9d, the capacitor voltages of the SMs balance and do not diverge during DC fault ride through. Due to the proposed cluster balancing control method, it takes a relatively short time to balance the capacitor voltages between phase clusters. Table 2 gives a detailed comparison with other strategies.

Conclusions
The SM with DC fault self-clearing can achieve DC short-circuit fault isolation. But when it may take a long time for the system to relieve the DC fault, the capacitor voltage divergence will happen on the SMs, which causes the MMC-HVDC not to keep hot standby for a long time. In this paper, it is proved that the constant power load in the SM leads to the capacitor voltage divergence. Therefore, this paper proposes a DC short-circuit fault ride through strategy of MMC-HVDC based on the cascaded star converter. The three working upper or lower bridge arms are chosen according to the grid voltage polarities, and the MMC may be seen as a cascaded star converter. Through the strategy similar to the cascaded star converter, the capacitor voltages are maintained and balanced during fault ride through. The proposed cluster balancing control by scaling the amplitude of the modulated wave does not affect the modulated wave polarity, and can balance the capacitor voltages between phase clusters without the growing three-phase currents. The effectiveness of the proposed DC short-circuit fault ride through strategy is demonstrated on simulation model in PSCAD/EMTDC.
The proposed DC short-circuit fault ride through strategy enjoys the following advantages: (a) The short-circuit current does not exist during DC short-circuit fault ride through; (b) The converter is controllable during fault ride through, which avoids the divergence of the capacitor voltages; (c) The AC breaker will not be tripped. After the fault is cleared, the power transmission is recovered quickly; and (d) The strategy can be applied to more MMC-HVDC topologies including in the topologies using the SMs with DC fault self-clearing but not generating −1 level.