Mitigation of DC Components Using Adaptive BP-PID Control in Transformless Three-Phase Grid-Connected Inverters

: Transformerless grid-connected inverters, due to their advantages of high efﬁciency, small volume and light weight, have been the subject of more research and interest in recent years. Due to the asymmetrical driving signal in pulse width modulation (PWM) caused by time-delay, zero-drift of the current sensors and imparities of the power transistors, output of the grid current contains dc component. As a result, power quality of the grid is degraded. In this paper, a dc (direct current) component suppression scheme with adaptive back-propagation (BP) neural network proportional-integral-differential (PID) control is proposed for dc component minimization. Moreover, sliding-window-double-iteration-method (SWDIM) is utilized for fast dc component extraction. Compared with the conventional method, the proposed scheme shows better performance, and the dc component can be attenuated to be within 0.5% of the rated current. grid-connected current in the stationary frame can be established. The result shows that if there are any dc components in the sensors, after been ampliﬁed by the current controller, the inverter-side output voltage will contain dc components.


Introduction
Grid-connected inverter systems are the key facilities for wind turbine generation (WTG), photovoltaic, and fuel cell power generation systems. An ideal output of the grid-connected inverter should only contain ac (alternating current) component. In practice, due to various reasons that lead to the presence of dc components in the system [1][2][3][4][5][6][7] such as (1) asymmetries in the switching behavior of power semiconductor devices, (2) existing dc components in the grid, (3) PWM duty-ratio imparities of the gate drivers, (4) turn-ON/-OFF delays on the devices, (5) asymmetries of the power transistors (such as on-state resistance, voltage drop, leakage current, etc.), and (6) dc components from voltage and current sensors, etc., there are some small amounts of dc components in the grid-side current. Since the inherent equivalent resistance of a voltage-source grid-connected inverter is very small, this will cause the saturation of distribution transformers in the grid and result in poor power quality, higher loss, line-frequency power ripple, dc-link voltage ripple and overheating issues in the power system [8,9]. Moreover, power quality of the grid is degraded, as a result, other equipment sharing the same grid may not work properly, and therefore, dc component injection to the grid should be strictly inhibited.
(1) The influences that will lead to dc components in the grid-connected system are analyzed, including turn-ON/-OFF time-delay, imparities of power transistors, unbalanced grid voltage, scaling errors of sensors. (2) Different from conventional dc component suppression methods, in this paper, to effectively and timely minimize the dc components in the grid, an adaptive back-propagation BP-PID controller is presented, in which, coefficients of PID controller are adaptively regulated on-line by the output of the BP controller. The proposed scheme combines the merits of two controllers, which show better performance in robustness, self-learning capability, and fast time response. (3) Sliding-Window-Double-Iteration-Method (SWDIM) [27][28][29], which has the advantages of easiness, fast implementation and better disturbance rejection capability, is implemented to extract the dc components from the grid-current.
This paper is arranged in four sections. In Section 2, the topology of a three-phase LCL type grid-connected inverter is demonstrated, and how the imparities of power bridge, time-delay on gate driving signals, zero-drift of the sensors and unbalanced grid voltage affect the dc components of the output-current are analyzed. Section 3 gives the proposed dc component minimization control strategy using an adaptive BP-PID controller. The speed learning coefficients of BP-PID controller are automatically regulated. Section 4 demonstrates the simulation and experimental results for the proposed scheme, and suggestions for future research work are also given. Figure 1 shows the schematic diagram of three-phase grid-connected inverter using P/Q control. With the help of grid voltage e ga , e gb and e gc , the reference grid current (i are f , i bre f and i cre f ) is calculated, e ga , e gb and e gc are the phase-voltage of the grid, respectively. L a , L b and L c are the inverter-side inductance, respectively. L ga , L gb and L gc are the grid-side inductance, respectively. i ga , i gb and i gc are the phase-current of the grid, respectively. v a , v b and v c are the inverter-side output voltage, respectively.

DC Component Injection Analysis
Energies 2018, 11, x FOR PEER REVIEW 3 of 23 detection and suppression schemes using current sensors are the simplest, most direct and efficient ways, and the main contributions of this paper are summarized as follows: (1) The influences that will lead to dc components in the grid-connected system are analyzed, including turn-ON/-OFF time-delay, imparities of power transistors, unbalanced grid voltage, scaling errors of sensors. (2) Different from conventional dc component suppression methods, in this paper, to effectively and timely minimize the dc components in the grid, an adaptive back-propagation BP-PID controller is presented, in which, coefficients of PID controller are adaptively regulated on-line by the output of the BP controller. The proposed scheme combines the merits of two controllers, which show better performance in robustness, self-learning capability, and fast time response. (3) Sliding-Window-Double-Iteration-Method (SWDIM) [27][28][29], which has the advantages of easiness, fast implementation and better disturbance rejection capability, is implemented to extract the dc components from the grid-current.
This paper is arranged in four sections. In Section 2, the topology of a three-phase LCL type gridconnected inverter is demonstrated, and how the imparities of power bridge, time-delay on gate driving signals, zero-drift of the sensors and unbalanced grid voltage affect the dc components of the output-current are analyzed. Section 3 gives the proposed dc component minimization control strategy using an adaptive BP-PID controller. The speed learning coefficients of BP-PID controller are automatically regulated. Section 4 demonstrates the simulation and experimental results for the proposed scheme, and suggestions for future research work are also given. Figure 1 shows the schematic diagram of three-phase grid-connected inverter using / P Q    symmetrical (time-delay exists), and the zero-drift error (or scaling errors) in current detection circuit varies. The ac-voltage of the grid (e ga , e gb and e gc ) are not symmetrical, also due to the noise, the current reference sometimes may contain dc component, this can also cause additional dc component at the output of point of common coupling (PCC).

DC Component Injection Due to Gate-Driving Delays
In this section, how the dc components are being influenced by device turn-ON/-OFF delays, is analyzed. Taking bipolar PWM modulation as an example, assuming that the average voltage between point O and O' (as shown in Figure 1) in the switching period is u OO , the average voltage between point A and O in the switching period is u AO , and the dc-link-voltage is u d , the on-time for power transistor VT 1 and VT 4 are t on1 , t on4 , respectively, T s is the PWM period.
To simplify the analysis, take phase-A as an example. When power transistor VT 1 switches on, the inverter output voltage u AO = u d 2 ; when power transistor VT 4 switches off, the inverter output voltage u AO = − u d 2 . Therefore, the waveform of u AO is a rectangular wave with an amplitude of u d 2 . The inverter voltage output for phase B and C are similar to those of phase A, except that each phase differs of 120 • . Line-to-line voltage for u AB , u BC and u CA can be calculated by the following equation.
The inverter output voltage of per-phase is calculated as Combing (1) with (2), rearrange them to get the following equation.
Assuming the loads for the grid are symmetrical, and the grid voltage is balanced, which means u AO + u BO + u CO = 0, so that the voltage of u OO in Figure 1 would be In the positive half-cycle of the grid, the average voltage u AO would be Solving this first-order differential equation to get the grid-connected current as Similarly, in the negative half-cycle of the ac grid, the average voltage u AO is Energies 2018, 11, 2047

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Solving the first-order differential Equation (7) to get the grid-connected current Combining (6) with (8), the grid-current i ga under normal state would be Assuming that in the positive and negative half-cycle of the ac-grid, there are time-delays ∆t 1 and ∆t 4 in the driving signal, the average voltage in (5) can be written as (10), and the average voltage in (7) can be written as (11).
Hence, in the positive half-cycle of the ac-grid, the grid-side current i ga1 is In the negative half-cycle of the ac-grid, the grid-side current i ga2 is Combing (12) with (13), the grid-current i ga considering the time-delay ∆t 1 and ∆t 4 would be Equation (14) demonstrates that if there are any asymmetries on the device turn-ON/-OFF delays, the grid-connected current i ga will change. If the time-delay of power transistor VT 1 and VT 4 are the same, ∆t 1 = ∆t 4 , there will be no dc component in the output current.

DC Component Analysis Due to Zero-Drift and Scaling Error of Current and Voltage Sensors
In grid-connected converters, the current or voltage sampling for grid-side current is necessary, yet, zero-drift current and scaling errors exist in current and voltage sensors. Figure 2 illustrates the control diagram of LCL-type grid-connected system, the grid and capacitor current are usually adopted as the current feedbacks. According to the closed-loop control diagram, a system block diagram of the grid-connected current in the stationary frame can be established. The result shows that if there are any dc components in the sensors, after been amplified by the current controller, the inverter-side output voltage will contain dc components. yet, zero-drift current and scaling errors exist in current and voltage sensors. Figure 2 illustrates the control diagram of LCL-type grid-connected system, the grid and capacitor current are usually adopted as the current feedbacks. According to the closed-loop control diagram, a system block diagram of the grid-connected current in the stationary frame can be established. The result shows that if there are any dc components in the sensors, after been amplified by the current controller, the inverter-side output voltage will contain dc components.

Scaling errors
Zero-drift errors Therefore, how to eliminate the influences caused by zero-drift or scaling errors in current sensors are the key issues. Assuming all the sensors have the same scaling error coefficient i λ and zero-drift offset  , the grid-current ga i would be: To simplify (16) for analysis, the influence of the controllers is ignored by considering In the stationary coordinate, the reference current for phase-A can be written as According to (17), dc component in phase-B and phase-C are similar with phase-A. Since all sensors have the same zero-drift current i Δ , a differential elimination method is put forward to eliminate the zero-drift current, the output current is defined by: Therefore, how to eliminate the influences caused by zero-drift or scaling errors in current sensors are the key issues. Assuming all the sensors have the same scaling error coefficient λ i and zero-drift offset , the grid-current i ga would be: To simplify (16) for analysis, the influence of the controllers is ignored by considering G(s) = H(s) = 1. In the stationary coordinate, the reference current for phase-A can be written as i * a (s) = I m w 0 s 2 +w 2 0 in frequency domain. In the formula mentioned, I m is the amplitude of the three-phase reference current and w 0 is the line angular frequency. When s = 0, the grid current at zero frequency i ga (0) represents the dc component: According to (17), dc component in phase-B and phase-C are similar with phase-A. Since all sensors have the same zero-drift current ∆i, a differential elimination method is put forward to eliminate the zero-drift current, the output current is defined by: Since, the grid-connected inverter is star-connected, from (18), the feedback grid current i ga0 , i gb0 and i gc0 without zero-drift can be derived as: From (19), the dc component caused by zero-drift in current sensors can be effectively eliminated using this differential method.

DC Component Analysis Due to the Asymmetries of Power Transistors
In an LCL-type grid-connected system, the power transistors do not always have the same characteristics, such as state-on resistance, hence the voltage drop is different, this section will analyze how dc components are affected due to the asymmetries of power transistors. Assuming the voltage-drop of power device VT 1 and VT 4 are ∆u t1 and ∆u t4 respectively, t on1 and t on4 are the device on-time for VT 1 and VT 4 , respectively. In the positive half-cycle of the grid, the average voltage u AO would be: Similarly, in the negative half-cycle of the ac-grid, the average voltage output u AO would be: Hence, combining (20) and (21), the relation between grid-side current i g and device on-time of t on1 (VT 1 ) and t on4 (VT 4 ) would be: Formula (22) indicates that if the power transistors do not always have the same characteristics, the grid-connected current will contain dc components, which is decided by the voltage-drop of power transistors.

DC Component Analysis Due to Unbalanced Grid Voltage
In utility, the operation of the PWM inverter may suffer from a short circuit fault, especially an asymmetrical short-circuit fault, which will make the phase voltage of the grid unbalanced and may further cause dc component in the grid-connected current. Unbalanced grid voltage consists of under-voltage and over-voltage imbalance. Assuming that the voltage fluctuations for three-phase coefficients are symbolize as λ a , λ b and λ c respectively, the grid voltage will be: In (23), assuming the grid voltage for u ga0 ,u gb0 and u gc0 are symmetrical and balanced, which means u ga0 + u gb0 + u gc0 = 0. Also, assuming the loads are symmetrical, as a result, the sum of load voltage u LRa + u LRb + u LRc = 0, then the voltage u OO will be written as: Considering (6), (8), (23) and (24), the grid-current i ga considering unbalanced grid voltage is: The result shows that if there is any unbalanced grid voltage, the grid-connected current will contain dc components, which are decided by the fluctuation coefficients (λ a , λ b and λ c ) of the voltage sensors.

DC Component Extraction Algorithm Using SWDIM
To realize dc component suppression, it is necessary to extract the dc component from the grid current. In this paper, a novel method to acquire dc components named SWDIM is proposed. Fundamental frequency component and harmonic component detection are presented. Assuming the grid-connected current i g can be written as: In (26), i dc is the dc component of the grid current, i ac is the ac component of the grid current. i n ,n f 1 , ϕ n are the amplitude, frequency and phase-angle of the ac signal, respectively, the integration result for i g is written in (27) as: Obviously, considering T = 1/ f 1 , the second component of (27) is 0, the dc component is determined by: From the above analysis in (28), a conclusion can be made that even if there is a large current when T = 1/ f 1 , high accuracy dc component estimation can still be achieved. In a utility, the ac frequency usually varies within a certain area, which degrades the performance of the proposed method. Considering T = 1/ f 0 and f 0 = f 1 , the integration result for grid current i g (t) is given by: From (29), the estimation error for dc component contains ac components, the amplitude is . It has to be noted that, if the difference between f 0 and f 1 is small, the value of sin(nπ f 1 / f 0 ) would also be very small. To overcome the limitations caused by frequency drift, double integration for the grid current can be accomplished. The result is shown in (30): From (30), it can be clearly seen that the dc component estimation still exists, however, the estimation error is much smaller than that in (30). This is explained in (31) as: The frequency error between fundamental frequency f 0 and drift-frequency f 1 is much smaller than the estimation error shown in (32): It can be proved that through many times of integration, the steady-state error can be greatly minimized. However, the more integration times implemented, the slower the time response for dc component suppression will be. In utility, considering the time response requirements, double integrations can satisfy our requirements.

Proposed DC Component Suppression Scheme with Adaptive BP-PID Controller
Some conventional dc component suppression scheme studies adopt a PID controller. Its coefficients are usually fixed, which is not suitable for dynamic reference, and sometimes unsuitable parameter specification will cause the instability of the system. To minimize the dc components, as well as low harmonic distortions in grid current, adaptive back-propagation (BP) neural network, which has the advantages of strong adaptation, self-learning capability and on-line parameter regulation capability, has been put forward, the proposed scheme combines the merits of the two controllers, which could achieve better performance to minimize the dc component.

DC Component Suppression Scheme with Adaptive BP-PID Control
To effectively realize dc component suppression and based on the analysis in Section 2 of how the dc component is generated, an intelligent control algorithm that utilizes an adaptive BP-PID control algorithm is illustrated in Figure 3, where the reference current is composed by two parts, one for the quasi-proportional resonance (QPR) current controller for closed-loop current tracking and the other part is composed by the output of the dc component suppression controller. The coefficients of PID controller in dc-suppression are regulated in a timely way by the output of an adaptive BP neural network. PSIM 9.1 and VS2010 are utilized to accomplish the co-Simulink work. The control algorithm is written in C-language. The power circuit topology is set up in PSIM.  As shown in Figure 3, the implementation of the proposed suppression control scheme contains three steps:  The implementation flowchart of BP-PID controller used in the simulation is illustrated in Figure 4. Firstly, to eliminate dc components caused by zero-drift of the sensors, usually, the current sensors of the inverter, by its nature, have zero drift or scaling errors when they receive a symmetrical sine wave. The output signal has a dc component. If the dc component is positive, after being corrected by a current loop controller, the correction loop causes the output of inverter producing a corresponding negative dc component, and vice versa. Using this theory, the output control method for dc components can be eliminated.

Adaptive Speed Learning BP-PID Controller Design
In Figure 5, γ is defined as the learning speed of ( ) the absolute values of the dc component are greater than the differential error, which means that the error is relatively bigger, it is needed to consider the regulation steps of the control output variable. Figure 5 illustrates the implementation flowchart based on the above analysis.

Adaptive Speed Learning BP-PID Controller Design
In Figure 5, γ is defined as the learning speed of u(k). The core objective of the adaptive BP-PID controller for dc component suppression is to find the most appropriate coefficient γ to minimize the dc component.
Assuming that there is a limitation for the difference e dc between reference dc component i dcre f and feedback dc component i dc f d , when the absolute value of dc component |de dc (k)| ≤ err max varies within a very small range, the control output u(k) should maintain its previous value. When the absolute values of the dc component are greater than the differential error, which means that the error is relatively bigger, it is needed to consider the regulation steps of the control output variable. Figure 5 illustrates the implementation flowchart based on the above analysis.

Simulation Results
To validate the correctness of the proposed system, simulation verifications were performed. The simulation verification contains two steps: (1) design of an LCL filter, (2) implementation of the proposed dc component suppression scheme.

Inverter-Side Inductance Calculation of LCL-Filter
According to the theoretical analysis [27], the expressions for maximum inverter-side inductance is: where in (33), g V is the grid voltage, 1

Simulation Results
To validate the correctness of the proposed system, simulation verifications were performed. The simulation verification contains two steps: (1) design of an LCL filter, (2) implementation of the proposed dc component suppression scheme.

Inverter-Side Inductance Calculation of LCL-Filter
According to the theoretical analysis [27], the expressions for maximum inverter-side inductance is: where in (33), V g is the grid voltage, I 1 = P e 3V g is the rated current of the inverter, ω 0 is the angular frequency of the grid, λ vL1 is the ratio between the RMS value of inverter-side inductance and filter capacitance C f , which is usually selected as 0.05. In the proposed scheme, set V g = 220 V, I 1 = P e 3V g = 3.03 A, ω 0 = 100π and λ vL1 = 0.05, L 1max can be calculated as 11.6 mH.
Similarly, the expression for minimum inverter-side inductance is: where in (34), V in is the dc-link voltage of the inverter, T sw is the switching frequency of the transistors, I 1 = P e 3V g is the RMS value of fundamental current, λ cL1 is the ripple coefficient of inverter-side inductance output current, which is usually chosen as 0.2~0.3. Set V in = 700 V, T sw = 50k, I 1 = P e 3V g = 3.03 A and λ cL1 = 0.3, L 1min can be calculated as 1.9 mH. As a result, considering the volume and efficiency of the inverter, the inverter-side inductance of the LCL filter is chosen as L 1 = 2 mH.

Capacitance Calculation of LCL-Filter
The capacitance of C f in LCL-filter will influence the reactive power. Large capacitance will increase the reactive power and the inverter-side current, moreover, switching power loss of power transistors will increase, corresponding. The expression for inverter-side capacitor is [28]: where in (35), C max is the maximum allowable capacitance, λ C is the ratio between the reactive power introduce by capacitance and the rated power output of grid-connected inverter, which is usually chosen as λ C = 5%. As a result, the maximum allowable capacitance in three-phase grid connected system is calculated as 2.19 µF. As a result, the filter capacitance C f is chosen as 2.2 µF in experiment.

Grid-Side Inductance Calculation of LCL-Filter
When the inverter-side and filter capacitance are specified, the grid-side inductance is usually chosen according to the standards in IEEE Std.929-2000 and IEEE Std-2003. The expression for minimum grid-side inductance is shown as [29]: where in (36), f sw is the switching frequency of power transistor, f r is the frequency of carrier signal, is the ratio between grid current and inverter-side voltage. Similar with the former calculation method, the grid-side inductance is calculated by (36) as L 2 = 1.08 mH, as a result, an approximate grid inductance with L 2 = 1 mH is utilized in the experiment.

Implementation of the Proposed DC Suppression Scheme
The control algorithm is written in C code in VS2010, the simulation setup is shown in Figure 3. Table 1 shows the parameter specifications. To demonstrate how dc-component are minimized, dc-components of 1.5-A in phase-A, −0.5-A in phase-B and −1-A in phase-C are given as the initial existing dc-component, respectively. The SPWM modulation technique is implemented in a current closed-loop. DC component suppression comparisons results between PID and adaptive BP-PID controller are illustrated. The comparisons are performed by the following steps: (1) Before 0.04 s, the inverter operates in grid-connected mode without suppression. The current closed-loop with conventional PID controller is implemented. The dc components of phase-A, Phase-B, and Phase-C using SWDIM are shown, respectively. (2) When the simulation time t (0.1 s < t < 0.2 s), dc component suppression using the conventional PID controller is implemented. From Figures 6-8, when given different active power, the adaptive BP-PID controller algorithm can eliminate the dc component in a short time, and the steady state value is close to 0, which proves that the adaptive BP-PID controller used is superior to the traditional PID controller in dc component suppression.
Taking Figure 7 as an example for analysis: when the active power reference P = 3.6 kW, it can be seen from Figure 7a,b that the grid-connected current obviously contains a dc-offset compared with the standard sinusoidal wave without dc-suppression control. The waveform of phase A is shifted upward and the phase B and phase C waveforms are shifted downward, indicating that the grid-connected current contains dc components.
The three-phase dc components are about 1.5, −0.5, and −1 A, respectively, which proves that the sliding window integration method can accurately extract the dc signals. When t = 0.1 s, the dc suppression loop with traditional PID controller is implemented. The grid-connected current still have large offsets, and the dc component exhibits periodic fluctuations. Although the dc component of the grid-connected current is suppressed, the suppression effect is not ideal. The dc suppression loop with adaptive BP-PID controller is put into operation at 0.2 s. The grid-connected current of the system enters a steady state after a short time, and the grid current does not contain any dc-offset. At this time, the dc component is close to 0, indicating that the dc component in the grid-connected current is minimized. From Figure 7c, taking phase-A as an example, the grid-connected current and voltage of the inverter are in phase when the system adopts a dc suppression loop with a conventional PID controller or an adaptive BP-PID controller. The grid current can still be well tracked. From Figures 6-8, when given different active power, the adaptive BP-PID controller algorithm can eliminate the dc component in a short time, and the steady state value is close to 0, which proves that the adaptive BP-PID controller used is superior to the traditional PID controller in dc component suppression.
Taking Figure 7 as an example for analysis: when the active power reference 3.6 P = kW, it can be seen from Figure 7a,b that the grid-connected current obviously contains a dc-offset compared with the standard sinusoidal wave without dc-suppression control. The waveform of phase A is shifted upward and the phase B and phase C waveforms are shifted downward, indicating that the grid-connected current contains dc components. The three-phase dc components are about 1.5, −0.5, and −1 A, respectively, which proves that the sliding window integration method can accurately extract the dc signals. When t=0.1s , the dc system enters a steady state after a short time, and the grid current does not contain any dc-offset. At this time, the dc component is close to 0, indicating that the dc component in the grid-connected current is minimized. From Figure 7c, taking phase-A as an example, the grid-connected current and voltage of the inverter are in phase when the system adopts a dc suppression loop with a conventional PID controller or an adaptive BP-PID controller. The grid current can still be well tracked.

Hardware Setup
To validate the proposed dc component minimization strategy, a 2-kVA three-phase transformer-less grid-connected inverter system hardware platform is set up. Figure 9a shows the system configuration block diagram and Figure 9b shows the hardware setup of the proposed control scheme. The red line represents the positive pole of the dc bus voltage, and conversely, the black line represents the negative pole in Figure 9a. Similarly, the yellow,green and blue lines represent Aphase, B-phase and C-phase, respectively. The power transistors IRFP460C 500 V/20 A, which are

Hardware Setup
To validate the proposed dc component minimization strategy, a 2-kVA three-phase transformer-less grid-connected inverter system hardware platform is set up. Figure 9a shows the system configuration block diagram and Figure 9b shows the hardware setup of the proposed control scheme. The red line represents the positive pole of the dc bus voltage, and conversely, the black line represents the negative pole in Figure 9a. Similarly, the yellow,green and blue lines represent A-phase, B-phase and C-phase, respectively. The power transistors IRFP460C 500 V/20 A, which are especially tailored to minimize on-state resistance, provide superior switching performance, withstand high-energy pulse in the avalanche and commutation mode are applied in the system. Since the aim of this article is to verify the correctness of the proposed controller, to guarantee the safety of the hardware configuration, experiments have been made with a relatively small current.
The parameter specifications implemented in the experiment are illustrated in Table 2 in the appendix. The switching frequency of the inverter is 15 kHz. The proposed control scheme is implemented with a 32-bit float-point TMS320F28335 DSP in the experiment, which is mainly used for fast and complicated mathematic calculations and control algorithm implementation. The execution time for the proposed algorithm is about 200 µs in total. A small Hall current sensor is set between the inverter output and the grid to measure the dc component injection to the grid. The voltage across the shunt resistor is filtered by a low-pass filter with a cut-off of 2 Hz to suppress fundamental frequency, a four-channel TDS2010B oscilloscope (Tektronix, Beaverton, OR, USA) is implemented for measuring the dc component voltage. especially tailored to minimize on-state resistance, provide superior switching performance, withstand high-energy pulse in the avalanche and commutation mode are applied in the system. Since the aim of this article is to verify the correctness of the proposed controller, to guarantee the safety of the hardware configuration, experiments have been made with a relatively small current. The parameter specifications implemented in the experiment are illustrated in Table 2 in the appendix. The switching frequency of the inverter is 15 kHz. The proposed control scheme is implemented with a 32-bit float-point TMS320F28335 DSP in the experiment, which is mainly used for fast and complicated mathematic calculations and control algorithm implementation. The execution time for the proposed algorithm is about in total. A small Hall current sensor is set between the inverter output and the grid to measure the dc component injection to the grid. The voltage across the shunt resistor is filtered by a low-pass filter with a cut-off of 2 Hz to suppress fundamental frequency, a four-channel TDS2010B oscilloscope (Tektronix, Beaverton, OR, USA) is implemented for measuring the dc component voltage.

Experimental Results
To clearly see the effectiveness of the control strategy on dc component suppression scheme, a dc component bias is superposed artificially on the reference current, via the closed-loop control, leading to a dc component in the grid-side inductance. Then the proposed control scheme is added and checked to verify the effectiveness of dc component minimization. The experimental results are shown in Figures 10 and 11, respectively.

Experimental Results
To clearly see the effectiveness of the control strategy on dc component suppression scheme, a dc component bias is superposed artificially on the reference current, via the closed-loop control, leading to a dc component in the grid-side inductance. Then the proposed control scheme is added and checked to verify the effectiveness of dc component minimization. The experimental results are shown in Figures 10 and 11, respectively. Figure 10 demonstrates the waveform of inverter-side current, in which a dc component bias of (0.2, 0.15 and −0.35 A) for aref i , bref i and cref i is superposed on the reference current, respectively, the grid current reference is 1-A. Also, as shown in Figure 10, without minimization control strategy, there are obviously dc components in the three-phase currents. The reference current of the d-axis in rotating coordinates is given by    Figure 10 demonstrates the waveform of inverter-side current, in which a dc component bias of (0.2, 0.15 and −0.35 A) for i are f , i bre f and i cre f is superposed on the reference current, respectively, the grid current reference is 1-A. Also, as shown in Figure 10, without minimization control strategy, there are obviously dc components in the three-phase currents. The reference current of the d-axis in rotating coordinates is given by i dre f = 1 A, the peak values of the three-phase grid current reference are i ga = 1.19 A, i gb = 1.14 A and i gc = 0.67 A, respectively, which demonstrates the existence of a dc component. Figure 11 shows the grid current with dc component minimization control using the adaptive BP-PID method. When the reference current of the d-axis is given by i dre f = 1 A, as shown in Figure 11a, the peak values of the three-phase grid currents are i ga = 0.999 A, i gb = 1.029 A and i gc = 1.022 A, respectively. As shown in Figure 11b, with the proposed controller, the grid current becomes more symmetrical, the current differences are 1, 30 and 22 mA, respectively, the dc component can be successfully minimized.   Table 4, with the proposed dc component minimization strategy, both the dc component and the harmonics in the three-phase currents are reduced, compared with the results shown in Table 3. Especially, the dc component has been effectively attenuated below 0.5% as defined by IEEE Standard 1547-2003. In addition, the THD has also been reduced from (7.68%, 6.81%, and 8.13%) to (6.52%, 6.38%, and 5.87%), respectively. These results have shown the effectiveness of the proposed dc component minimization control strategy.  Table 4,  Table 3. Especially, the dc component has been effectively attenuated below 0.5% as defined by IEEE Standard 1547-2003. In addition, the THD has also been reduced from (7.68%, 6.81%, and 8.13%) to (6.52%, 6.38%, and 5.87%), respectively. These results have shown the effectiveness of the proposed dc component minimization control strategy. Table 3. Harmonics and THD of the three-phase currents without the dc component suppression.  Table 4. Harmonics and THD of the three-phase currents with the dc component suppression.

Conclusions
In this paper, a dc component minimization suppression scheme in a three-phase transformer-less grid-connected system is proposed. The factors that influence dc components are analyzed in detail. SWDIM is implemented for precise dc component extraction even under frequency variation and harmonic distortion conditions. An adaptive BP-PID controller has been designed to enable the precise regulation of the dc components in stationary frame. Theoretical analysis and simulation results have proved the excellent performance of the proposed scheme. Based on a reduced small power hardware platform, experimental results have been given to verify the correctness of the proposed scheme. The proposed method can be well adopted in existing inverters for dc component minimization by adding suitable software programs. We suggest that further efforts can be concentrated on multilevel grid-connected inverters and matrix inverters.