Extraction of Junction Temperature of SiC MOSFET Module Based on Turn-On dI DS / dt

In this paper, a method of extracting the junction temperature based on the turn-on current switching rate (dIDS/dt) of silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) is proposed. The temperature dependence of dIDS/dt is analyzed theoretically, and experimentally to show that dIDS/dt increases with the rising junction temperature. In addition, other factors affecting dIDS/dt are also discussed by using the fundamental device physics equations and experiments. The result shows that the increase of the DC-link voltage VDC, the external gate resistance RG-ext, and the decrease of the driving voltage VGG can increase the temperature sensitivity of the dIDS/dt. A PCB (printed circuit board) Rogowski coil measuring circuit based on the fact that the SiC MOSFET chip temperature and dIDS/dt is estimated in a linear way is designed to obtain the junction temperature. The experimental results demonstrate that the proposed junction temperature extracting is effective.


Introduction
In recent years, power semiconductor devices such as the insulated gate bipolar transistor (IGBT) and the metal-oxide semiconductor field effect transistors (MOSFETs) have been widely applied in many industrial fields especially fields with high reliability requirements in new energy, wind power generation, and automotive and aerospace industries [1].Therefore, the reliability issues have become the focus of increasing concern.In particular, the novel wide band gap (WBG) devices, which are high electron mobility transistors such as silicon carbide (SiC) power MOSFET or gallium nitride (GaN), can significantly improve power density and conversion efficiency.However, due to the lack of related technology and the instability of the gate oxide layer, the WBG devices require significant condition monitoring to ensure its reliability [2][3][4].Studies have shown that 31% of failures in power electronic converters can be attributed to the failure of power devices while 60% of device failures are due to thermal stress.In fact, due to the different thermal expansion coefficients of several materials in power semiconductor modules, the accumulation of thermal stress will eventually lead to aging failure.In an actual operating condition, the higher the junction temperature is, the smaller the safety margin of the operation is.Additionally, the greater the junction temperature fluctuations are, the shorter the life of the thermal cycle is.Therefore, the measurement or estimation of junction temperature is essential for its condition monitoring [5,6].Obtaining this temperature in real time during the operation of the converter can effectively improve the status monitoring system of the SiC MOSFET.In addition, using the junction temperature-based control algorithm can enhance the lifetime of the module [7].The current methods for obtaining the power semiconductor junction temperature are mainly through a direct measurement method and an indirect measurement method.Direct measurement methods are based on optical and physical contact methods that use infrared cameras (IR) and thermocouples to measure the junction temperature, but they need to destroy the module package structure [8,9].This method uses an internal implanted thermistor sensor to obtain temperature, but it is limited by the accuracy and bandwidth of the sensor and the dynamic response is slow (a few milliseconds are required).This means the methods based on optical and physical contact are limited in practical industrial applications.Indirect measurement methods mainly include the RC thermal impedance model [10,11] and the thermo-sensitive electrical parameter (TSEP).The RC thermal resistance network model mainly includes the Foster and Cauer models, but they do not consider changes in the thermal impedance caused by aging, which results in the inability to obtain accurate junction temperatures.Based on the TSEP, the temperature estimation of the standard package module can be performed non-invasively without modifying the module itself and only the electrical parameters of the device need to be obtained.Many studies have found that the TSEP method is the most promising solution for monitoring the junction temperature of the module [12].The high-precision and fast-response temperature measurement of the power device can be performed, and the junction temperature can be measured online or offline using TSEP.This is a very extensive research field.Reference [13] uses the on-resistance R on to obtain the junction temperature of the IGBT.However, due to the low on-resistance of the SiC MOSFET (several tens of mΩ), a very precise measurement circuit is required and the switching frequency of the SiC MOSFET is high.It is difficult to measure the junction temperature accurately.In Reference [14], the IGBT junction temperature was measured using the Miller plateau voltage (V GP ).However, due to the high switching speed of the SiC MOSFET, the turn-on transient is only few hundred nanoseconds, which means the length of the Miller platform is very short and is difficult to measure.Reference [15] provides a method for measuring the junction temperature using the threshold voltage (V TH ) of the IGBT.Physically, V TH is the minimum gate bias inducing an inversion layer of free electrons underneath the gate oxide.It creates a conductive channel between the drain and source in MOSFET or the collector and emitter in IGBT.Since this voltage is not well defined, a quasi-threshold voltage (gate voltage of drain current reaching 10% of rated current) can only be obtained by detecting the value of the drain current.Reference [16] uses the turn-off delay of IGBT to measure the junction temperature, but SiC MOSFET is a unipolar switching device and does not include any extracting minority carriers during the turned off transient.Therefore, the junction temperature cannot be measured using the temperature sensitivity of the minority carrier during the turn off transient.Reference [17] proposed a method to obtain the junction temperature based on the peak value of the gate current I G peak during the SiC MOSFET turn-on transient.Based on the positive temperature coefficient of the internal gate resistance (R G-in ), SiC MOSFET can generate different gate currents at different temperatures.The junction temperature is extracted by obtaining the peak value of the gate current.
Reference [18] includes an analysis of the relationship between dI DS /dt and the junction temperature during the SiC MOSFET turned on and off transient.However, it lacks the experimental research on the large current module and does not design a measurement circuit to define the junction temperature.In summary, compared to silicon semiconductors, there are few studies on the junction temperature of silicon carbide semiconductors.Due to the wide bandgap characteristics of SiC MOSFET, some methods of extracting junction temperature can be used on silicon IGBT but cannot be applied to SiC MOSFET.In this paper, based on the switching characteristics of SiC MOSFET, the junction temperature is obtained by the turn-on current switching rate (dI DS /dt).Firstly, it is analyzed that the temperature sensitivity of dI DS /dt is mainly related to the negative temperature coefficient of the threshold voltage (V TH ).Second, an experimental platform was established to demonstrate the good linear relationship between dI DS /dt and the junction temperature.The effects of gate drive resistance R G , the supply voltage V DC , load current I DS , and the drive voltage V GG on dI DS /dt have been experimentally verified.Lastly, a small and economical Rogowski coil measuring Energies 2018, 11, 1951 3 of 15 circuit for obtaining the dI DS /dt is proposed.The circuit can be embedded in the SiC MOSFET driver.The feasibility of the circuit to obtain the junction temperature is verified by experiments.In practical engineering applications, considering the switching loss and frequency, an intelligent driver method is proposed to measure the junction temperature of the SiC MOSFET without increasing the switching loss.

Theoretical Analysis of Turn-On dI DS /dt Temperature Dependence
Figure 1a shows the cell structure of the planar SiC MOSFET.It can be seen that the cell of the SiC MOSFET is mainly composed of the gate, source, drain, oxide layer, N-drift region, N-base region, and Junction Field-Effect Transistor (JEFT) region.The figure also shows the route of the electron carrier flow, the position of inversion layer channel, and the distribution of parasitic capacitance.the dIDS/dt is proposed.The circuit can be embedded in the SiC MOSFET driver.The feasibility of the circuit to obtain the junction temperature is verified by experiments.In practical engineering applications, considering the switching loss and frequency, an intelligent driver method is proposed to measure the junction temperature of the SiC MOSFET without increasing the switching loss.Figure 1b shows the typical SiC MOSFET turn-on transient waveforms under an inductive load.In order to facilitate the theoretical analysis, the parasitic inductance of the switching loop is neglected [19].This switching process can be divided into four phases to analyze further.Before t0, SiC MOSFET is blocked, the driving voltage VGG = Uoff, the drain-source voltage VDS = VDC (DC-link voltage), and the gate current IG is zero.

Theoretical Analysis of
In Phase 1 (t ∈ [t0,t1]), the turn-on pulse trigger at t0, the driving voltage VGG = Uon, and the gate current IG first performs a step to its maximum value and then starts to decay.At the same time, the gate voltage VGS begins to increase.Due to the forward bias of VGS, holes in the P base region are first squeezed out to form a depletion layer.With the increase of VGS, the electrons (minority carriers) in the P base region begin to gather under the gate oxide layer to form an inversion layer channel when the energy band is bent to the surface potential, which is equal to the body potential.VGS rises to the threshold voltage VTH when the inversion layer channel is formed at t1. tTH is the turn-on delay time.When initiating the turn-on until VGS reaches VTH, it can be calculated by using Equation (1) where RG is the gate total resistance and CISS is the input capacitance.The expression for VTH can be obtained from reference [18] where q is the charge constant, VFB is the flat-band voltage (related to the oxide layer and semiconductor interface charge and gate material), ξsic is the dielectric constant of the semiconductor, and NA is the doping concentration.COX is the oxide layer capacitance, T is the absolute temperature (thermodynamic temperature), the Fermi potential ΨB is the potential difference between the mid-gap and the Fermi level far from the surface, and К is the Boltzmann constant.Figure 1b shows the typical SiC MOSFET turn-on transient waveforms under an inductive load.In order to facilitate the theoretical analysis, the parasitic inductance of the switching loop is neglected [19].This switching process can be divided into four phases to analyze further.Before t 0 , SiC MOSFET is blocked, the driving voltage V GG = U off , the drain-source voltage V DS = V DC (DC-link voltage), and the gate current I G is zero.
In Phase 1 (t ∈ [t 0 ,t 1 ]), the turn-on pulse trigger at t 0 , the driving voltage V GG = U on , and the gate current I G first performs a step to its maximum value and then starts to decay.At the same time, the gate voltage V GS begins to increase.Due to the forward bias of V GS , holes in the P base region are first squeezed out to form a depletion layer.With the increase of V GS , the electrons (minority carriers) in the P base region begin to gather under the gate oxide layer to form an inversion layer channel when the energy band is bent to the surface potential, which is equal to the body potential.V GS rises to the threshold voltage V TH when the inversion layer channel is formed at t 1 .t TH is the turn-on delay time.When initiating the turn-on until V GS reaches V TH , it can be calculated by using Equation (1) where R G is the gate total resistance and C ISS is the input capacitance.The expression for V TH can be obtained from reference [18] where q is the charge constant, V FB is the flat-band voltage (related to the oxide layer and semiconductor interface charge and gate material), ξ sic is the dielectric constant of the semiconductor, and N A is the doping concentration.C OX is the oxide layer capacitance, T is the absolute temperature (thermodynamic temperature), the Fermi potential ψ B is the potential difference between the mid-gap and the Fermi level far from the surface, and K is the Boltzmann constant.
Using Equation (3), it can be seen that ψ B is related to the doping concentration and temperature of the semiconductor and n i is the concentration of the carrier.If the start time of turn-on is 0, the changing rate of the gate voltage can be calculated by using the equation below.
) is the inversion layer channel established at time t 1 .The electron carriers start to enter in the JFET region and the drain-source current I DS starts to increase.When I DS reaches the rated current, the freewheeling diode starts to reverse recovery and the I DS reaches its maximum value at time t 2 .Due to the influence of the parasitic inductance between the drain and source, the drain-source voltage V DS drops by a small step, but since V DS >> (V GG −V TH ), SiC MOSFET is in the saturation region, which means the expression of the drain current I DS can be calculated by using the following equation: In the above equations, β is the gain coefficient, W CH is the channel width of the inversion layer, µ CH is the effective mobility of the channel electrons, C OX is the capacitance of the oxide layer, and L is the channel length.The current switching rate dI DS /dt can be calculated together with Equation (4) and the derivative of Equation ( 5), which is shown below.
In Phase 3 (t ∈ [t 2 ,t 3 )), when the drain-source current I DS reaches the maximum value at time t 2 , the gate voltage V GS rises to the Miller plateau voltage V GP , V GS remains basically unchanged, and I DS starts to fall to the rated current.After the reverse recovery of the freewheeling diode is complete, the gate current I G charges to the Miller capacitance reversely.At the same time, the drain-source voltage V DS begins to drop and drops to a very low on-state voltage at t 3 .The Miller plateau stage ends.
In Phase 4 (t ∈ [t 3 ,t 4 )), the gate capacitance C GS is charged by the gate current I G after t 3 .V GS starts to increase exponentially and rises to the driving voltage V GG at t 4 .In addition, I G decreases to zero.At the end of this phase, the SiC MOSFET is fully turned on.
From the SiC MOSFET turn-on process, it can be seen that temperature-related factors include the threshold voltage V TH and the drain current change rate dI DS /dt.When Equations ( 2) and (3) are combined, the temperature is derived to obtain Equation (8).From Equation (2), the threshold voltage V TH is a function of temperature.As the temperature is raised, the band bending (2ψ B ) required to induce an inversion layer decreases due to the rapid increase in the intrinsic carrier concentration (n i ) in Equation (3).This is partially offset by the temperature pre-factor (KT) and the increased ionization of acceptors N A when the temperature is raised.However, as the temperature rises, the Fermi level moves closer to the mid-gap.Therefore, the band bending (2ψ B ) needed to reach the threshold decreases.This reduces the threshold voltage, which is shown in Equation (2) [20].Therefore, the threshold voltage decreases with an increasing temperature and shows a negative temperature coefficient.
The derivation of the temperature is obtained by using Equation (7).
From Equation ( 9), it can be concluded that the temperature coefficient of dI DS /dt is related to the gate threshold voltage V TH and the temperature coefficient of the gain coefficient β.Based on Equation ( 6), the gain coefficient β is proportional to the channel width W CH , the effective mobility of the channel µ CH , and the oxide capacitance C OX , but is inversely proportional to channel length L. W CH , µ CH , and C OX are related to the manufacturer's process and are constant under the same module, which means β only relates to µ CH .In the silicon semiconductor, µ CH is about half of the mobility of the drift region while, in 4H-SiC, µ CH is only 5-10% of the mobility of the drift region.It is mainly affected by the surface roughness scattering, Coulomb scattering, and phonon scattering of the semiconductor and oxide interfaces [21].The main effect of µ CH is Coulomb scattering at room temperature.As the temperature increases, the surface roughness scattering and Coulomb scattering decrease and a large number of phonon scattering increases, which results in a decrease of the carrier mobility.Therefore, µ CH decreases with an increasing temperature.From Equation ( 6), β displays a negative temperature coefficient, but due to the wide bandgap characteristics of SiC MOSFET, µ CH is very low and the temperature sensitivity of β is also low.Therefore, the negative temperature coefficient of V TH dominates the negative temperature coefficient of β [21].The temperature coefficient of dI DS /dt ((dI DS ) 2 ⁄(dt•dT)) is mainly affected by the threshold voltage V TH .
Reference [22] proposed that the input capacitor C ISS is also affected by the temperature because C ISS includes Miller capacitance and gate capacitance C GS where the gate capacitance C GS does not change with temperature.The Miller capacitance is composed of the oxide layer capacitance C OX and depletion layer capacitance C dep .In general, C OX does not change with the temperature.The expression of C dep is shown in the equation below.
In Equation (10), A is the effective area of the capacitor area, ξ sic is the dielectric constant, q is the unit charge, N D , N A is the doping concentration of the donor and acceptor, and V DS is the drain voltage of SiC MOSFET.When the temperature rises, the doping concentration increases, and the Miller capacitance increases with a rise in temperature.It shows a positive temperature coefficient.However, since the rise of the drain-source current I DS mainly occurs in Phase 2 (t 1 , t 2 ), the drain voltage V DS is large during this period, which means the depletion capacitance C dep is small.The Miller capacitance is mainly the oxide capacitance C OX [20].Therefore, the temperature effect of the input capacitor C ISS can be ignored.
In summary, due to the negative temperature coefficient of the threshold voltage (a negative sign before dV TH /dT in Equation ( 9)), the turn-on dI DS /dt shows a positive temperature coefficient and the SiC MOSFET turns on faster at a higher temperature.

Relationship between dI DS /dt and Junction Temperature
In order to demonstrate dI DS /dt temperature dependence, a 1.2 kV, 180 A SiC MOSFET module (BSM180D12P2C101, ROHM Semiconductor, Kyoto, Japan) [23] was used to build a double pulse experimental platform, which is shown in Figure 2. The module has two SiC MOSFETs switches in series including one as a test device and the other as a freewheeling diode (D 1 ).The module has a parasitic inductance L S between source S and auxiliary source S' and it can be seen that L S is 13 nH from the manual.In the experiment, the DC-link voltage was measured using a high-voltage differential probe (N2891A, Agilent Technologies, Santa Clara, CA, USA) and the drain current was measured using a Rogowski coil (CWTMini1B, PEM, Nottingham, UK).The oscilloscope used for capturing the data was Agilent MSO8064A with a bandwidth of 600 MHz.The SiC MOSFET module is placed on the adjustable heating plate and coated with thermal grease on the substrate.The substrate of the module is closely attached to the heating plate and each temperature is adjusted.The heating process takes a long time in order for the junction temperature (T j ) of the chip can be considered equal to the temperature of the heating plate.Each experiment is performed from a low temperature to a high temperature, which ensures that there is no heat wasted inside the chip.In addition, it improves the measurement accuracy.The experimental circuit is shown in Figure 3.In order to demonstrate dIDS/dt temperature dependence, a 1.2 kV, 180 A SiC MOSFET module (BSM180D12P2C101, ROHM Semiconductor, Kyoto, Japan) [23] was used to build a double pulse experimental platform, which is shown in Figure 2. The module has two SiC MOSFETs switches in series including one as a test device and the other as a freewheeling diode (D1).The module has a parasitic inductance LS between source S and auxiliary source S' and it can be seen that LS is 13 nH from the manual.In the experiment, the DC-link voltage was measured using a high-voltage differential probe (N2891A, Agilent Technologies, Santa Clara, CA, USA) and the drain current was measured using a Rogowski coil (CWTMini1B, PEM, Nottingham, UK).The oscilloscope used for capturing the data was Agilent MSO8064A with a bandwidth of 600 MHz.The SiC MOSFET module is placed on the adjustable heating plate and coated with thermal grease on the substrate.The substrate of the module is closely attached to the heating plate and each temperature is adjusted.The heating process takes a long time in order for the junction temperature (Tj) of the chip can be considered equal to the temperature of the heating plate.Each experiment is performed from a low temperature to a high temperature, which ensures that there is no heat wasted inside the chip.In addition, it improves the measurement accuracy.The experimental circuit is shown in Figure 3.  4. It can be seen that the dIDS/dt of 150 °C is greater than 60 °C.Therefore, the dIDS/dt increases when the temperature is raised due to the negative temperature sensitivity of the threshold voltage VTH.In addition, at higher temperatures, the inversion layer forms earlier and the drain-source current IDS takes the shortest time to reach the rated current.At the same time, the intrinsic carrier concentration increases with a rising temperature, more carriers flow through the channel, and dIDS/dt becomes larger.Therefore, dIDS/dt shows a positive temperature coefficient, which is consistent with the above theoretical analysis during the turn on In order to demonstrate dIDS/dt temperature dependence, a 1.2 kV, 180 A SiC MOSFET module (BSM180D12P2C101, ROHM Semiconductor, Kyoto, Japan) [23] was used to build a double pulse experimental platform, which is shown in Figure 2. The module has two SiC MOSFETs switches in series including one as a test device and the other as a freewheeling diode (D1).The module has a parasitic inductance LS between source S and auxiliary source S' and it can be seen that LS is 13 nH from the manual.In the experiment, the DC-link voltage was measured using a high-voltage differential probe (N2891A, Agilent Technologies, Santa Clara, CA, USA) and the drain current was measured using a Rogowski coil (CWTMini1B, PEM, Nottingham, UK).The oscilloscope used for capturing the data was Agilent MSO8064A with a bandwidth of 600 MHz.The SiC MOSFET module is placed on the adjustable heating plate and coated with thermal grease on the substrate.The substrate of the module is closely attached to the heating plate and each temperature is adjusted.The heating process takes a long time in order for the junction temperature (Tj) of the chip can be considered equal to the temperature of the heating plate.Each experiment is performed from a low temperature to a high temperature, which ensures that there is no heat wasted inside the chip.In addition, it improves the measurement accuracy.The experimental circuit is shown in Figure 3.  4. It can be seen that the dIDS/dt of 150 °C is greater than 60 °C.Therefore, the dIDS/dt increases when the temperature is raised due to the negative temperature sensitivity of the threshold voltage VTH.In addition, at higher temperatures, the inversion layer forms earlier and the drain-source current IDS takes the shortest time to reach the rated current.At the same time, the intrinsic carrier concentration increases with a rising temperature, more carriers flow through the channel, and dIDS/dt becomes larger.Therefore, dIDS/dt shows a positive temperature coefficient, which is consistent with the above theoretical analysis during the turn on • C is greater than 60 • C. Therefore, the dI DS /dt increases when the temperature is raised due to the negative temperature sensitivity of the threshold voltage V TH .In addition, at higher temperatures, the inversion layer forms earlier and the drain-source current I DS takes the shortest time to reach the rated current.At the same time, the intrinsic carrier concentration increases with a rising temperature, more carriers flow through the channel, and dI DS /dt becomes larger.Therefore, dI DS /dt shows a positive temperature coefficient, which is consistent with the above theoretical analysis during the turn on transient.In the experiment, the voltage of the parasitic inductance L S between the auxiliary source S' and the source S is measured, which is shown in Figure 5.It can be seen that the peak value of V S'S increases with an increasing temperature and shows a better linear relationship.The dI DS /dt can be obtained by Equation (11).The voltage V S'S is 1.6 V at 75 • C and 1.9 V at 150 • C. Therefore, it has a difference of 300 millivolts.The resolution of V S'S is 4 mV/ • C and the junction temperature can be obtained in real time by using Equation ( 12) where K 0 is the temperature resolution.This is related to the manufacturer's production process and product type.V S S | T 0 is the V S'S value at temperature T 0 .
Energies 2018, 11, x FOR PEER REVIEW 7 of 15 transient.In the experiment, the voltage of the parasitic inductance LS between the auxiliary source S' and the source S is measured, which is shown in Figure 5.It can be seen that the peak value of VS'S increases with an increasing temperature and shows a better linear relationship.The dIDS/dt can be obtained by Equation (11).The voltage VS'S is 1.6 V at 75 °C and 1.9 V at 150 °C.Therefore, it has a difference of 300 millivolts.The resolution of VS'S is 4 mV/°C and the junction temperature can be obtained in real time by using Equation (12) where K0 is the temperature resolution.This is related to the manufacturer's production process and product type.SʹS T V | 0 is the VS'S value at T0.

Influence of Other Factors on dIDS/dt
If dIDS/dt is used as the parameter of TSEP for SiC MOSFET condition monitoring, its relationship with other parameters must be calibrated.The temperature sensitivity of dIDS/dt needs to be removed from these factors in order to be used for the junction temperature detection.From Equations ( 7) and ( 9), it is clearly shown that the factors affecting the dIDS/dt are gate resistance RG, the DC-link voltage

Influence of Other Factors on dIDS/dt
If dIDS/dt is used as the parameter of TSEP for SiC MOSFET condition monitoring, its relationship with other parameters must be calibrated.The temperature sensitivity of dIDS/dt needs to be removed from these factors in order to be used for the junction temperature detection.From Equations ( 7) and ( 9), it is clearly shown that the factors affecting the dIDS/dt are gate resistance RG, the DC-link voltage

Influence of Other Factors on dI DS /dt
If dI DS /dt is used as the parameter of TSEP for SiC MOSFET condition monitoring, its relationship with other parameters must be calibrated.The temperature sensitivity of dI DS /dt needs to be removed from these factors in order to be used for the junction temperature detection.From Equations ( 7) and ( 9), it is clearly shown that the factors affecting the dI DS /dt are gate resistance R G , the DC-link voltage V DC , the load current, the gate voltage V GG , and the junction temperature T j .The relationship between them is shown in Figure 6.The current change rate dI DS /dt increases when the junction temperature T j , the drive voltage V GG , and the DC-link voltage V DC increase.However, dI DS /dt decreases with increasing gate resistance R G .The load current cannot be determined by using the formula.The following experiments are used to verify their relationship.

Effect of Load Current and DC-link Voltage on dIDS/dt
The effect of the load current on the temperature sensitivity of dIDS/dt was analyzed in the doublepulse experiment, and the load current can be adjusted by changing the pulse duration of the turnon voltage VGG.The experiments were performed at the DC-link voltage VDC = 350 V, the driving resistance RG-ext = 60 Ω, the junction temperature Tj = 150 °C, and a range of load current from 50 A to 160 A. The experimental waveform is shown in Figure 7.It can be seen that dIDS/dt did not change substantially under the different current at the same temperatures.Figure 8 shows that, at the same current, the higher the temperature is, the greater the dIDS/dt is and the better linearity is.Therefore, dIDS/dt is not disturbed by the fluctuation of the load current and it is beneficial to use it as TSEP for the junction temperature extraction of the SiC MOSFET under practical conditions.

Effect of Load Current and DC-link Voltage on dI DS /dt
The effect of the load current on the temperature sensitivity of dI DS /dt was analyzed in the double-pulse experiment, and the load current can be adjusted by changing the pulse duration of the turn-on voltage V GG .The experiments were performed at the DC-link voltage V DC = 350 V, the driving resistance R G-ext = 60 Ω, the junction temperature T j = 150 • C, and a range of load current from 50 A to 160 A. The experimental waveform is shown in Figure 7.It can be seen that dI DS /dt did not change substantially under the different current at the same temperatures.Figure 8 shows that, at the same current, the higher the temperature is, the greater the dI DS /dt is and the better linearity is.Therefore, dI DS /dt is not disturbed by the fluctuation of the load current and it is beneficial to use it as TSEP for the junction temperature extraction of the SiC MOSFET under practical conditions.
In order to verify the effect of the DC-link voltage V DC on the SiC MOSFET, the temperature of SiC MOSFET is kept constant at 150 • C and the drain-source current I DS = 80 A at a steady state.Double-pulse experiments were performed at different DC-link voltages (100 V, 120 V, 180 V, 200 V, 250 V, and 380 V), respectively.The turn-on I DS and V DS waveforms are shown in Figure 9.It can be seen that, at the same temperature and rated current, there is only a slight increase in dI DS /dt of the DC-link voltage with a difference of 280 V.The voltage V S'S induced by parasitic inductance L S is measured and shown in Figure 10.It can be seen that the peak value of V S'S is also a slight increase with the increase of V DC , which means that dI DS /dt increases slightly with V DC .As the DC-link voltage increases, more charges are discharged in the N-drift region increasing the depletion layer width.This will also decrease the depletion layer capacitance C dep .Based on Equation (10), it can also be seen that C dep decreases with increasing DC-link voltage.Therefore, the Miller capacitance is reduced by increasing V DC , which, in turn, reduces the input capacitance C ISS and speeds up the turn-on transient of the SiC MOSFET.However, C dep is small in this stage (in Phase 2, the drain voltage V DS is large) and dI DS /dt shows a slight increase.However, the DC-link voltage V DC is often constant in voltage source converter applications, which means the influence of V DC on dI DS /dt is less important.The dI DS /dt temperature coefficient is usually calibrated to accommodate different DC-link voltages in a new operating environment.In addition, the slight fluctuation of the DC-link voltage has little effect on pulse experiment, and the load current can be adjusted by changing the pulse duration of the turnon voltage VGG.The experiments were performed at the DC-link voltage VDC = 350 V, the driving resistance RG-ext = 60 Ω, the junction temperature Tj = 150 °C, and a range of load current from 50 A to 160 A. The experimental waveform is shown in Figure 7.It can be seen that dIDS/dt did not change substantially under the different current at the same temperatures.Figure 8 shows that, at the same current, the higher the temperature is, the greater the dIDS/dt is and the better linearity is.Therefore, dIDS/dt is not disturbed by the fluctuation of the load current and it is beneficial to use it as TSEP for the junction temperature extraction of the SiC MOSFET under practical conditions.pulse experiment, and the load current can be adjusted by changing the pulse duration of the turnon voltage VGG.The experiments were performed at the DC-link voltage VDC = 350 V, the driving resistance RG-ext = 60 Ω, the junction temperature Tj = 150 °C, and a range of load current from 50 A to 160 A. The experimental waveform is shown in Figure 7.It can be seen that dIDS/dt did not change substantially under the different current at the same temperatures.Figure 8 shows that, at the same current, the higher the temperature is, the greater the dIDS/dt is and the better linearity is.Therefore, dIDS/dt is not disturbed by the fluctuation of the load current and it is beneficial to use it as TSEP for the junction temperature extraction of the SiC MOSFET under practical conditions.In order to verify the effect of the DC-link voltage VDC on the SiC MOSFET, the temperature of SiC MOSFET is kept constant at 150 °C and the drain-source current IDS = 80 A at a steady state.Double-pulse experiments were performed at different DC-link voltages (100 V, 120 V, 180 V, 200 V, 250 V, and 380 V), respectively.The turn-on IDS and VDS waveforms are shown in Figure 9.It can be seen that, at the same temperature and rated current, there is only a slight increase in dIDS/dt of the DC-link voltage with a difference of 280 V.The voltage VS'S induced by parasitic inductance LS is measured and shown in Figure 10.It can be seen that the peak value of VS'S is also a slight increase with the increase of VDC, which means that dIDS/dt increases slightly with VDC.As the DC-link voltage increases, more charges are discharged in the N-drift region increasing the depletion layer width.This will also decrease the depletion layer capacitance Cdep.Based on Equation (10), it can also be seen that Cdep decreases with increasing DC-link voltage.Therefore, the Miller capacitance is reduced by increasing VDC, which, in turn, reduces the input capacitance CISS and speeds up the turn-on transient of the SiC MOSFET.However, Cdep is small in this stage (in Phase 2, the drain voltage VDS is large) and dIDS/dt shows a slight increase.However, the DC-link voltage VDC is often constant in voltage source converter applications, which means the influence of VDC on dIDS/dt is less important.The dIDS/dt temperature coefficient is usually calibrated to accommodate different DC-link voltages in a new operating environment.In addition, the slight fluctuation of the DC-link voltage has little effect on the dIDS/dt in the actual operating conditions, which also facilitates the use of the dIDS/dt as a TESP parameter for junction temperature extraction.

The Effect of Drive Resistance on dIDS/dt
As known in silicon MOSFETs and IGBTs, the external drive resistance (RG-ext) also affects the turn-on dIDS/dt of SiC MOSFET.In order to observe the effect of the RG-ext on dIDS/dt, the heating plates were adjusted to 50 °C, 75 °C, 100 °C, 125 °C, and 150°C, respectively.Each adjustment waits for one In order to verify the effect of the DC-link voltage VDC on the SiC MOSFET, the temperature of SiC MOSFET is kept constant at 150 °C and the drain-source current IDS = 80 A at a steady state.Double-pulse experiments were performed at different DC-link voltages (100 V, 120 V, 180 V, 200 V, 250 V, and 380 V), respectively.The turn-on IDS and VDS waveforms are shown in Figure 9.It can be seen that, at the same temperature and rated current, there is only a slight increase in dIDS/dt of the DC-link voltage with a difference of 280 V.The voltage VS'S induced by parasitic inductance LS is measured and shown in Figure 10.It can be seen that the peak value of VS'S is also a slight increase with the increase of VDC, which means that dIDS/dt increases slightly with VDC.As the DC-link voltage increases, more charges are discharged in the N-drift region increasing the depletion layer width.This will also decrease the depletion layer capacitance Cdep.Based on Equation (10), it can also be seen that Cdep decreases with increasing DC-link voltage.Therefore, the Miller capacitance is reduced by increasing VDC, which, in turn, reduces the input capacitance CISS and speeds up the turn-on transient of the SiC MOSFET.However, Cdep is small in this stage (in Phase 2, the drain voltage VDS is large) and dIDS/dt shows a slight increase.However, the DC-link voltage VDC is often constant in voltage source converter applications, which means the influence of VDC on dIDS/dt is less important.The dIDS/dt temperature coefficient is usually calibrated to accommodate different DC-link voltages in a new operating environment.In addition, the slight fluctuation of the DC-link voltage has little effect on the dIDS/dt in the actual operating conditions, which also facilitates the use of the dIDS/dt as a TESP parameter for junction temperature extraction.

The Effect of Drive Resistance on dI DS /dt
As known in silicon MOSFETs and IGBTs, the external drive resistance (R G-ext ) also affects the turn-on dI DS /dt of SiC MOSFET.In order to observe the effect of the R G-ext on dI DS /dt, the heating plates were adjusted to 50 • C, 75 • C, 100 • C, 125 • C, and 150 • C, respectively.Each adjustment waits for one hour for the junction temperature of the chip to reach the set temperature.The rated current remains at 150 A and the waveforms of I DS observed from different R G-ext are shown in Figure 11.As observed from Figures 11 and 12, the dI DS /dt reduces as the resistance increases and the switching speed becomes slower.Since the increase of R G-ext reduces the gate current I G , the gate voltage V GS charges slowly to the gate capacitance C GS and V GS reaches the threshold voltage for a longer time (introduced from Equation ( 1)).In addition, the time that V GS reaches the Miller platform voltage also becomes longer (in Phase 2), which means dI DS /dt will decrease when R G-ext increases (introduced in Equation ( 7)).However, a small R G-ext increases dI DS /dt, but the gate parasitic inductance cannot be suppressed in a way that reduces the temperature sensitivity of dI DS /dt by decreasing the gate voltage that reaches the chip [24].It can be also seen from Figures 11 and 12 that temperature sensitivity of dI DS /dt shows better linearity under a large R G-ext and there is less oscillation in the waveform of I DS at a large drive resistance, which creates an easy way to obtain dI DS /dt.In addition, R G-in is the equivalent of the distribution resistance of the gate polysilicon and metal connection in MOSFET.Reference [25] confirmed that R G-in shows a positive temperature coefficient.If R G-ext is large, the temperature effect of R G-in is suppressed and it can be defaulted as R G (R G = R G-ext + R G-in ).This does not change with increasing temperature, which means dI DS /dt has better temperature sensitivity under larger R G-ext .Equation ( 9) also suggests that the increase of R G decreases the coefficient in front of dβ/dT, which increases the temperature sensitivity of dI DS /dt.slowly to the gate capacitance CGS and VGS reaches the threshold voltage for a longer time (introduced from Equation ( 1)).In addition, the time that VGS reaches the Miller platform voltage also becomes longer (in Phase 2), which means dIDS/dt will decrease when RG-ext increases (introduced in Equation ( 7)).However, a small RG-ext increases dIDS/dt, but the gate parasitic inductance cannot be suppressed in a way that reduces the temperature sensitivity of dIDS/dt by decreasing the gate voltage that reaches the chip [24].It can be also seen from Figures 11 and 12 that temperature sensitivity of dIDS/dt shows better linearity under a large RG-ext and there is less oscillation in the waveform of IDS at a large drive resistance, which creates an easy way to obtain dIDS/dt.In addition, RG-in is the equivalent of the distribution resistance of the gate polysilicon and metal connection in MOSFET.Reference [25] confirmed that RG-in shows a positive temperature coefficient.If RG-ext is large, the temperature effect of RG-in is suppressed and it can be defaulted as RG (RG = RG-ext + RG-in).This does not change with increasing temperature, which means dIDS/dt has better temperature sensitivity under larger RG-ext.Equation ( 9) also suggests that the increase of RG decreases the coefficient in front of dβ/dT, which increases the temperature sensitivity of dIDS/dt.In summary, the experimental and theoretical analysis are consistent and dIDS/dt shows better temperature sensitivity under the larger RG.Based on the experiment of this module, it is found that RG-ext shows a better temperature sensitivity when it is around 60 Ω (relative to RG-in, which is already very large).Since RG-ext is so large, dIDS/dt is too small, which makes the measurement difficult.

Driving Voltage VGG Effect on dIDS/dt
Combined with the theoretical analysis of the second part, it can be seen from Equation ( 7) that the reduction of the driving voltage VGG will reduce the dIDS/dt.However, from Equation ( 9), it can be deduced that the decrease of VGG reduces the coefficient of dβ/dT, which increases the positive temperature coefficient of dIDS/dt.In order to verify the influence of VGG on the temperature coefficient of dIDS/dt, the DC-link voltage VDC is kept at 350 V, the driving resistance is RG-ext = 60 Ω, and IDS at a steady state is 100 A. The double-pulse experiment was performed at different driving voltages of 12 slowly to the gate capacitance CGS and VGS reaches the threshold voltage for a longer time (introduced from Equation ( 1)).In addition, the time that VGS reaches the Miller platform voltage also becomes longer (in Phase 2), which means dIDS/dt will decrease when RG-ext increases (introduced in Equation ( 7)).However, a small RG-ext increases dIDS/dt, but the gate parasitic inductance cannot be suppressed in a way that reduces the temperature sensitivity of dIDS/dt by decreasing the gate voltage that reaches the chip [24].It can be also seen from Figures 11 and 12 that temperature sensitivity of dIDS/dt shows better linearity under a large RG-ext and there is less oscillation in the waveform of IDS at a large drive resistance, which creates an easy way to obtain dIDS/dt.In addition, RG-in is the equivalent of the distribution resistance of the gate polysilicon and metal connection in MOSFET.Reference [25] confirmed that RG-in shows a positive temperature coefficient.If RG-ext is large, the temperature effect of RG-in is suppressed and it can be defaulted as RG (RG = RG-ext + RG-in).This does not change with increasing temperature, which means dIDS/dt has better temperature sensitivity under larger RG-ext.Equation ( 9) also suggests that the increase of RG decreases the coefficient in front of dβ/dT, which increases the temperature sensitivity of dIDS/dt.In summary, the experimental and theoretical analysis are consistent and dIDS/dt shows better temperature sensitivity under the larger RG.Based on the experiment of this module, it is found that RG-ext shows a better temperature sensitivity when it is around 60 Ω (relative to RG-in, which is already very large).Since RG-ext is so large, dIDS/dt is too small, which makes the measurement difficult.

Driving Voltage VGG Effect on dIDS/dt
Combined with the theoretical analysis of the second part, it can be seen from Equation ( 7) that the reduction of the driving voltage VGG will reduce the dIDS/dt.However, from Equation ( 9), it can be deduced that the decrease of VGG reduces the coefficient of dβ/dT, which increases the positive temperature coefficient of dIDS/dt.In order to verify the influence of VGG on the temperature coefficient of dIDS/dt, the DC-link voltage VDC is kept at 350 V, the driving resistance is RG-ext = 60 Ω, and IDS at a steady state is 100 A. The double-pulse experiment was performed at different driving voltages of 12 In summary, the experimental and theoretical analysis are consistent and dI DS /dt shows better temperature sensitivity under the larger R G .Based on the experiment of this module, it is found that R G-ext shows a better temperature sensitivity when it is around 60 Ω (relative to R G-in , which is already very large).Since R G-ext is so large, dI DS /dt is too small, which makes the measurement difficult.

Driving Voltage V GG Effect on dI DS /dt
Combined with the theoretical analysis of the second part, it can be seen from Equation ( 7) that the reduction of the driving voltage V GG will reduce the dI DS /dt.However, from Equation ( 9), it can be deduced that the decrease of V GG reduces the coefficient of dβ/dT, which increases the positive temperature coefficient of dI DS /dt.In order to verify the influence of V GG on the temperature coefficient of dI DS /dt, the DC-link voltage V DC is kept at 350 V, the driving resistance is R G-ext = 60 Ω, and I DS at a steady state is 100 A. The double-pulse experiment was performed at different driving voltages of 12 V, 15 V, 18 V, and 20 V and different temperature points of 50 • C, 75 • C, 100 • C, 125 • C, and 150 • C, respectively.Figure 13 shows the waveforms of I DS with different drive voltages of 12 V and 20 V, respectively.Figure 14 shows the dI DS /dt values for different temperatures under the four driving voltages.It can be seen from Figure 13 that, as the driving voltage decreases, dI DS /dt becomes smaller.However, there is a greater range of variation with the junction temperature when the driving voltage V GG = 12 V.Using the dI DS /dt measured at 50 • C when V GG is 12 V as a reference, the value of dI DS /dt at 150 • C increases by 1.2 times.Similarly, using the dI DS /dt measured at 50 • C when V GG = 20 V as a reference, the value of dI DS /dt at 150 • C increases by 1.12 times.At the same time, the reduction of V GG reduces the switching speed and the oscillation of I DS that facilitates the measurement of the dI DS /dt.Therefore, dI DS /dt shows better temperature sensitivity at low drive voltages.However, it can be seen from Figure 14 that the dI DS /dt is too low when the driving voltage is reduced, which makes it difficult to measure.In addition, if V GG is too low, the module will not be completely turned on and it will work in the active area.Therefore, it is best to select a driving voltage of 12 V based on this module.respectively.Figure 13 shows the waveforms of IDS with different drive voltages of 12 V and 20 V, respectively.Figure 14 shows the dIDS/dt values for different temperatures under the four driving voltages.It can be seen from Figure 13 that, as the driving voltage decreases, dIDS/dt becomes smaller.However, there is a greater range of variation with the junction temperature when the driving voltage VGG = 12 V.Using the dIDS/dt measured at 50 °C when VGG is 12 V as a reference, the value of dIDS/dt at 150 °C increases by 1.2 times.Similarly, using the dIDS/dt measured at 50 °C when VGG = 20 V as a reference, the value of dIDS/dt at 150 °C increases by 1.12 times.At the same time, the reduction of VGG reduces the switching speed and the oscillation of IDS that facilitates the measurement of the dIDS/dt.Therefore, dIDS/dt shows better temperature sensitivity at low drive voltages.However, it can be seen from Figure 14 that the dIDS/dt is too low when the driving voltage is reduced, which makes it difficult to measure.In addition, if VGG is too low, the module will not be completely turned on and it will work in the active area.Therefore, it is best to select a driving voltage of 12 V based on this module.

Design Measuring Junction Temperature Circuit and Experimental Verification
The dIDS/dt as a real-time junction temperature extraction for SiC MOSFETs can be achieved using the following method.For the SiC MOSFET module with a source auxiliary terminal S, it is possible to measure the peak value of the induced voltage VS'S generated by the parasitic inductance LS between the source assist S' and the source S during the SiC MOSFET turn-on transient.The value respectively.Figure 13 shows the waveforms of IDS with different drive voltages of 12 V and 20 V, respectively.Figure 14 shows the dIDS/dt values for different temperatures under the four driving voltages.It can be seen from Figure 13 that, as the driving voltage decreases, dIDS/dt becomes smaller.However, there is a greater range of variation with the junction temperature when the driving voltage VGG = 12 V.Using the dIDS/dt measured at 50 °C when VGG is 12 V as a reference, the value of dIDS/dt at 150 °C increases by 1.2 times.Similarly, using the dIDS/dt measured at 50 °C when VGG = 20 V as a reference, the value of dIDS/dt at 150 °C increases by 1.12 times.At the same time, the reduction of VGG reduces the switching speed and the oscillation of IDS that facilitates the measurement of the dIDS/dt.Therefore, dIDS/dt shows better temperature sensitivity at low drive voltages.However, it can be seen from Figure 14 that the dIDS/dt is too low when the driving voltage is reduced, which makes it difficult to measure.In addition, if VGG is too low, the module will not be completely turned on and it will work in the active area.Therefore, it is best to select a driving voltage of 12 V based on this module.

Design Measuring Junction Temperature Circuit and Experimental Verification
The dIDS/dt as a real-time junction temperature extraction for SiC MOSFETs can be achieved using the following method.For the SiC MOSFET module with a source auxiliary terminal S, it is possible to measure the peak value of the induced voltage VS'S generated by the parasitic inductance LS between the source assist S' and the source S during the SiC MOSFET turn-on transient.The value

Design Measuring Junction Temperature Circuit and Experimental Verification
The dI DS /dt as a real-time junction temperature extraction for SiC MOSFETs can be achieved using the following method.For the SiC MOSFET module with a source auxiliary terminal S, it is possible to measure the peak value of the induced voltage V S'S generated by the parasitic inductance L S between the source assist S' and the source S during the SiC MOSFET turn-on transient.The value of L S can be found in the device manual.According to the formula V S'S = L(dI DS /dt), the value of dI DS /dt can be obtained.Figure 15 shows the peak value measurement circuit of V S'S , but the above circuit is only suitable for SiC MOSFET modules with an auxiliary source.In order to target all modules, a measurement circuit based on the printed circuit board (PCB) Rogowski coil [26] was proposed.The measurement circuit is shown in Figure 16a.It consists of two high-precision operational amplifiers (LM7171), a diode, a storage capacitor of 4.7 nF, and a discharge resistor R 1 .The first LM7171 is mainly used to acquire the parameters of the dI DS /dt sensed by the PCB Rogowski coil and is used to isolate the high voltage.The second LM7171 mainly amplifies the resolution according to the actual needs.It facilitates the acquisition of the one-to-one correspondence between dI DS /dt and the junction temperature.From Figure 17b, it can be seen that the circuit occupies a small space and the cost is low so that it can be embedded in the drive module.The PCB Rogowski coil can be directly mounted on the terminal of the SiC MOSFET module, which offers a new idea for engineering applications.
In order to verify the feasibility of the circuit, the driving voltage is 12 V under the voltage and current level of 350 V and 100 A and the double pulse experiments are carried out at the working junction temperature of SiC MOSFET at 50 • C, 75 • C, 100 • C, 125 • C, and 150 • C, respectively.The magnification of the measurement circuit is 1 (This value can be changed by adjusting the ratio of R 2 to R 3 ) and the output waveform is shown in Figure 17.It can be seen that each temperature corresponding to the measured voltage shows better linearity.The measured voltage is 0.4 V at 50 • C, and 0.8 V at 150 • C. In addition, the resolution is 4 mV/ • C. The resolution can be increased by increasing the amplification of the operational amplifier.The Junction temperature of SiC MOSFET can be obtained by using Equation ( 13) where T 1 is the calculation temperature, K 1 is the resolution (250 • C/mV), and V 1 is the measuring voltage by this measuring circuit.
To further test the feasibility of extracting the junction temperature of this circuit, the heating plate is adjusted to different temperatures.The measured voltage is obtained by the measuring circuit of Figure 16 and the measured temperature can be calculated by using Equation (13).The result is shown in Table 1.It can be observed that, compared with the actual junction temperature, the maximum deviation of the calculated temperature does not exceed 5 • C. Therefore, this circuit for extracting the junction temperature of SiC MOSFET is feasible.In an actual operation, the junction temperature and the measurement voltage corresponding to the calculated temperature are converted into the digital signals by the A/D module (Analog to Digital Converter) and are stored in the Field-Programmable Gate Array (FPGA) of the driving module.The junction temperature is obtained by looking up the table.
As mentioned above, dI DS /dt has better temperature sensitivity under a small drive voltage and a large drive resistance, but it also brings about an increase in the switching loss.Since the real work does not need to extract the junction temperature at every moment, an intelligent driver [27] can be used to set a small time period to make the driver open SiC MOSFET under the large resistance and small drive voltage for the junction temperature extraction.After the data is acquired, the original small drive resistance and large gate voltage are restored.Therefore, the accurate junction temperature can be extracted while satisfying fast switching frequency and small switching loss.In summary, it is feasible to extract the junction temperature from SiC MOSFET based on dI DS /dt.
does not need to extract the junction temperature at every moment, an intelligent driver [27] can be used to set a small time period to make the driver open SiC MOSFET under the large resistance and small drive voltage for the junction temperature extraction.After the data is acquired, the original small drive resistance and large gate voltage are restored.Therefore, the accurate junction temperature can be extracted while satisfying fast switching frequency and small switching loss.In summary, it is feasible to extract the junction temperature from SiC MOSFET based on dIDS/dt.

Conclusions
In this paper, the temperature dependence of the turn-on dIDS/dt of SiC MOSFET is discussed using device mathematical models and experiments.It is shown that dIDS/dt increases with a rising temperature as a result of the negative temperature sensitivity of the threshold voltage VTH.Afterward, other factors affecting dIDS/dt are analyzed.It was found that rising DC-link voltage VDC values and external gate resistance RG-ext as well as the decrease of the driving voltage VGG can increase the temperature sensitivity of dIDS/dt.However, the load current has no effect on dIDS/dt.Therefore, there is a good temperature sensitivity of dIDS/dt under large drive resistance and small drive voltage.Lastly, a small and low-cost PCB-based Rogowski coil measurement circuit was designed.The dIDS/dt obtained by this circuit exhibits a near linear dependency on temperature with a resolution of 4 mV/°C (the resolution can be increased by adjusting the amplification factor).When the actual application needs junction temperature extraction, the intelligent driver sends a detection signal to

Conclusions
In this paper, the temperature dependence of the turn-on dIDS/dt of SiC MOSFET is discussed using device mathematical models and experiments.It is shown that dIDS/dt increases with a rising temperature as a result of the negative temperature sensitivity of the threshold voltage VTH.Afterward, other factors affecting dIDS/dt are analyzed.It was found that rising DC-link voltage VDC values and external gate resistance RG-ext as well as the decrease of the driving voltage VGG can increase the temperature sensitivity of dIDS/dt.However, the load current has no effect on dIDS/dt.Therefore, there is a good temperature sensitivity of dIDS/dt under large drive resistance and small drive voltage.Lastly, a small and low-cost PCB-based Rogowski coil measurement circuit was designed.The dIDS/dt obtained by this circuit exhibits a near linear dependency on temperature with a resolution of 4 mV/°C (the resolution can be increased by adjusting the amplification factor).When the actual application needs junction temperature extraction, the intelligent driver sends a detection signal to

Conclusions
In this paper, the temperature dependence of the turn-on dI DS /dt of SiC MOSFET is discussed using device mathematical models and experiments.It is shown that dI DS /dt increases with a rising temperature as a result of the negative temperature sensitivity of the threshold voltage V TH .Afterward, other factors affecting dI DS /dt are analyzed.It was found that rising DC-link voltage V DC values

Figure 1 .
Figure1ashows the cell structure of the planar SiC MOSFET.It can be seen that the cell of the SiC MOSFET is mainly composed of the gate, source, drain, oxide layer, N-drift region, N-base region, and Junction Field-Effect Transistor (JEFT) region.The figure also shows the route of the electron carrier flow, the position of inversion layer channel, and the distribution of parasitic capacitance.

Figure 4 .
Figure 4. Waveforms of the drain-source current at different temperatures.

Figure 5 .
Figure 5. Parasitic inductance LS induced the voltage waveform at turn-on.

Figure 5 .
Figure 5. Parasitic inductance L S induced the voltage waveform at turn-on.
dI DS /dt in the actual operating conditions, which also facilitates the use of the dI DS /dt as a TESP parameter for junction temperature extraction.

Figure 7 .
Figure 7.The measured I DS turn-on current transients for different load currents (R G-ext = 60 Ω, T j = 150 • C).

Figure 9 .Figure 10 .
Figure 9.The turn-on IDS and VDS waveforms at different DC-link voltages.

Figure 9 .
Figure 9.The turn-on I DS and V DS waveforms at different DC-link voltages.

Figure 9 .Figure 10 .
Figure 9.The turn-on IDS and VDS waveforms at different DC-link voltages.

Figure 10 .
Figure 10.Parasitic inductance induced voltage waveforms at different DC-link voltages.

Figure 12 .
Figure 12.The dI DS /dt under different resistances and temperatures.

Figure 13 .
Figure 13.Different temperature drain current waveforms for two drive voltages.

Figure 14 .
Figure 14.dIDS/dt values for different temperatures under four driving voltages.

Figure 13 .
Figure 13.Different temperature drain current waveforms for two drive voltages.

Figure 13 .
Figure 13.Different temperature drain current waveforms for two drive voltages.

Figure 14 .
Figure 14.dIDS/dt values for different temperatures under four driving voltages.

Figure 14 .
Figure 14.dI DS /dt values for different temperatures under four driving voltages.

Figure 15 .
Figure 15.Parasitic inductance induced the voltage VS'S measurement circuit when it is turned on.Figure 15.Parasitic inductance induced the voltage V S'S measurement circuit when it is turned on.

Figure 15 .Figure 16 .Figure 17 .
Figure 15.Parasitic inductance induced the voltage VS'S measurement circuit when it is turned on.Figure 15.Parasitic inductance induced the voltage V S'S measurement circuit when it is turned on.Energies 2018, 11, x FOR PEER REVIEW 13 of 15

Table 1 . 2
The measured voltage by the measuring circuit at different temperatures and the temperature calculated by using Equation (13).Junction Temperature 60 °C 70 °C 110 °C 130 °C 140 °C Measured Voltage 0.43 V 0.5 V 0.655 V 0.73 V 0.755 V Calculation Temperature 57.5 °C 75 °C 114 °C 133 °C 139 °C Deviation −

Table 1 . 2
The measured voltage by the measuring circuit at different temperatures and the temperature calculated by using Equation (13).Junction Temperature 60 °C 70 °C 110 °C 130 °C 140 °C Measured Voltage 0.43 V 0.5 V 0.655 V 0.73 V 0.755 V Calculation Temperature 57.5 °C 75 °C 114 °C 133 °C 139 °C Deviation −

Figure 17 .
Figure 17.Measurement circuit output waveforms at different temperatures.

Table 1 .
The measured voltage by the measuring circuit at different temperatures and the temperature calculated by using Equation (13).