Smoothly Transitive Fixed Frequency Hysteresis Current Control Based on Optimal Voltage Space Vector

Jiang Zeng 1, Lin Yang 1, Yuchang Ling 1, Haoping Chen 2, Zhonglong Huang 1, Tao Yu 1 ID and Bo Yang 3,* 1 School of Electric Power, South China University of Technology, GuangZhou 510640, China; zengxy@scut.edu.cn (J.Z.); Ylin_SCUT@163.com (L.Y.); lingychy@foxmail.com (Y.L.); huangzlg@163.com (Z.H.); taoyu1@scut.edu.cn (T.Y.) 2 Dongguan Power Supply Bureau, Dongguan 523000, China; 15099963392@163.com 3 Faculty of Electric Power Engineering, Kunming University of Science and Technology, Kunming 650500, China * Correspondence: yangbo_ac@outlook.com


Introduction
In the past decade, distributed generation (DG), including wind, hydro, solar, biomass, geothermal, tidal, fuel cell, has been widely deployed which can provide a powerful solution for the growing energy crisis resulting from the use of conventional fossil fuels, e.g., coal, gas, oil [1][2][3][4][5][6][7][8].The integration of large-scale DG into the power grid will inevitably degrade power quality [9][10][11], in which harmonics due to adoption of converters of DG have a severe impact on the devices connected to the power system, which has gained enormous attention in recent year [12,13].At present, the active power filter (APF) is one of the most effective tools for harmonics reduction [14], which usually adopts hysteresis current control (HCC) to realize an efficient harmonics compensation thanks to its elegant merits of simple implementation, high accuracy and fast response [15].
Generally speaking, there are two types of HCC: fixed bandwidth HCC (BHCC) and fixed frequency HCC (FHCC).Here, the fluctuation of switching frequency of BHCC often causes an Energies 2018, 11, 1695 3 of 20 strategies will be switched only if current errors exceed the limit of the outer hysteresis bandwidth.Then, an improved approach of regulating the hysteresis bandwidth is presented to fix the switching frequency with switch phases being regulated, based on OVSV.Furthermore, a flexible division of the voltage-space-vectors diagram is designed to divide the original region into six sub-regions.By adopting the flexible division, the control strategies under mode 0 and mode 1 can be switched alternately.Lastly, comprehensive case studies are undertaken to evaluate and compare the control performance of S-FHCC and ST-FHCC.
The original contribution and novelty of this paper can be summarized into the following three aspects:

•
The paper considers an APF in a three-phase-three-wire power system, in which FHCC is developed instead of the one given by [32][33][34].Under such a configuration, the voltage between neutral point and dc-link midpoint of the APF results in a strong control coupling of three-phase, which has a dramatic impact on regulation of hysteresis bandwidth and fixed frequency.Hence phase-to-phase decoupling is implemented to eliminate the voltage, such that the two phase-to-phase current errors can be independently controlled by two switches with the third switch being a constant;

•
Compared to [33,34], an improved approach of variable hysteresis bandwidth is presented in this paper, of which the midpoint of switch signals in the state of 0 is synchronized to the clock pulse with a constant frequency.Meanwhile, the equation is given to calculate the hysteresis bandwidth in the next period according to that in the current period.With this approach, fixed frequency and regulation of switch phases can be obtained simultaneously, such that the switching frequency can be constant while the uncontrollable phase-to-phase current error can be reduced greatly.

•
A flexible division of the voltage-space-vector diagram is developed to divide the original voltage-space-vectors diagram into six sub-regions, upon which the control strategies under mode 0 and mode 1 can be switched alternately.As a result, a smooth transition can be realized while the inherent weakness of S-FHCC can be avoided, e.g., the control strategies will be switched only if current errors exceed the limit of the outer hysteresis bandwidth.The switching is far smoother with higher control accuracy and smaller current errors in ST-FHCC than those in S-FHCC.
The remainder of this paper is organized as follows: Section 2 aims to introduce the principle of S-FHCC.In Section 3, an approach of the variable hysteresis bandwidth is presented.ST-FHCC is described in detail in Section 4. Case studies are presented in Section 5 while some discussions about the results generated is given in Section 6.The work presented in the paper and some concluding remarks/findings are summarized in Section 7.

Active Power Filter (APF) Model
Figure 1 shows an equivalent circuit of a three-phase APF.Here, S a , S b and S c represent three switching functions and 1 or 0 are used to represent their states, respectively.Here, 1 means the upper leg is turn-on and the lower leg is turn-off, while 0 means the opposite state.E is the DC-link capacitor voltage.R and L are resistor and inductor connected to the inverter bridge with the power grid.u 0 is the voltage between neutral point and ground.u a , u b , u c are phase a, phase b and phase c terminal voltage with respect to the neutral point of inverter bridge O, while i a , i b i c are phase a, phase b and phase c line currents, respectively.The decoupling of phase-to-phase currents is required to obtain S-FHCC [30], such that the dynamics of current error can be written with a voltage-space-vector. Ignore the resistance, yields   i uu (1) where Δi is the difference between the line current space vector reference i * and line current space vector i; u is a voltage-space-vector; and u * is a voltage-space-vector reference corresponding to i * , respectively.Expand (1) into where u ab * , u bc * , u ca * are the line voltage references of phase ab, phase bc, phase ca, respectively.Δiab, Δibc, Δica are given by * ca are the phase-to-phase current references of phase ab, phase bc, phase ca, and iab, ibc, ica are the differences between ia and ib, ib and ic, ic and ia, respectively.
From Equation (2), one can see that the phase-to-phase current errors are only determined by the corresponding two-phase switches, thus a decoupled current control could be realized.For instance, set Sb = 0 or 1 and Δiab and Δibc can be controlled by Sa and Sc, respectively.A similar control strategy can be derived when Sa or Sc are set to be a constant.Therefore, as shown in Figure 2, the voltagespace-vectors diagram can be divided into three parallelogram regions, each of which is denoted to be either mode 0 (one of the three switches Sa, Sb or Sc is fixed to be 0 while the others are arbitrary) or mode 1 (one of the three switches Sa, Sb or Sc is fixed to be 1 while the others are arbitrary).The decoupling of phase-to-phase currents is required to obtain S-FHCC [30], such that the dynamics of current error can be written with a voltage-space-vector. Ignore the resistance, yields where ∆i is the difference between the line current space vector reference i * and line current space vector i; u is a voltage-space-vector; and u * is a voltage-space-vector reference corresponding to i * , respectively.Expand (1) into where u * ab , u * bc , u * ca are the line voltage references of phase ab, phase bc, phase ca, respectively.∆i ab , ∆i bc , ∆i ca are given by where i * ab , i * bc , i * ca are the phase-to-phase current references of phase ab, phase bc, phase ca, and i ab , i bc , i ca are the differences between i a and i b , i b and i c , i c and i a , respectively.
From Equation (2), one can see that the phase-to-phase current errors are only determined by the corresponding two-phase switches, thus a decoupled current control could be realized.For instance, set S b = 0 or 1 and ∆i ab and ∆i bc can be controlled by S a and S c , respectively.A similar control strategy can be derived when S a or S c are set to be a constant.Therefore, as shown in Figure 2, the voltage-space-vectors diagram can be divided into three parallelogram regions, each of which is denoted to be either mode 0 (one of the three switches S a , S b or S c is fixed to be 0 while the others are arbitrary) or mode 1 (one of the three switches S a , S b or S c is fixed to be 1 while the others are arbitrary).
The detailed control strategies under mode 0 and mode 1 in different parallelogram regions are given by Table 1.The detailed control strategies under mode 0 and mode 1 in different parallelogram regions are given by Table 1.

S-FHCC and Its Weakness
In literature [30,31], two hysteresis comparators employed in S-FHCC are depicted by Figure 3.The inner hysteresis comparator is adopted to detect whether the current error exceeds the inner bandwidth while the outer hysteresis comparator is used to detect whether the current error exceeds the outer bandwidth, which is larger than the inner bandwidth, such that the location of u * could be determined.In Figure 3, S i and S e are logic vectors calculated by reversing the outputs of the inner hysteresis comparator and the outer hysteresis comparator while 2h i and 2h e are their hysteresis bandwidth, respectively.In addition, S represents the switching vector, given by

S-FHCC and Its Weakness
In literature [30,31], two hysteresis comparators employed in S-FHCC are depicted by Figure 3.The inner hysteresis comparator is adopted to detect whether the current error exceeds the inner bandwidth while the outer hysteresis comparator is used to detect whether the current error exceeds the outer bandwidth, which is larger than the inner bandwidth, such that the location of u * could be determined.The detailed control strategies under mode 0 and mode 1 in different parallelogram regions are given by Table 1.

S-FHCC and Its Weakness
In literature [30,31], two hysteresis comparators employed in S-FHCC are depicted by Figure 3.The inner hysteresis comparator is adopted to detect whether the current error exceeds the inner bandwidth while the outer hysteresis comparator is used to detect whether the current error exceeds the outer bandwidth, which is larger than the inner bandwidth, such that the location of u * could be determined.In Figure 3, S i and S e are logic vectors calculated by reversing the outputs of the inner hysteresis comparator and the outer hysteresis comparator while 2h i and 2h e are their hysteresis bandwidth, respectively.In addition, S represents the switching vector, given by In Figure 3, S i and S e are logic vectors calculated by reversing the outputs of the inner hysteresis comparator and the outer hysteresis comparator while 2h i and 2h e are their hysteresis bandwidth, respectively.In addition, S represents the switching vector, given by Note that the location of u * can be determined by the signs of the three line-to-line voltage references, i.e., u * ab , u * bc , u * ca , which is indicated by S e .Besides, the phase lock aims at fixing the switching frequency of APF with a proportional-integral (PI) controller.More details of the S-FHCC can be found in references [30,31] for interested readers.Nevertheless, an inherent weakness of S-FHCC is that the change of the location of u * can be detected only if one of the three current errors exceeds the limit of the corresponding outer hysteresis bandwidth, such that the control strategy are changed.For instance, when u * moves from region VI to region I shown by Figure 4a, the control strategy in region VI (S c controls ∆i bc while S a controls ∆i ab ) is still adopted with the fact that ∆i bc will increase continuously despite the value of S c until the current error ∆i bc exceeds the limit of the outer hysteresis comparator, as clearly provided in Figure 4b.
Note that the location of u * can be determined by the signs of the three line-to-line voltage references, i.e., u ab * , u bc * , u ca * , which is indicated by S e .Besides, the phase lock aims at fixing the switching frequency of APF with a proportional-integral (PI) controller.More details of the S-FHCC can be found in references [30,31] for interested readers.
Nevertheless, an inherent weakness of S-FHCC is that the change of the location of u * can be detected only if one of the three current errors exceeds the limit of the corresponding outer hysteresis bandwidth, such that the control strategy are changed.For instance, when u * moves from region VI to region I shown by Figure 4a, the control strategy in region VI (Sc controls Δibc while Sa controls Δiab) is still adopted with the fact that Δibc will increase continuously despite the value of Sc until the current error Δibc exceeds the limit of the outer hysteresis comparator, as clearly provided in Figure 4b.

Fixed Swithcing Frequency Based on Optimal Voltage Space Vector (OVSV)
Since the uncontrollable current error is the negative sum of the other two phase-to-phase current errors under control, e.g., Δiab = −(Δibc + Δica), Δibc and Δica should be as close as possible in amplitude and opposite to each other in phase in order to decrease the amplitude of Δiab.Thus, the hysteresis bandwidth is required to fix switching frequency and to regulate the phase of two controllable switches.Moreover, an approach of fixing switching frequency with switch phases being regulated is presented such that the midpoint of switching signals in the state of 0 is synchronized to the clock pulse with a constant frequency, which is demonstrated as follows.
Assume u * is in region P02, shown in Figure 2. It can be seen that Sc and Sa can independently control Δibc and Δiab, respectively.u * changes slightly during a switching period under high switching frequency, which could be ignored.Hence, the current error increases or decreases linearly with respect to time.The process of fixing the switching frequencies of Sa and Sc with switch phases being regulated are depicted in Figure 5, by which the current error will cross the zero-point of the clock pulse in each switching period.As a result, the switching frequencies of Sa and Sc remain constant, which is equal to that of the clock pulse.More importantly, the phases of Sa and Sc are regulated to be almost opposite.

Fixed Swithcing Frequency Based on Optimal Voltage Space Vector (OVSV)
Since the uncontrollable current error is the negative sum of the other two phase-to-phase current errors under control, e.g., ∆i ab = −(∆i bc + ∆i ca ), ∆i bc and ∆i ca should be as close as possible in amplitude and opposite to each other in phase in order to decrease the amplitude of ∆i ab .Thus, the hysteresis bandwidth is required to fix switching frequency and to regulate the phase of two controllable switches.Moreover, an approach of fixing switching frequency with switch phases being regulated is presented such that the midpoint of switching signals in the state of 0 is synchronized to the clock pulse with a constant frequency, which is demonstrated as follows.
Assume u * is in region P 02 , shown in Figure 2. It can be seen that S c and S a can independently control ∆i bc and ∆i ab , respectively.u * changes slightly during a switching period under high switching frequency, which could be ignored.Hence, the current error increases or decreases linearly with respect to time.The process of fixing the switching frequencies of S a and S c with switch phases being regulated are depicted in Figure 5, by which the current error will cross the zero-point of the clock pulse in each switching period.As a result, the switching frequencies of S a and S c remain constant, which is equal to that of the clock pulse.More importantly, the phases of S a and S c are regulated to be almost opposite.
According to Figure 5, in order to synchronize the clock pulse and the midpoint of the switch signals in the state of 0, the hysteresis bandwidths must satisfy: where h k and h k+1 are the hysteresis bandwidth in the current switching period and in the next switching period; T 1 and T 2 denote the durations of the switch signal that stayed at 1 and 0 in the current switching period; T s is a given switching period; and ∆t is the difference between the midpoint of switch signal and clock pulse, respectively.
In S-FHCC, the adopted voltage-space-vectors are not optimal when the three-phase switches operate without regulating the phase of switches.In contrast, regulating the phase of switches cannot only decrease current error and harmonics, but can also lead to an OVSV.
For example, when u * is in region I under mode 0, the waveforms of S a , S b , S c and the sequence of voltage-space-vectors are (V 0 , V 1 , V 2 , V 3 , V 0 ) without regulating the phase of switches, as shown in Figure 6a.Moreover, this also demonstrates that the currents are controllable in the whole parallelogram region denoted by P 03 .However, there are three OVSVs, i.e., V 0 , V 1 , V 2 , and one suboptimal voltage-space-vector, i.e., V 3 , in the adopted control set of voltage-space-vectors {V 0 , V 1 , V 2 , V 3 } [30,31], which cannot all be optimal.According to Figure 5, in order to synchronize the clock pulse and the midpoint of the switch signals in the state of 0, the hysteresis bandwidths must satisfy: where hk and hk+1 are the hysteresis bandwidth in the current switching period and in the next switching period; T1 and T2 denote the durations of the switch signal that stayed at 1 and 0 in the current switching period; Ts is a given switching period; and Δt is the difference between the midpoint of switch signal and clock pulse, respectively.In S-FHCC, the adopted voltage-space-vectors are not optimal when the three-phase switches operate without regulating the phase of switches.In contrast, regulating the phase of switches cannot only decrease current error and harmonics, but can also lead to an OVSV.
For example, when u * is in region I under mode 0, the waveforms of Sa, Sb, Sc and the sequence of voltage-space-vectors are (V0, V1, V2, V3, V0) without regulating the phase of switches, as shown in Figure 6a.Moreover, this also demonstrates that the currents are controllable in the whole parallelogram region denoted by P03.However, there are three OVSVs, i.e., V0, V1, V2, and one suboptimal voltage-space-vector, i.e., V3, in the adopted control set of voltage-space-vectors {V0, V1, V2, V3} [30,31], which cannot all be optimal.
With switch phases regulated, the waveforms of Sa, Sb, Sc and the operation sequence of voltagespace-vectors are (V0, V1, V2, V1, V0), as shown in Figure 6b.Since region I belongs to the parallelogram region, the current error is also controllable in the region I. Furthermore, the adopted control set of voltage-space-vectors {V0, V1, V2} is all optimal.According to Figure 5, in order to synchronize the clock pulse and the midpoint of the switch signals in the state of 0, the hysteresis bandwidths must satisfy: where hk and hk+1 are the hysteresis bandwidth in the current switching period and in the next switching period; T1 and T2 denote the durations of the switch signal that stayed at 1 and 0 in the current switching period; Ts is a given switching period; and Δt is the difference between the midpoint of switch signal and clock pulse, respectively.In S-FHCC, the adopted voltage-space-vectors are not optimal when the three-phase switches operate without regulating the phase of switches.In contrast, regulating the phase of switches cannot only decrease current error and harmonics, but can also lead to an OVSV.
For example, when u * is in region I under mode 0, the waveforms of Sa, Sb, Sc and the sequence of voltage-space-vectors are (V0, V1, V2, V3, V0) without regulating the phase of switches, as shown in Figure 6a.Moreover, this also demonstrates that the currents are controllable in the whole parallelogram region denoted by P03.However, there are three OVSVs, i.e., V0, V1, V2, and one suboptimal voltage-space-vector, i.e., V3, in the adopted control set of voltage-space-vectors {V0, V1, V2, V3} [30,31], which cannot all be optimal.
With switch phases regulated, the waveforms of Sa, Sb, Sc and the operation sequence of voltagespace-vectors are (V0, V1, V2, V1, V0), as shown in Figure 6b.Since region I belongs to the parallelogram region, the current error is also controllable in the region I. Furthermore, the adopted control set of voltage-space-vectors {V0, V1, V2} is all optimal.With switch phases regulated, the waveforms of S a , S b , S c and the operation sequence of voltage-space-vectors are (V 0 , V 1 , V 2 , V 1 , V 0 ), as shown in Figure 6b.Since region I belongs to the parallelogram region, the current error is also controllable in the region I. Furthermore, the adopted control set of voltage-space-vectors {V 0 , V 1 , V 2 } is all optimal.

Flexible Division of Voltage-Space-Vector Diagram
To prevent the current error from exceeding its limit illustrated by Figure 4b, one should switch between mode 0 and mode 1.As shown in Figure 7a, the inherent weakness can be thoroughly overcome if the control strategy under mode 0 (S b = 0, S c → ∆i bc , S a → ∆i ab ) is switched into the control strategy under mode 1 (S a = 1, S b → ∆i ab , S c → ∆i ca ) before u * crosses the boundary VI-I.Similarly, mode 1 should be switched into mode 0 before u * crosses the boundary I-II.The reason is that in the overlapping area, two of the three current errors are always controllable, and the switching between mode 0 and mode 1 will not lead to what Figure 4b describes.Therefore, in order to smoothly transit the boundaries of the three parallelogram regions under mode 0 or mode 1, the control strategies under mode 0 and mode 1 should be switched in the overlapping areas of the two parallelogram regions under mode 0 and mode 1, respectively.

Flexible Division of Voltage-Space-Vector Diagram
To prevent the current error from exceeding its limit illustrated by Figure 4b, one should switch between mode 0 and mode 1.As shown in Figure 7a, the inherent weakness can be thoroughly overcome if the control strategy under mode 0 (Sb = 0, Sc → Δibc, Sa → Δiab) is switched into the control strategy under mode 1 (Sa = 1, Sb → Δiab, Sc → Δica) before u * crosses the boundary VI-I.Similarly, mode 1 should be switched into mode 0 before u * crosses the boundary I-II.The reason is that in the overlapping area, two of the three current errors are always controllable, and the switching between mode 0 and mode 1 will not lead to what Figure 4b describes.Therefore, in order to smoothly transit the boundaries of the three parallelogram regions under mode 0 or mode 1, the control strategies under mode 0 and mode 1 should be switched in the overlapping areas of the two parallelogram regions under mode 0 and mode 1, respectively.
More specifically, before u * crosses the boundary VI-I, mode 0 is switched into mode 1.Moreover, when u * crosses the boundary VI-I, the operation sequence of voltage-space-vectors varies from S16 to S11, where S16 and S11 represent the operation sequences of (V7, V6, V1, V6, V7) and (V7, V2, V1, V2, V7), respectively.With u * crossing the boundary VI-I, the duration of Sb staying at 0 decreases gradually which is contrary to that of Sc staying at 0, such that a smooth transition of three-phase switches can be realized, as shown from Figure 7b.Remark 1. u * can be composed according to volt-second balance when u * is located in region VI, as where T 0 ' is the duration of V7; T 6 ' denotes the duration of V6 while T 1 ' denotes the duration of V1; and Ts is the switching period.
With u * crossing the boundary VI-I, T 6 ' will decrease while T 1 ' will increase, which show that the duty-cycle of Sb narrows gradually which is contrary to that of Sc in Figure 7b.Moreover, when u * is just located in the boundary VI-I, T1 is equals to 0, which shows that the duty-cycle of Sb is equal to that of Sc.After u * crosses the boundary, u * will be composed of where T 2 ' is the duration of V2.
With u * changing continuously, T 2 ' will increase while T 1 ' will decrease, which illustrates that the duty-cycle of Sb decrease further which is contrary to that of Sc in Figure 7b.More specifically, before u * crosses the boundary VI-I, mode 0 is switched into mode 1.Moreover, when u * crosses the boundary VI-I, the operation sequence of voltage-space-vectors varies from S 16 to S 11 , where S 16 and S 11 represent the operation sequences of (V 7 , V 6 , V 1 , V 6 , V 7 ) and (V 7 , V 2 , V 1 , V 2 , V 7 ), respectively.With u * crossing the boundary VI-I, the duration of S b staying at 0 decreases gradually which is contrary to that of S c staying at 0, such that a smooth transition of three-phase switches can be realized, as shown from Figure 7b.
Remark 1. u * can be composed according to volt-second balance when u * is located in region VI, as where T 0 is the duration of V 7 ; T 6 denotes the duration of V 6 while T 1 denotes the duration of V 1 ; and T s is the switching period.
With u * crossing the boundary VI-I, T 6 will decrease while T 1 will increase, which show that the duty-cycle of S b narrows gradually which is contrary to that of S c in Figure 7b.Moreover, when u * is just located in the boundary VI-I, T 1 is equals to 0, which shows that the duty-cycle of S b is equal to that of S c .After u * crosses the boundary, u * will be composed of Energies 2018, 11, 1695 9 of 20 where T 2 is the duration of V 2 .
With u * changing continuously, T 2 will increase while T 1 will decrease, which illustrates that the duty-cycle of S b decrease further which is contrary to that of S c in Figure 7b.
The three parallelogram regions under mode 0 and those under mode 1 can produce six overlapping areas, i.e., I-VI, as depicted in Figure 2. The control strategies under mode 0 (mode 1) should be switched into those under mode 1 (mode 0) in these overlapping areas, for two controllable current errors are always under control by two switches in these overlapping areas.Hence, a switching boundary needs to be set in each overlapping area in order to switch between the control strategies under mode 0 and those under mode 1 in the overlapping areas.On the one hand, the voltage-space-vectors diagram can be divided into six symmetric sub-regions, e.g., A to F, in Figure 8a.Two different control modes are adopted to two adjacent sub-regions.The regions A, C and E are controlled by mode 1 while regions B, D and E are controlled by mode 0. Under such a scenario, the current error will not exceed its limit in the division boundaries.Besides, symmetrical division can offer a fast and accurate regulation of hysteresis bandwidth and phase.The detailed control strategies are tabulated in Table 2.
Energies 2018, 11, x FOR PEER REVIEW 9 of 20 The three parallelogram regions under mode 0 and those under mode 1 can produce six overlapping areas, i.e., I-VI, as depicted in Figure 2. The control strategies under mode 0 (mode 1) should be switched into those under mode 1 (mode 0) in these overlapping areas, for two controllable current errors are always under control by two switches in these overlapping areas.Hence, a switching boundary needs to be set in each overlapping area in order to switch between the control strategies under mode 0 and those under mode 1 in the overlapping areas.On the one hand, the voltage-space-vectors diagram can be divided into six symmetric sub-regions, e.g., A to F, in Figure 8a.Two different control modes are adopted to two adjacent sub-regions.The regions A, C and E are controlled by mode 1 while regions B, D and E are controlled by mode 0. Under such a scenario, the current error will not exceed its limit in the division boundaries.Besides, symmetrical division can offer a fast and accurate regulation of hysteresis bandwidth and phase.The detailed control strategies are tabulated in Table 2.   On the other hand, the voltage-space-vectors diagram can also be divided more flexibly and even asymmetrically in ST-FHCC, as illustrated by Figure 8b.Note that such a division provides more margins for switching control strategies, which is due to the fact that even if there is a slight estimation error of u * , the current errors are still under control.

Switching of the Control Strategies in S-FHCC
As illustrated in Figure 9a, the operation sequence of voltage-space-vectors varies from S06 to S01 with u * crossing from region VI to I, where S06 and S01 denote the operation sequences of (V0, V1, V6, V1, V0) and (V0, V1, V2, V1, V0), respectively.In S06 or S01, u will be V0, V1, V6, V1, V0 or V0, V1, V2, V1, V0 in sequence in a switching period.Consider that u * is approximated to be a constant in a switching

Sub-Regions Control Strategy
On the other hand, the voltage-space-vectors diagram can also be divided more flexibly and even asymmetrically in ST-FHCC, as illustrated by Figure 8b.Note that such a division provides more margins for switching control strategies, which is due to the fact that even if there is a slight estimation error of u * , the current errors are still under control.

Switching of the Control Strategies in S-FHCC
As illustrated in Figure 9a, the operation sequence of voltage-space-vectors varies from S 06 to S 01 with u * crossing from region VI to I, where S 06 and S 01 denote the operation sequences of ( sequence in a switching period.Consider that u * is approximated to be a constant in a switching period, the derivatives of ∆i with respect to the time are obtained from Equation ( 1) and depicted in Figure 9b, where (d∆i 1 /dt), (d∆i 2 /dt), (d∆i 3 /dt) are the derivatives of ∆i with respect to the time with u equal to V 0 , V 1 , V 6 , respectively.Assume the initial ∆i is zero to simplify the analysis.∆i will change in the directions of the derivatives of ∆i with respect to the time in sequence.There are trajectories of ∆i in a solid line and in a dotted line corresponding with S 06 and S 01 , as clearly shown by Figure 9c.Moreover, the trajectories of ∆i will gradually change from S 06 into S 01 with u * changing.
Energies 2018, 11, x FOR PEER REVIEW 10 of 20 period, the derivatives of Δi with respect to the time are obtained from Equation ( 1) and depicted in Figure 9b, where (dΔi1/dt), (dΔi2/dt), (dΔi3/dt) are the derivatives of Δi with respect to the time with u equal to V0, V1, V6, respectively.Assume the initial Δi is zero to simplify the analysis.Δi will change in the directions of the derivatives of Δi with respect to the time in sequence.There are trajectories of Δi in a solid line and in a dotted line corresponding with S06 and S01, as clearly shown by Figure 9c.Moreover, the trajectories of Δi will gradually change from S06 into S01 with u * changing.
In order to achieve a smooth switching of current error, the ideal switching point should be the zero-crossing of current errors according to Figure 9c, such that three-phase switches can switch smoothly.
Based on the above analysis, the switching point is determined by detecting whether current error exceeds the limit of the outer hysteresis bandwidth or not.In other words, the switching point cannot be selected as the zero-crossing point of current errors, which usually results in a low control accuracy and an unstable switching of three-phase switches that will affect the fixed-frequency control and regulation of the switches phase.

Smooth Switching of the Control Strategies in ST-FHCC
In ST-FHCC, when u * crosses the division boundary, the switching time of each phase is used to determine the u * location at first.Then, the zero-crossing point of current errors (according to the clock signal) is chosen as the switching point of mode 0 and mode 1 based on the u * location and predivided voltage-space-vectors diagram, such that a smooth switching of current errors and threephase switches can be realized.In order to achieve a smooth switching of current error, the ideal switching point should be the zero-crossing of current errors according to Figure 9c, such that three-phase switches can switch smoothly.
Based on the above analysis, the switching point is determined by detecting whether current error exceeds the limit of the outer hysteresis bandwidth or not.In other words, the switching point cannot be selected as the zero-crossing point of current errors, which usually results in a low control accuracy and an unstable switching of three-phase switches that will affect the fixed-frequency control and regulation of the switches phase.

Smooth Switching of the Control Strategies in ST-FHCC
In ST-FHCC, when u * crosses the division boundary, the switching time of each phase is used to determine the u * location at first.Then, the zero-crossing point of current errors (according to the clock signal) is chosen as the switching point of mode 0 and mode 1 based on the u * location and pre-divided voltage-space-vectors diagram, such that a smooth switching of current errors and three-phase switches can be realized.
For example, when u * crosses from region A to B, the operation sequence of voltage-space-vectors varies from S 11 to S 01 , where S 11 and S 01 denote the operation sequences of (V 7 , , respectively.The trajectories of current errors are depicted by Figure 10a, where α 0 , α 1 , α 2 , α 7 are the derivatives of ∆i with respect to time under the operations of V 0 , V 1 , V 2 , V 7 , respectively.The ideal switching point should be the zero-crossing point of current errors based on the clock signal in practice with the result that three-phase switches can switch smoothly, as shown in Figure 10b.For example, when u * crosses from region A to B, the operation sequence of voltage-space-vectors varies from S11 to S01, where S11 and S01 denote the operation sequences of (V7, V2, V1, V2, V7) and (V0, V1, V2, V1, V0), respectively.The trajectories of current errors are depicted by Figure 10a, where α0, α1, α2, α7 are the derivatives of Δi with respect to time under the operations of V0, V1, V2, V7, respectively.The ideal switching point should be the zero-crossing point of current errors based on the clock signal in practice with the result that three-phase switches can switch smoothly, as shown in Figure 10b.

Detailed Procedure of ST-FHCC
The detail procedure of ST-FHCC is depicted by Figure 11.The three hysteresis comparators are set to output 0 when the current errors exceed their upper bandwidths while set to be 1 when the current errors exceed their lower bandwidths.

Detailed Procedure of ST-FHCC
The detail procedure of ST-FHCC is depicted by Figure 11.The three hysteresis comparators are set to output 0 when the current errors exceed their upper bandwidths while set to be 1 when the current errors exceed their lower bandwidths.
The following example illustrates the process of obtaining the ST-FHCC in detail.When u * is located in region A, S a is fixed to be 1, and S b controls ∆i ab while S c controls ∆i ca .According to Equation (2), ∆i ab will increase when S b stays at 1 while ∆i ab will decrease when S b stays at 0. On the contrary, ∆i ca will decrease when S c stays at 1 while ∆i ab will increase when S c stays at 0. If the hysteresis comparator 1 outputs 1, it means that ∆i ab exceeds the lower bandwidth of the hysteresis comparator and needs to be increased.Thus, S 1 should be assigned to S b .Similarly, if the hysteresis comparator 3 outputs 1, it means that ∆i ca exceeds the lower bandwidth of the hysteresis comparator and needs to be increased.Thus, S 3 should be assigned to S c .Consequently, Table 3 can be obtained.
Table 3.The relationship between S 1 , S 2 , S 3 and S a , S b , S c .

The Location of u
The relationships

Detailed Procedure of ST-FHCC
The detail procedure of ST-FHCC is depicted by Figure 11.The three hysteresis comparators are set to output 0 when the current errors exceed their upper bandwidths while set to be 1 when the current errors exceed their lower bandwidths.The following example illustrates the process of obtaining the ST-FHCC in detail.When u * is located in region A, Sa is fixed to be 1, and Sb controls Δiab while Sc controls Δica.According to Equation ( 2), Δiab will increase when Sb stays at 1 while Δiab will decrease when Sb stays at 0. On the contrary, Δica will decrease when Sc stays at 1 while Δiab will increase when Sc stays at 0. If the hysteresis comparator 1 outputs 1, it means that Δiab exceeds the lower bandwidth of the The overall smoothly transitive fixed frequency hysteresis current control (ST-FHCC) procedure.
According to S a , S b , and S c , ∆h a , ∆h b , and ∆h c can be obtained by solving Equation ( 5), respectively.Since S b controls ∆i ab while S c controls ∆i ca , ∆h b should be the bandwidth of hysteresis comparator 1 to limit ∆i ab , such that ∆h b is assigned to ∆h 1 while ∆h c should be the bandwidth of hysteresis comparator 3 to limit ∆i ca , such that ∆h c is assigned to ∆h 3 .Therefore, Table 4 can be obtained.Remark 2. The outer hysteresis comparator employed in S-FHCC is no longer required in ST-FHCC.The control strategy under mode 0 (mode 1) is switched into that under mode 1 (mode 0) in the overlapping areas produced by the parallelogram regions of mode 0 and those of mode 1, as two controllable current errors are always under control by two switches in the overlapping areas.Therefore, the current errors will not exceed the larger bandwidth of the outer hysteresis comparator with the switching procedures of ST-FHCC implemented.Furthermore, the outer hysteresis comparator is no longer required to switch the control strategies in ST-FHCC.

Case Studies
The effectiveness of ST-FHCC is evaluated and compared with that of S-FHCC [30] by power systems computer aided design/electromagnetic transients including DC (PSCAD/EMTDC).The test system is given by Figure 12, in which the APF is used to compensate the harmonic currents produced by the rectifier and the DC motor, while the system parameters are given as L s = 0.001 H, L L = 0.003 H, L f = 0.0125 H, R d = 37 Ω, L d = 0.015 H, u c = 800 V.The root-mean-square (RMS) of phase-to-phase voltage u s is 380 V and the switching frequency of APF is 10 kHz.In addition, i a , i b , i c are the line currents of APF; i La , i Lb , i Lc are the line currents of the non-linear load; i sa , i sb , i sc denote the line currents supplied by the three-phase power grid, respectively.

The Effect of Harmonics Compensation in ST-FHCC
Figure 13a,b show the load current of phase a and the system current of ST-FHCC after the harmonics compensation, which demonstrate that the harmonic current produced by the load can be effectively compensated.Moreover, Figure 13c illustrates that the current error of phase a is under control which is bounded between −0.8A to 0.8 A. Figure 13d shows that the total harmonic distortion (THD) value of isa is reduced dramatically from 24.43 to 5.01% after isa is compensated by APF.

The Effect of Harmonics Compensation in ST-FHCC
Figure 13a,b show the load current of phase a and the system current of ST-FHCC after the harmonics compensation, which demonstrate that the harmonic current produced by the load can be effectively compensated.Moreover, Figure 13c illustrates that the current error of phase a is under control which is bounded between −0.8A to 0.8 A. Figure 13d shows that the total harmonic distortion (THD) value of i sa is reduced dramatically from 24.43 to 5.01% after i sa is compensated by APF.

The Effect of Harmonics Compensation in ST-FHCC
Figure 13a,b show the load current of phase a and the system current of ST-FHCC after the harmonics compensation, which demonstrate that the harmonic current produced by the load can be effectively compensated.Moreover, Figure 13c illustrates that the current error of phase a is under control which is bounded between −0.8A to 0.8 A. Figure 13d shows that the total harmonic distortion (THD) value of isa is reduced dramatically from 24.43 to 5.01% after isa is compensated by APF.

The Performance of the Current Errors in S-FHCC
The current error ∆i ab obtained by S-FHCC is given in Figure 14a, which shows that the control strategy is discontinuous with mode 1.When S-FHCC switches from S a = 1 to S b = 1, the phase-to-phase current error ∆i ab exceeds the limit, i.e., 2 A, of the outer hysteresis comparator.Here, Figure 14b enlarges the results obtained near 0.0238 s, in which it can be found that S-FHCC can only be switched after the current error exceeding the limit of the outer hysteresis comparator.During the switching, the transient process of current error phase and three-phase switches operation is disordered, which greatly affects the control of switching frequency and the switches phase.

The Performance of the Current Errors in S-FHCC
The current error Δiab obtained by S-FHCC is given in Figure 14a, which shows that the control strategy is discontinuous with mode 1.When S-FHCC switches from Sa = 1 to Sb = 1, the phase-tophase current error Δiab exceeds the limit, i.e., 2 A, of the outer hysteresis comparator.Here, Figure 14b enlarges the results obtained near 0.0238 s, in which it can be found that S-FHCC can only be switched after the current error exceeding the limit of the outer hysteresis comparator.During the switching, the transient process of current error phase and three-phase switches operation is disordered, which greatly affects the control of switching frequency and the switches phase.which corresponds to the analysis of Table 2.Moreover, the current errors and operation of three-phase switches can change smoothly before and after the switching.

The Performance of the Current Errors in ST-FHCC
In addition, Figure 16 depicts the three-phase switching times by counting how three-phase switch signals rise and fall during 0 s-0.06 s.One of the three-phase switches does not operate in Region E, F, A and B, which is denoted by the horizontal straight lines.The operation times of the phase-C switch can be calculated as 20,147 times per second during 0.02 s-0.03 s.As shown by Figure 15b, the phase-C switch operates twice during a clock-pulse period due to the regulating phases of the switches.Therefore, the switching frequency is 10,073.5Hz.Besides, the switching frequencies of the phase-A and the phase-C switches can be calculated as an approximate 10 kHz.Furthermore, the average switching frequencies of three-phase can be evaluated as an approximated 10 kHz even during 0 s-0.06 s.To summarize, the switching frequency can remain constant at 10 kHz by ST-FHCC.
Energies 2018, 11, x FOR PEER REVIEW 16 of 20 the switches.Therefore, the switching frequency is 10,073.5Hz.Besides, the switching frequencies of the phase-A and the phase-C switches can be calculated as an approximate 10 kHz.Furthermore, the average switching frequencies of three-phase can be evaluated as an approximated 10 kHz even during 0 s-0.06 s.To summarize, the switching frequency can remain constant at 10 kHz by ST-FHCC.

The Trajectories of Current Errors by S-FHCC and ST-FHCC
Figure 17a,b compares the switching trajectories of the current error space-vector of S-FHCC and ST-FHCC, respectively.One can see that ST-FHCC has no disorder of current error when switched at the zero-crossing point.In contrast, S-FHCC presents a significant disorder of current error when switched at the zero-crossing point.Lastly, from Figure 18a,b, one can find that ST-FHCC can achieve a more stable and smoother current error compared to that of S-FHCC.

The Trajectories of Current Errors by S-FHCC and ST-FHCC
Figure 17a,b compares the switching trajectories of the current error space-vector of S-FHCC and ST-FHCC, respectively.One can see that ST-FHCC has no disorder of current error when switched at the zero-crossing point.In contrast, S-FHCC presents a significant disorder of current error when switched at the zero-crossing point.
Energies 2018, 11, x FOR PEER REVIEW 16 of 20 the switches.Therefore, the switching frequency is 10,073.5Hz.Besides, the switching frequencies of the phase-A and the phase-C switches can be calculated as an approximate 10 kHz.Furthermore, the average switching frequencies of three-phase can be evaluated as an approximated 10 kHz even during 0 s-0.06 s.To summarize, the switching frequency can remain constant at 10 kHz by ST-FHCC.

The Trajectories of Current Errors by S-FHCC and ST-FHCC
Figure 17a,b compares the switching trajectories of the current error space-vector of S-FHCC and ST-FHCC, respectively.One can see that ST-FHCC has no disorder of current error when switched at the zero-crossing point.In contrast, S-FHCC presents a significant disorder of current error when switched at the zero-crossing point.Lastly, from Figure 18a,b, one can find that ST-FHCC can achieve a more stable and smoother current error compared to that of S-FHCC.Lastly, from Figure 18a,b, one can find that ST-FHCC can achieve a more stable and smoother current error compared to that of S-FHCC.

Discussions
 Note that the proposed approach of variable hysteresis bandwidth is different from the conventional one, which is derived from a simplified single-phase model of a power system with APF [32][33][34].In the ST-FHCC, the hysteresis bandwidth in the next switching period is derived from the hysteresis bandwidth in the current period according to Equation (5), which is obtained in a way that the midpoint of switch signals in the state of 0 is accurately synchronized to the clock pulse with a constant frequency, which can simultaneously realize a fixed frequency and a regulation of switch phases.In other words, two controllable current errors controlled by two switches will cross the zero point of the clock pulse accurately.As a result, the two operated switches will always operate twice during two clock pulses.Hence, the switching period will be equal to that of the clock pulse.Besides, the phases of two controllable current errors will be opposite while the two corresponding switches will be symmetrical with the switch phases regulated, as depicted in Figure 5. Since Δiab + Δibc + Δica = 0, the uncontrollable current error will decrease dramatically.In addition, the operated voltage-space-vectors will all be optimal. S-FHCC is based on the division of three parallelogram regions in Figure 2, and the control strategies under mode 0 or mode 1 will be switched only if the current errors exceed the limit of the outer hysteresis bandwidth, which cannot be avoided, as illustrated in Figure 4.In contrast, ST-FHCC is based on the flexible division of six sub-regions in Figure 8, and the control strategies under mode 0 and mode 1 are switched alternatively by considering the location of u * .The reason is that two controllable current errors are always under control by two switches no matter what control strategy under mode 0 or mode 1 is adopted in the overlapping areas produced by the parallelogram regions of mode 0 and those of mode 1.Thus, one can switch the control strategy under mode 0 (or mode 1) into that under mode 1 (or mode 0) at the zerocrossing of current errors in the overlapping areas in order to smoothly transit the boundary determined by the three parallelogram regions under mode 0 (or mode 1), as shown by Figure 7b.As a consequence, the current errors will not exceed the limit of the outer hysteresis comparator and the outer hysteresis comparator is no longer required.

Conclusions
In this paper, an ST-FHCC has been developed for APF.An improved approach to regulate the hysteresis bandwidth has been presented to obtain the fixed frequency and the regulation of switch phases based on OVSV.To enhance S-FHCC, a flexible division of the voltage-space-vectors diagram has been proposed and the control strategies under mode 0 and mode 1 are switched alternatively to

•
Note that the proposed approach of variable hysteresis bandwidth is different from the conventional one, which is derived from a simplified single-phase model of a power system with APF [32][33][34].In the ST-FHCC, the hysteresis bandwidth in the next switching period is derived from the hysteresis bandwidth in the current period according to Equation (5), which is obtained in a way that the midpoint of switch signals in the state of 0 is accurately synchronized to the clock pulse with a constant frequency, which can simultaneously realize a fixed frequency and a regulation of switch phases.In other words, two controllable current errors controlled by two switches will cross the zero point of the clock pulse accurately.As a result, the two operated switches will always operate twice during two clock pulses.Hence, the switching period will be equal to that of the clock pulse.Besides, the phases of two controllable current errors will be opposite while the two corresponding switches will be symmetrical with the switch phases regulated, as depicted in Figure 5. Since ∆i ab + ∆i bc + ∆i ca = 0, the uncontrollable current error will decrease dramatically.In addition, the operated voltage-space-vectors will all be optimal.• S-FHCC is based on the division of three parallelogram regions in Figure 2, and the control strategies under mode 0 or mode 1 will be switched only if the current errors exceed the limit of the outer hysteresis bandwidth, which cannot be avoided, as illustrated in Figure 4.In contrast, ST-FHCC is based on the flexible division of six sub-regions in Figure 8, and the control strategies under mode 0 and mode 1 are switched alternatively by considering the location of u * .The reason is that two controllable current errors are always under control by two switches no matter what control strategy under mode 0 or mode 1 is adopted in the overlapping areas produced by the parallelogram regions of mode 0 and those of mode 1.Thus, one can switch the control strategy under mode 0 (or mode 1) into that under mode 1 (or mode 0) at the zero-crossing of current errors in the overlapping areas in order to smoothly transit the boundary determined by the three parallelogram regions under mode 0 (or mode 1), as shown by Figure 7b.As a consequence, the current errors will not exceed the limit of the outer hysteresis comparator and the outer hysteresis comparator is no longer required.

Figure 1 .
Figure 1.Equivalent circuit of a three-phase active power filter (APF).

Figure 1 .
Figure 1.Equivalent circuit of a three-phase active power filter (APF).

Figure 3 .
Figure 3. Switching fixed frequency hysteresis current control (S-FHCC). e controls Δibc; Sa controls Δiab.Sc=0; Sa controls Δica; Sb controls Δibc Only if Sc lost the control of Δibc, such that Δibc exceed the limit of the outer hysteresis comparator

Figure 4 .
Figure 4.The limit exceeding of current error resulted by the transition of u*.(a) u * moves from region VI to region I; (b) current error exceeds the limit.

Figure 4 .
Figure 4.The limit exceeding of current error resulted by the transition of u*.(a) u * moves from region VI to region I; (b) current error exceeds the limit.

Figure 5 .
Figure 5. Phase of switches is regulated.

Figure 5 .
Figure 5. Phase of switches is regulated.

Figure 5 .
Figure 5. Phase of switches is regulated.

Figure 6 .
Figure 6.Operation sequences of switches and voltage-space-vectors variation.(a) voltage-spacevectors operation without phase regulation; (b) optimal voltage space vector (OVSV) operation with phase regulation.

Figure 6 .
Figure 6.Operation sequences of switches and voltage-space-vectors variation.(a) voltage-space-vectors operation without phase regulation; (b) optimal voltage space vector (OVSV) operation with phase regulation.

Figure 7 .
Figure 7. Smooth transition of voltage-space-vectors and the operation of three-phase switches.(a) u * moves from region VI to region I; (b) the operation process of the three-phase switches.

Figure 7 .
Figure 7. Smooth transition of voltage-space-vectors and the operation of three-phase switches.(a) u * moves from region VI to region I; (b) the operation process of the three-phase switches.

Figure 8 .
Figure 8.The flexible division of the voltage-space-vectors diagram combined with mode 0 and mode 1.(a) Symmetry division; (b) asymmetry division.

Figure 8 .
Figure 8.The flexible division of the voltage-space-vectors diagram combined with mode 0 and mode 1.(a) Symmetry division; (b) asymmetry division.

Figure 9 .
Figure 9.The ideal switching point in S-FHCC.(a) the operation sequence of voltage-space-vectors and three-phase switches; (b) the derivatives of Δi with respect to time; (c) three-phase switches operation.

Figure 9 .
Figure 9.The ideal switching point in S-FHCC.(a) the operation sequence of voltage-space-vectors and three-phase switches; (b) the derivatives of ∆i with respect to time; (c) three-phase switches operation.

Figure 10 .
Figure 10.The control mode switching in the zero-crossing point of current errors.(a) Current errors changes smoothly (S01:solid line; S11: dotted line); (b) operation of three-phase switches.

Figure 10 .
Figure 10.The control mode switching in the zero-crossing point of current errors.(a) Current errors changes smoothly (S 01 :solid line; S 11 : dotted line); (b) operation of three-phase switches.

Figure 13 .
Figure 13.Load current, current supplied by power system after compensation, and current error of phase a between actual current of phase a and its reference.(a) current iLa; (b) current isa; (c) current error of phase a between actual; (d) THDs of iLa and isa current of phase a and its reference.

Figure 13 .
Figure 13.Load current, current supplied by power system after compensation, and current error of phase a between actual current of phase a and its reference.(a) current iLa; (b) current isa; (c) current error of phase a between actual; (d) THDs of iLa and isa current of phase a and its reference.

Figure 13 .
Figure 13.Load current, current supplied by power system after compensation, and current error of phase a between actual current of phase a and its reference.(a) current i La ; (b) current i sa ; (c) current error of phase a between actual; (d) THDs of i La and i sa current of phase a and its reference.

Figure 14 .
Figure 14.The performance of the current errors obtained by S-FHCC.(a) Δiab obtained by S-FHCC; (b) detailed current errors when Δiab exceeds its limit.

Figure
Figure15aprovides the changes of the phase-to-phase current error Δiab and the hysteresis bandwidth obtained during 0.02 s to 0.03 s, whose detailed variation is clearly shown by Figure15bobtained during 0.0254 s to 0.0258 s.

Figure 14 .
Figure 14.The performance of the current errors obtained by S-FHCC.(a) ∆i ab obtained by S-FHCC; (b) detailed current errors when ∆i ab exceeds its limit.

Figure 17 .
Figure 17.The trajectory of the current error space-vector in the switching point.(a) S-FHCC; (b) ST-FHCC.

Figure 17 .
Figure 17.The trajectory of the current error space-vector in the switching point.(a) S-FHCC; (b) ST-FHCC.

Figure 17 .
Figure 17.The trajectory of the current error space-vector in the switching point.(a) S-FHCC; (b) ST-FHCC.

Table 1 .
Control strategies in different parallelogram regions under mode 0 and mode 1.
c controls ∆i bc S a controls ∆i ab .P 12 S b = 1 S c controls ∆i bc S a controls ∆i ab .

Table 1 .
Control strategies in different parallelogram regions under mode 0 and mode 1. Sa controls Δica Sb controls Δibc

Table 2 .
The detailed control strategies based on the flexible division.