The Parallel Virtual Inﬁnite Capacitor Applied to DC-Link Voltage Filtering for Wind Turbines

: We propose the parallel virtual inﬁnite capacitor (PVIC) concept, which refers to two virtual inﬁnite capacitors (VIC) connected to the same DC link and sharing one capacitor, one tuned to low frequencies (LF) and one tuned to high frequencies (HF). A PVIC can suppress voltage variations (ripple) in a wider frequency range than a usual VIC. The LF-VIC is controlled by a sliding mode controller to regulate the low-frequency component of the voltage to its reference value, and by a proportional-integral (PI) controller to maintain its state of charge within the desired operating range and achieve the ‘plug-and-play’ pattern of PVIC. The HF-VIC is controlled by another sliding mode controller to limit the high-frequency ripples and also to keep its state of charge within a reasonable operating interval. As our main application, we use the PVIC to replace a DC-link capacitor for voltage ﬁltering on the DC link of a doubly fed induction generator (DFIG), which is driven by a WindPact (WP) 1.5-MW wind turbine under different grid conditions with turbulent wind input. The simulation study indicates that the PVIC provides much better voltage stabilisation than a DC-link capacitor with the same capacitance, especially in the low frequency range.


Introduction
Capacitors are commonly used for DC voltage smoothing (ripple elimination) in power electronic circuits, such as in photovoltaic systems, fuel cells, LED drivers, electric (or hybrid) vehicles and their chargers, power factor correctors (PFC), the power train of wind power generators, etc. Low-frequency ripple suppression requires large capacitance, which could be provided by electrolytic or super-capacitors. However, such capacitors suffer from low reliability and low operating voltages [1][2][3]. Many ideas have been proposed as alternatives to large capacitors (or to achieve better performance with the same capacitance), and such circuits are known as "power filters", "active capacitors" or "ripple eliminators" (see, for instance, [4,5] (for the output voltage variations of controlled rectifiers) Refs. [6,7] (using stacked swithed capacitors for LED drivers), Refs. [8][9][10][11] and there are many more). We refer to [10,12] for nice surveys of this area. In this line of research, the virtual infinite capacitor (VIC) concept has been introduced in [13], which is a circuit able to eliminate random low-frequency voltage fluctuations [13][14][15]. The idea is to create a nonlinear capacitor where the plot of voltage as a function of charge has a flat segment, where the dynamic capacitance is infinity (see Figure 1b).
The VIC circuit contains a bidirectional DC-DC converter which (using the terminology from Kassakian et al. [16]) is a canonical switching cell (see Figure 1a for a simplified circuit not showing sensing, control or drivers). In [17], the control algorithm and operation of the VIC have been redesigned to work in discontinuous conduction mode (DCM), which has enabled substantially reducing the switching frequency (and using snubber circuits to reduce the switching losses). As can be seen in Figure 1b, there are three regions of operation for the VIC. The control algorithms are designed individually for these three regions. The most important is the normal operating range (the middle segment in Figure 1b) where the voltage V across the VIC remains at a reference value V re f , while the charge Q can vary in the interval [Q min , Q max ]. In this range, the gate control signals q andq are controlled in such a way as to transfer the excess charge that would create voltage ripples in V to the capacitor C s and thus constrain the voltage V to a small neighbourhood of V re f . This VIC configuration was found to be quite effective in suppressing unpredictable voltage fluctuations, through both simulations [17,18] and experiments [15,19].  When we compute the output impedance of a VIC (as is done, for instance, in [15]), we find that it is high for frequencies near zero (as it should), it has a region where it is very low (as desired), but it grows for higher frequencies. The region of low impedance depends on the control algorithm. There are applications where there are two main sources of ripple, in two distinct frequency ranges. For instance, in the power conversion system of a wind turbine, the DC-link voltage ripple can originate from variations of wind speed (low frequency), grid imbalance (twice the grid frequency) and switching ripple from the main converters (relatively high frequency). To deal with such situations, we introduce here the parallel virtual infinite capacitor (PVIC) concept. The PVIC is composed of two VICs, one for low-frequency (LF) and one for high frequency (HF), which share a common capacitor. We also propose a new soft switching topology (see Figure 2) to be used for both the LF-VIC and the HF-VIC, which of course improves the efficiency compared with earlier designs. The operation of this new circuit will be explained in Section 2. For the LF-VIC, we design a sliding mode controller (SMC) to regulate the DC-link voltage in the frequency range of this VIC. A proportional-integral (PI) controller is used to maintain the charge in this VIC in its normal operating range and realise the 'plug-and-play' feature of the PVIC. Another sliding mode controller is designed for the HF-VIC to suppress the high-frequency component of the ripple voltage and at the same time to keep the state of charge (SoC) of this VIC within the normal operating range. Note that sliding mode controllers are robust and appropriate for nonlinear variable structure systems [20][21][22][23] such as power converters [24][25][26][27][28].
The PVIC can be applied to many systems where voltage filtering in a wide frequency range is required. In this paper, a wind power generator is chosen to demonstrate the performance of the PVIC. Wind power will continue to be an important source of electric power. At the end of 2017, the cumulative installed wind turbine capacity was over 539 GW, which can cover over 5% of the electric power demand of the world. Wind power capacity is expected to rise to 840 GW in 2020 [29,30]. Doubly fed induction generators (DFIG) have been widely used for wind turbines with power ratings of 1.5-MW and above since 1996 [31]. In this paper, the PVIC is used for DC-link voltage filtering on the DC link of a 1.5-MW DFIG wind turbine system. A DFIG wind turbine is quite vulnerable to grid faults because the DFIG stator is directly connected to the grid. Grid faults may cause voltage variations at the DFIG terminals, which may lead to high currents causing the DC-link voltage to drop, preventing the converters from working, or to rise too high, which may damage the capacitors and IGBTs [32,33]. During grid faults, the DC-link voltage should be maintained at the normal level to enable the converters to apply the voltage ride through an algorithm, especially to guarantee the control performance of the rotor side converter. Even without grid faults, DC-link voltage fluctuations need to be limited to guarantee accurate power regulation [33]. PVIC serves as a solution to maintain the DC-link voltage within reasonable bounds, regardless of the grid conditions. Different electronic circuits used for active ripple suppression on the DC link of wind turbine have been proposed (see [34,35] and the references therein). Figure 3 shows the configuration of a DFIG driven by a 1.5-MW wind turbine connected to the power grid via back-to-back converters and transformers. Typically, the rotor side converter is controlled to maximize wind power extraction, and the grid side converter is controlled to stabilise the DC-link voltage. In this paper, we use a grid-connected DFIG model [36,37], driven by the popular WindPact (WP) 1.5-MW wind turbine [38][39][40] under turbulent wind generated by NREL Turbsim [41]. We have replaced the DC-link capacitor seen in Figure 3 with a PVIC with the same total capacitance and we compare the performance of the DC-link capacitor with that of the PVIC in stabilizing the DC-link voltage. The comparisons under different grid faults demonstrate the capability of the PVIC in handling unpredictable voltage fluctuations. In order to introduce disturbances to the DC link, we have simulated faults at the infinite bus. The simulations indicate that the PVIC is more effective in suppressing the voltage fluctuations than the equivalent DC-link capacitor (i.e., a DC-link capacitor with the same capacitance), regardless if there are grid disturbances or not.
The structure of the paper is as follows. In Section 2, we briefly explain the operation principle and control of the VIC and especially of the soft switching version from Figure 2. In Section 3, we present our simulation results for the the DC-link voltage filtering performance of the PVIC. We compare the performance of the PVIC with that of the equivalent (in capacitance) DC-link capacitor.

The PVIC and Its Control
To improve efficiency, we use a new soft switching circuit shown in Figure 2, where the two snubber capacitors C sn are small. This is an improvement of the circuit appearing in ( [42], Figure 2). The upper switching unit is composed of the S 1 , S 3 , C sn , D 1 and D 3 , in which S 1 is synchronized with S 3 . The lower switching unit is similar. The inductors are not coupled.
We take the upper switching unit (see Figure 2) as an example to explain the soft switching mechanism. This is really soft switching only in discontinuous conduction mode (DCM), while in continuous conduction mode (CCM) it is only zero voltage switching-off. Immediately after S 1 and S 3 are turned off, the voltage on the left side of C sn will remain close to V without dropping abruptly because C sn takes time to get charged via D 1 and D 3 until V C sn reaches V, which implies zero voltage switching-off of S 1 and S 3 . The main current will flow via D 6 , decreasing at a slope of −V s /L, until one of the following two events occurs: either the current reaches zero and then remains zero for some time (DCM) or the switches are controlled to turn on again. Immediately after S 1 and S 3 are turned on, the voltage on the right side of C sn will suddenly jump to V + V C sn ≈ 2V. Then, C sn starts to release energy through the switches and the upper inductor L to charge C s , until V C sn reaches nearly zero or the switches are controlled to turn off. This discharging period of C sn is relatively short because the time constant √ LC sn is small. Hence, practically all the energy that was stored in C sn is saved into C s . However, if the inductor current at the moment of switching-on is not zero, then we do not have zero current switch-on. After switch-on and after C sn is emptied, the inductor current (flowing through the switches and the diodes D1 and D3) grows, at a slope of (V − V s )/L. Of course, the rising current will stop once the switches are turned off, which closes the whole cycle. The story for the lower switching unit is similar. Figure 4 shows the circuit realisation of a PVIC, which replaces the DC-link capacitor. q L ,q L ∈ {0, 1} are binary signals, andq L = 1 − q L . The switches S 1 L and S 3 L are on if q L = 1. The switches S 2 L and S 4 L are on ifq L = 1. The binary signals q H andq H are defined in a similar way. The capacitor C s H is smaller than the capacitor C s L . The remaining components in the HF-VIC are same as in the LF-VIC. The control of PVIC is attained by the LF-VIC controller and HF-VIC controller. The former regulates low-frequency components of the voltage V to the neighbourhood of its reference, while the latter suppresses the high-frequency ripples of the voltage V. During the power up process (see the left segment in Figure 1b), a constant duty cycle D pow_up and a constant PWM switching frequency f pow_up are applied to both VICs. During the protection region of operation (the right segment in Figure 1b), all the switches are turned off to avoid the overcharge of C s L and C s H . The transitions between the three processes are controlled using a state machine, which was detailed in [19]. Next, we discuss the control algorithm in the normal operation range. The low-frequency signals V l f & i l f and high-frequency signals V h f and i h f are acquired by passing V and i through a low pass filter with the corner frequency f l : According to Figure 4, we have Considering (1), we can rewrite (2) as where i s L L , i s L H , i s H L , and i s H H are defined by Multiplying both sides of (2) with Subtracting (5) from (2), we get Then, the state equations of the PVIC can be written as: These state equations are considered only in the operating range, which is Ω defined by: For subsequent analysis, we set the following lower and upper bounds:

Control of the LF-VIC
The LF-VIC controller is composed of a sliding mode voltage controller and a PI charge controller. Their control objectives are to control the low-frequency component of the voltage to its expected reference in normal operation process and, restrain the LF-VIC's SoC within its normal operating range, respectively.

Voltage Control of the LF-VIC
We use a sliding mode controller to regulate the low-frequency component of V. We employ a sliding function with the states x = V l f i s L V s L T and disturbance i l f , based on ( [13], Section 6): where we set k 1 > 0. The sliding surface Γ L is the set of all the possible x ∈ Ω for which Note that the energy stored in the two inductors of the PVIC can be roughly written as (9) represents the energy in L L . The remaining part V re f i h f − V s H i s H , which represents the energy in L H , is included in the HF-VIC controller, which will be discussed in Section 2.2. The absolute values of k 1 and k 2 should be small enough to diminish deviation between V l f and V re f when x is controlled to be within Γ L .
To reduce chattering effects and limit operating frequencies within a controllable range, we use the hysteresis-modulation (HM) sliding mode control [24] to determine the binary switching signals q L andq L : where is a small positive number. In the stability analysis later, we assume = 0 for simplicity but without loss of generality.
The sliding mode controller is designed according to the following steps. Firstly, the hitting condition should be satisfied to ensure that the state trajectory is guided to the sliding surface. After that, when the states are within a small vicinity of the sliding surface, the existence condition needs to be satisfied to maintain the states within the neighbourhood of the sliding surface and always direct the states towards the desired surface [20,25].
In this paper, we describe the hitting condition by whereṠ Combining (6) and (13), we geṫ When S L (x) > 0 for all x ∈ Ω\Γ L , q L = 0. To satisfy (12), we require thaṫ Here,i l f is set to bei l f ∈ [−i max L ,i max L ]. Note that it is hard to limit a current derivative term in reality. This limit is allowed to be violated under some circumstances such as the abrupt current change due to some faults. However, it will be brought back by the control schemes. A sufficient condition for (15) iṡ When S L (x) < 0 for all x ∈ Ω\Γ L , q L = 1. To satisfy (12), we havė That is, a sufficient condition for (17) iṡ From (16) and (18) we set where F Lb is derived from: and Note that it is reasonable to have inequalities (20) and (21) Then, the existing condition for this SMC is From (10), we have based on which the inequalities (15) and (17) can be written aṡ Since Ck 2 V re f > 0, (24) and (25) can be written as and The parameters k 1 and k 2 should be chosen to fulfill the inequalities (15), (17), (26), and (27) to satisfy both the hitting condition and existing condition, which are the sufficient conditions to attain the successful control. The details about the selection of k 1 and k 2 will be discussed in Section 2.3.

Charge Control of the LF-VIC
In the application of grid connected DFIG system, a charge control scheme is developed to regulate the LF-VIC's state of charge (V s L ) by coupling a PI controller with the controller of grid side converter. Since the charge controller is required to operate more slowly than the voltage controller, the average of V s L (i.e., V s Lavg ) is controlled, which is acquired by passing V s L through a low pass filter with the corner frequency f c (see Figure 5). In the voltage control of DC-link capacitor, the voltage V is fed back to the controller of grid side converter. Herein, the voltage V * rather than V is injected. V * is the estimated value of V obtained from the LF-VIC's state of charge through a PI controller: In this way, the control scheme of the grid side converter is not violated, realising a 'plug-and-play' pattern for the PVIC.

Control of the HF-VIC
For the control of HF-VIC, both voltage control and charge control are implemented by a sliding mode controller whose sliding function is The sliding surface Γ H is the set of all the possible The expression V re f i h f − V s H i s H appearing in (28) represents the power stored in L H , which is included in the HF-VIC controller. V sre f H − V s Havg is the charge control term in this sliding function. As with the charge control of the LF-VIC, the average of V s H (i.e., V s Havg ) is regulated to realise a much slower response of the charge control than the voltage control. V s Havg is obtained by passing V s H through a low pass filter with the corner frequency f c . The absolute values of the parameters k 3 and k 4 should be very small to guarantee the accuracy of the control.
The hysteresis-modulation (HM) sliding mode control is also applied to the HF-VIC, using the same as in (11): The hitting condition is described as for all x ∈ Ω\Γ H . Here,V s Havg is limited asV s Havg ∈ [−V s Havg max ,V s Havg max ], whereV s Havg max should be small due to the slow change of V s Havg . Similarly as in Section 2.1, when S H (x) > 0 and S H (x) < 0, we haveṠ respectively. Here,i h f is limited asi h f ∈ [−i max H ,i max H ], that is, the sufficient conditions for (30) and (31) areṠ andṠ To fulfil (32) and (33), we set where F Hb is derived from and To fulfil the inequalities (35) and (36), Similarly as in Section 2.1, we get and The parameters k 3 and k 4 should be chosen to satisfy the inequalities (30), (31), (38) and (39), so that the state trajectory will converge and stabilise at the sliding surface Γ H . The details about the selection of k 3 and k 4 will be discussed in Section 2.3.

Parameter Selection
In order to limit the deviation between V and its reference V re f , the absolute values of the parameters k 1 , k 2 , k 3 and k 4 should be small. We apply the interior-point optimization algorithm to find the boundaries of these four parameters, which are embedded in the nonlinear programming solver 'fmincon' in Matlab (MathWorks).
The parameters' initial values are all set to be zero. The related operating boundaries are listed in Table 1. The optimal boundaries for the parameters k 1~k4 are

Simulation Study
The simulations are conducted using a grid-connected DFIG model [36,37] driven by the WP 1.5-MW wind turbine model [38][39][40]. The parameters of the DFIG are listed in Table 2. The hub height of wind turbine is 84 m. The rated wind speed is about 12 m/s. The blade length is 33.25 m and the maximum blade chord is 8% of blade radius [43]. Table 2. Parameters of the 1.5-MW doubly fed induction generator (DFIG) model [36,37]. The NREL FAST (Fatigue, Aerodynamics, Structures, and Turbulence) code [38] is used to simulate dynamic responses of the turbine. FAST takes aerodynamics, control and electrical (servo) dynamics, and structural (elastic) dynamics of the turbine into account. FAST is interfaced with Matlab/Simulink through a Simulink S-Function block. During simulations, this block calls the FAST Dynamic Library, which has integrated all the FAST modules [38] and is compiled as a dynamic-link-library (DLL).

DFIG Parameters Values
NREL TurbSim [41] is utilised to generate stochastic, full-field, and turbulent wind flows for simulation studies. The International Electro-technical Commission (IEC) Kaimal spectral model [44,45] in Turbsim is applied to generate the wind condition as shown in Figure 6a, with the category A (most turbulent) IEC NTM (normal turbulence model). The mean hub-height longitudinal wind speed is 12 m/s. Note that the average sampling frequency of the LF-VIC controller is smaller than that of HF-VIC controller in the simulations, which are approximately 45 kHz and 100 kHz, respectively.  The voltage filtering performances of two configurations are compared: a 15 mF DC-link capacitor and a PVIC as in Figure 4, where the total capacitance of C, C s L and C s H is 15 mF. Tables 3 and 4 list the parameters of the electronic components in PVIC and control parameters of PVIC, respectively. Table 3. Parameters of the electronic components in PVIC (see Figure 4).

Components in PVIC Configuration
C 7 mF C s L 6 mF C s H 2 mF C sn 1 nF L L 10 µH L H 10 µH Table 4. Control parameters of the PVIC.

Parameters Values Parameters
Values Firstly, the simulation is conducted without grid disturbance under the turbulent wind input (see Figure 6). Figure 6a,b demonstrate the turbulent wind input and the DC-link voltage stabilised by DC-link capacitor and PVIC. Figure 6c,d illustrate the SoC of PVIC (i.e., V s L and V s H ). It is clear that when there is no grid disturbance, both configurations can stabilise the DC-link voltage V to its reference, and PVIC reduces about 30% of the voltage fluctuations compared with the equivalent DC-link capacitor (see Figure 6b), which is mainly achieved by HF-VIC controller to suppress the high-frequency ripple due to the fast switching of two converters. The SoC of the LF-VIC and HF-VIC are successfully controlled to the vicinity of their references by the charge control schemes explained in Section 2.
Then, the simulations are conducted under four types of grid disturbances with the same turbulent wind input (Figure 6a). The first case is the frequency variation. In reality, the frequency, as a key factor to judge the power quality, is allowed to vary within a very narrow range during normal operation. Here, we test the performance of the PVIC and a DC-link capacitor under a one-second large sinusoidal grid frequency variation with an amplitude of 1 Hz and a period of 0.5 s. Figure 7a,c show this grid condition and the performances of PVIC and DC-link capacitor. Note that the V l f and V h f of the DC-link voltage are obtained according to (1).
The second type of the tested grid disturbances is the balanced three-phase voltage sag and swell. This is one of the most common power disturbances, which is usually caused by abrupt reduction or increase in loads. The grid voltage is altered four times by ±0.15 p.u. and each change is kept for 15 grid cycles (250 ms) (see Figure 7b,d).
The third case of the disturbance test is the harmonics. In reality, a small range of harmonics due to the nonlinear loads, transformer magnetisation nonlinearities, rectification, etc. is allowed in the power system, which may introduce the high-frequency ripple to DC-link voltage. We inject a combination of a negative-sequence 1st order harmonic (with the magnitude of 0.1 p.u.) and negative-sequence 3rd order harmonic (with the magnitude of 0.1 p.u. and phase shift of 35 • ), lasting for 1 s. Figure 8a,c show this grid condition and the voltage filtering performance.
Finally, we combine the above frequency variation and harmonic disturbances as the fourth case. That is, both high-frequency and low-frequency ripples are introduced to the DC-link voltage. The grid condition and the voltage filtering performance are shown in Figure 8b,d.
From Figures 7 and 8, it is clear that the PVIC achieves 10-20 times smaller variations in the DC-link voltage than the equivalent DC-link capacitor during these tested grid disturbances. This is because the oscillations in the DC-link voltage are transferred into the capacitors C s L and C s H of the PVIC. The same conclusion can be obtained under other grid conditions, such as unbalanced voltage sag and swell, the phase shift in voltage, different harmonic injections, frequency steps variations, or the combinations of some of these faults.

Conclusions
We have introduced the concept of parallel virtual infinite capacitor (PVIC), which refers to a low-frequency (LF) virtual infinite capacitor (VIC) and a high-frequency (HF) VIC working on a common DC link and sharing one capacitor. It is meant to suppress voltage ripple in a wider frequency band than what one VIC could achieve. The low frequency ripple is regulated by a sliding mode controller, and a PI controller is applied to maintain the LF-VIC within its operating range. Another sliding mode controller is applied to suppress high-frequency fluctuations while at the same time keeping the HF-VIC's state of charge within the normal range. The PVIC has been applied to replace the DC-link capacitor between two back-to-back converters in a grid-connected DFIG wind turbine system. The simulations were conducted under normal grid operation and four types of grid disturbances with turbulent wind (frequency variation, three-phase voltage sag and swell, harmonics and frequency variation with harmonics). The results indicate that the PVIC provides outstanding ripple suppression performance regardless of the low-frequency and high-frequency fluctuations, individually or together. In comparison with an equivalent DC-link capacitor, the PVIC reduces the DC-link voltage ripple by about 30% during normal grid operation, and approximately 10-20 times during the tested grid disturbances. The PVIC can also be applied to other systems that have a large capacitor for voltage filtering, such as PFC, photovoltaic power generators, vehicle chargers, etc.