Transient Stability Enhancement Using a Wide-Area Controlled SVC: An HIL Validation Approach

: This paper presents a control scheme of a wide-area controlled static VAr compensator (WAC-SVC) and its real-time implementation in a hardware-in-the-loop (HIL) simulation scheme with three control objectives: (1) to increase the critical clearing time, (2) to damp the power oscillations, and (3) to minimize the maximum line current. The proposed control scheme considers a correction strategy to compensate the delays up to 200 ms. In addition to this, a generator tripping scheme based on synchrophasor measurements to determine the proximity to the loss of synchronism is proposed. A delay compensation algorithm based on polynomial approximations is also developed. The proposed WAC-SVC is experimentally validated using a Real-Time Digital Simulator platform (RTDS), industrial communication protocols, a commercial device for PMU-based control implementations, and digital relays with PMU capability. The real-time simulation results conﬁrm its effectiveness and feasibility in real industrial applications. Furthermore, practical guidelines to implement this kind of control schemes are provided.


Introduction
Due to the historical occurrence of several blackouts [1][2][3], significant research efforts have been motivated to investigate their causes to prevent future events [4][5][6]. That research suggests that monitoring systems have to be improved [7]. An essential factor to achieve this goal is the wide-area measurement system (WAMS), and, more specifically, the use of phasor measurement units (PMUs). Although many PMUs have been installed in power systems around the world for monitoring purposes and protection schemes, recently they are being incorporated in automatic control systems [6,[8][9][10][11]. Due to the high sampling rate and accuracy, compared with Supervisory Control and Data Acquisition (SCADA) systems, it has been possible to close the control loop not only locally, but in a wide-area-introducing in this way the wide-area control systems (WACS) [12,13].
The use of flexible AC transmission systems (FACTS) as actuators in WACS, leads to robust real-time control systems able to swiftly mitigate perturbations on the network. The most common FACTS device in literature and in the industry used for WACS applications is the static VAr compensator (SVC). The SVC has been commonly used for VAR regulation using local measurements, allowing for increasing the power transfer capabilities, controlling the voltage at a specific node, and enhancing stability margins, among others [14][15][16]. With WAMS, it is possible to improve these

Description of the Problem and Its Proposed Control
When a power system experiences a large momentary disturbance (e.g., short circuit, transmission line tripping, loss of generation, among others), the machines' speeds and angles increase during and after the disturbance. The power systems controllers such as Automatic Voltage Regulator (AVR), Power System Stabilizer (PSS), governor, and FACTS help the system to reach a new steady state. However, if the stability is not recovered, the speeds and angles keep increasing, and the system loses synchronism. In this regard, this paper proposes a generator tripping scheme to complement the proposed WAC-SVC and avoid machine damage in case the system could not reach a stable condition. This tripping scheme tracks the machine angle difference and the acceleration power in actual time to establish the closeness to the loss of synchronism and shut down the generator before it loses synchronism. This tripping logic disconnects the generator if and only if the system were to lose synchronism.
In addition to this, an efficient and straightforward strategy to compensate the communication delay is proposed so as to implement the WAC-SVC and the generator tripping scheme. These proposals are detailed, implemented and evaluated in offline and HIL simulations in the following sections.
Firstly, the test system is introduced for the explanatory purposes. Later on, the generator tripping scheme is explained methodically and validated against critical three-phase faults. After that, the development of the control strategy for the minimization of the line current along the SVC-compensated transmission line is presented. Then, the wide-area control for damping power oscillations is introduced. Finally, the delay compensation is thoroughly explained. Even though the generator tripping scheme is enabled the entire time in the proposed WAC-SVC, this is validated before the results section to focus that section on the current minimization and the damping oscillation control actions.

Test System
To explain the implementation and test the proposed WAC-SVC, the five-bus two-machine power system is used (shown in Figure 1). The capacity of machine A is 1150 MVA, and its active power reference is 1100 MW. The size of machine B is 5000 MVA. Each generator is a synchronous machine with its hydraulic turbine and controllers: AVR (IEEE ST1), PSS (IEEE PSS1A) and governor. The reference voltage at bus 1 and bus 5 is 13.8 kV. Transmission lines are modeled using a distributed parameter transmission line model. An SVC is connected at bus 4 and its capacity is ±230 MVAr at 500 kV. The convention used indicates that negative power corresponds to the inductive zone of the SVC. A 5000 MVA load is connected at bus 3; this load is represented by a constant power model. Appendix A gives all the parameters used.

Generator Tripping Scheme
Figure 2 is used to explain the proposed tripping scheme. P e (t) represents the active electric power delivered by the synchronous machine, P m is the mechanical power supplied to the generator by the prime mover, and δ(t) is the angular displacement of the rotor machine in electrical values. The three different P − δ curves represent the prefault, fault and postfault scenarios. The equal-area criterion (EAC) states that the machine will be stable if deceleration area (A 2 ) is equal or bigger than the acceleration area (A 1 ) [26]. However, since the P − δ curves are time-varying due to the control and compensation actions, it is challenging to establish a priori fulfillment of the EAC just after the fault clearing time in industrial applications. Figure 2a shows typical dynamic behavior of a stable case against a large disturbance. Originally, the system is operating at the equilibrium point a, where P e (t) = P m and δ(t) = δ 0 . When the fault strikes at t = t f , P e (t) suddenly changes from point a to point b and P e (t) becomes smaller than P m . Therefore, the rotor starts to accelerate, and the machine speed commences to exceed the synchronous speed (Figure 2a, bottom, red waveform), and thus the δ(t) starts to increase (Figure 2a, bottom, green waveform). Then, the fault is cleared at point c and suddenly the operating point d is reached in the postfault condition. At this operating point, d, P e (t) > P m and the rotor machine starts to slow down and reaches the synchronous speed at point e. However, even at this point, the machine is not in the final equilibrium point yet due to P e (t) > P m . Therefore, the machine continues reducing its speed to values below the synchronous speed. This oscillation process continues until the transient dies out and the machine settles down in the final steady-state.  Figure 2b shows the unstable case. Here, the machine does not reach the synchronous speed before reaching the critical point. Consequently, the machine starts to accelerate from δ(t) > δ un since P e (t) < P m [26].
As a conclusion, it is said that the machine is stable against a large disturbance if the machine reaches synchronous speed for the first time-after the fault clearance-before its angle reaches the critical point. A close-up of the critical and tripping points are shown in Figure 2c. Notice that, if the critical point exists, this is always between π/2 rad and π rad in the P − δ curve.
The basic idea to detect the unstable behavior after the fault clearance is to determine if the angle δ(t) keeps increasing just before it reaches the critical point δ un , as shown in Figure 2. To do this, we have to be able to measure or estimate in real time δ(t), P e (t), and P m . It is clear as per Figure 2 that, in the first swing, the system is in the deceleration area A 2 if δ(t) > π/2 rad and P e (t) > P m (P a < 0). The closeness between P e (t) and P m for δ(t) > π/2 rad gives the proximity to the critical point, and consequently to the instability. Figure 3 shows the proposed generator tripping scheme based on the previous explanations. Due to the simplicity of the equal-area criterion based on the classical model of transient stability, two conservative thresholds are added to establish the closeness to the tripping point before the machine starts to speed up again (Figure 2b,c).   Figure 4, the tripping condition is not reached. On the other hand, the tripping condition is actually reached as shown in Figure 5; the angle difference evolution when the machine is not disconnected is the one in red, and the one in blue is the response when the machine is disconnected just after the tripping condition is detected. The proposed generator tripping logic demonstrates its effectiveness as it disconnects the machine just when it is necessary and not before. Notice that, after the disconnection, the remaining system reaches a new steady-state. Be aware that the system loses synchronism if the machine A is not disconnected.  . Unstable case against a 12-cycle fault: the angle difference between bus 1 and bus 5 when the machine A is not disconnected (red) and when the machine A is disconnected according the proposed tripping logic (blue), the evolution of the power condition is in green, the angle condition is in blue, and the tripping signal is in red.
This logic allows the machines to remain connected to the power system to give time to their controllers and the proposed WAC-SVC to act and to stabilize the power oscillations. In addition, it prevents the generator from remaining connected under unsafe conditions. The next subsection describes the proposed control to increment the critical clearing time (CCT) and damp the power oscillations.

Control Strategy for the Minimization of the Line Current
The proposed control strategy for the minimization of the current magnitude along the SVC-compensated transmission line while maintaining the active power flow is described here.
As by-products, the power losses decrease, and the transferred active power along the line can increase since the reactive current component decreases.
On transmission lines, the Root Mean Squared (RMS) current varies along the line and its maximum value depends on the voltages at the ends of the line and the surge impedance load (SIL) [26,27]. For explanation purposes, consider the SVC-compensated transmission line section shown in Figure 6. The following equation gives the current profile along the line regarding its parameters and end voltages from the lossless long transmission line model [26]: where I 24 (x), V 2 , and V 4 are phasor quantities. x represents the distance to the sending end. I 24 (x) is the current at x, V 2 and V 4 are the voltage at sending and receiving ends, respectively, and is the transmission line length. γ is the propagation constant defined as √ ZY; for a lossless line Y = jωC and Z = jωL, therefore The objective is to supply the required active power at the sending end with the minimum value of the maximum RMS current along the line. Bear in mind that I 24 (x) is a complex variable, and its magnitude is: (I 24 (x)) and (I 24 (x)) are detailed in Appendix B. The position x Imax at which the current reaches its maximum RMS value is found by solving This assumption is true for lines transferring active power above its SIL; below the SIL, the maximum current is at one of the two ends. The maximum RMS current magnitude is found by substituting x Imax in Equation (3), i.e., |I 24 max |. Since an SVC is connected at the receiving end of the line, the voltage magnitude at this node can be regulated to minimize I 24 max . Therefore, the SVC voltage reference that minimizes the maximum current along the line is found by solving d|I 24max | d|V 4 | = 0 for |V 4 |, yielding the following result: Only the measurement of the sending end voltage is required to calculate the SVC voltage reference that minimizes the maximum current along the transmission line which can be observed in this equation. PMUs along with a delay compensation algorithm are used to implement Equation (4) in WAC-SVC.

Wide-Area Control for Damping Power Oscillations
Synchrophasor measurements can also be used for damping power system oscillations that consequently affect generator angular speeds. The power oscillations between two groups of machines or areas interconnected by a transmission link can be counteracted by adding the term k( f 1 − f 5 ) to Equation (4). The current control and damping oscillations strategies for the control reference calculation are synthesized in Equation (5): where f 1 and f 5 are the voltage oscillation frequencies of buses 1 and 5, respectively; and k is a proportional gain that weighs the damping oscillation term. An SVC is used in this work to follow the voltage reference given by Equation (5); however, a static compensator (STATCOM) can also be used instead [28,29].

Delay Compensation
The delay compromises the control performance, so it is necessary to implement an additional action to compensate it. This adverse effect can be worse than not having the SVC since delay increases the system oscillations, reduces the damping and the CCT. Figure 7 shows the typical time delays regarding the different stages involved in the WAC-SVC implementation. The total delay goes from 60 ms to 200 ms, approximately. However, this delay can be up to 400 ms or more, depending on the control application. The delay is time-varying since the phasor data concentrators (PDCs), in practical implementations, are configured to time-align and transmit simultaneously several synchrophasor data streams so as to be used for monitoring or control application. In the HIL implementation presented in this paper, the PDC function is executed by the RTAC. In real-life networks, the buses could be up to hundreds of kilometers apart. Therefore, the communication delays are not negligible. For this reason, an estimation process based on a polynomial fitting method is proposed to efficiently compensate the delays and allow the implementation of the proposed generator tripping scheme and the WAC-SVC. Refer to Appendix C for details.

HIL Implementation
HIL tests are now being increasingly used to assess and analyze the behavior of proposed controls, protections or algorithms because it is possible to detect some poor functioning or properties that are not considered or known in typical factory acceptance testing stages. Specifically, in the field of electrical power systems, it is uncommon to perform testing tasks in real-world systems; nonetheless, when the devices under test do not require power interchange, HIL tests are the best real-world approach in digital simulation.
The HIL implementation of the proposed generator tripping and WAC-SVC schemes consists of their programming in an industrial controller, and in the use of different communication protocols to send and receive information between the commercial devices. Commonly, commercially available controllers do not have sophisticated built-in functions, which makes it difficult to program complex control actions in these kind of devices. The following subsections present the HIL implementation details and guidelines.

Real-Time Test System Implementation
The real-time simulation platform used in this implementation is an RTDS. To reproduce the test power system, the RTDS must have at least two PB5 processor cards, a Giga Transceiver Analogue Output (GTAO) card for analog outputs, and a Giga Transceiver Network Interface (GTNET) card with enabled Generic Stream Encapsulation (GSE) protocol. In addition, four relays are necessary. In this case, we use two SEL-351S and two SEL-421. The relays must have an enabled PMU function. A GPS clock is required to timestamp the estimated phasors. Finally, the SEL-3530 RTAC (real-time automation controller) is used for programming the WACS, the time delay compensation method, and the generator tripping scheme [30]. Figure 8 shows the schematic representation of the HIL implementation. The power system is modeled and simulated in RTDS. The three-phase voltages of the buses 1, 2, 4 and 5 are sent to the relays using the analog output card. The four relays use the IEEE protocol C37.118 [31,32]   The RTAC receives and aligns the phasors according to their timestamp. Then, it executes the control strategy given by Equation (5) which is programmed in IEC 61131 language [33]. The resulting voltage reference signal for the SVC is sent back to the RTDS via Ethernet in the IEC 61850 GOOSE communication protocol [34,35]. GOOSE protocol is widely used in communications between protection devices and monitoring of electrical power systems [36]. The control signal is received by the RTDS and is assigned as the reference voltage to the internal control of the SVC. This follows the reference signal set by Equation (5) to complete the control action.

Device Configuration for Implementation
To reproduce this work, the following next steps are suggested: 1. Model the test system in RSCAD and perform dynamic simulation tests for assessing its correct behavior. 2. Connect external devices as shown in Figure 1. The GTAO card output voltage is ±10 V and the relays have a rated voltage input of up to 300 V (LN). Since a power amplifier is not considered in this implementation, a special cable is necessary to connect the RTDS with the relays. The special cable links the GTAO card with the low voltage card of each relay as shown in the relay manual [37,38]. 3. Configure each relay with 60 messages per second and select P as the PMU application. The user defines the IP address, the PMU ID, and the communication port. The user must also indicate the IP of the controller device, in this case, the RTAC. It is essential to ensure that the voltage measured by each relay corresponds to the voltage value in the respective bus of the power system implemented in the RTDS software. 4. Use the RTAC to perform the following three tasks: synchrophasors reception, algorithm programming, and sending of the control signal through GOOSE protocol. 5. Finally, configure the RTDS to receive GOOSE signals. It is necessary to have the GOOSE protocol in RTDS.
It is important to test each step separately beforehand to reduce error uncertainties and possible malfunctioning.

Results
This section presents the HIL results of the WACS implemented on the test system shown in Figure 1. Firstly, the system is used to evaluate the control strategy for the minimization of the maximum current along the line. Lastly, the proposed damping term is added and assessed against a three-phase bolted fault.

Assessment of the Control Strategy for the Line Current Minimization
Equation (4) gives the maximum current when the line is overloaded. Figure 9a shows the current along the SVC-compensated transmission line, i.e., the line between buses 2 and 4. The blue waveform corresponds to the current leaving bus 2, the pink one corresponds to the current entering bus 4, and the other waveforms correspond to intermediate currents along line 2-4. The system is initially in steady state with the SVC disconnected. At t = 1 s, the SVC starts the compensation using the voltage reference computed with Equation (4) to reduce the maximum current along the line. Notice how the maximum current is at the receiving end node (bus 4) and how it starts reducing as soon as the SVC is connected. Figure 9b,c shows the injected reactive power by the SVC and its voltage reference, respectively. Since the load is over the transmission line SIL and the reactive power is dominantly inductive, the reactive current component is inductive. This explains why the SVC is injecting its total capacitive reactive power.    As per Figure 9c, the voltage reference is dynamically changing about 1 pu according to Equation (4), but the voltage can only be taken to 0.95 pu due to the size of the SVC. A smaller maximum current along the line can be obtained using a larger SVC. With the actual SVC size, the maximum current is barely reduced a 4.3%.
To evaluate the effect of the SVC size, a steady-state analysis is performed. Figure 10 shows the maximum current along the line against the SVC reactive power and voltage. According to Figure 10a, it is possible to reduce the maximum current even more by injecting more reactive power.
On the other hand, Figure 10b shows the voltage on the SVC bus depending on the maximum current. For this no-SVC case, the bus voltage is 0.905 pu. As the injected reactive power increases, the SVC bus voltage increases and the maximum current decreases. The bus voltage is 0.95 pu when the SVC injects 200 MVAr. Figure 10a,b show that the voltage reference to minimize the maximum current is 1.069 pu. However, this reference implies injecting 800 MVAr, which exceeds the SVC capability.

Power Oscillations Damping Control
The purpose of this section is to evaluate the proposed WAC-SVC against power oscillations due to a 10-cycle three-phase bolted fault in the middle of the uncompensated transmission line. The short-circuit is cleared by simultaneously opening the breakers at the ends of this transmission line. A constant load model of 5000 MVA with a lagging power factor of 0.85 is used for representing the load at bus 3. The machine A supplies 1100 MW, and therefore the remaining line is over SIL after tripping the faulted line. Figure 11 shows the system response for the three different scenarios: the yellow waveform for the case without SVC, red for the proposed WAC-SVC implemented in the RTDS simulation software (RTDS-based WAC-SVC), and the blue one for the proposed delay-compensated HIL-based WAC-SVC. Notice that the second oscillation is the main problem for the case without SVC. For the other two cases, the responses almost overlap each other, demonstrating the effective implementation of the proposed WACS in the HIL environment. During the fault and the first swing after the fault clearing, the SVC injects its total capacitive reactive power and therefore, the delay compensation at the beginning of the fault is not needed. An extra logic is programmed to ensure the injection of the total capacitive reactive power after the fault is detected and during the first sliding window of the delay compensation method, i.e., 200 ms for this case. Figure 12 shows the SVC voltage reference through the prefault, fault, and postfault conditions. On the other hand, Figure 13 shows the reactive power injected by the SVC. Notice that, at the fault condition, the SVC is only capable of injecting around 90 MVAr due to the voltage sag. The SVC keeps injecting its full capacity during an additional 200 ms and then tracks the voltage reference given by Equation (5) after the fault is cleared. Notice that the SVC automatically behaves as described in [39] when using the proposed WACS. Due to the electromagnetic transients after the fault clearance, the SVC injects an oscillating reactive power as shown in Figure 13. Figures 11-13 demonstrate how the response of the delay-compensated HIL-based WAC-SVC match with the response only obtained through digital simulation without communication delays. These results show that the proposed delay compensation method and its implementation in an industrial real-time automatic controller work efficiently. By using industrial PMU and communication protocols as well as a satellite clock, a behavior as good as that obtained in ideal conditions without time delays is also achieved.   Figure 14 shows the P-δ phase portrait of the RTDS-based WAC-SVC. It can be seen here that the dynamic of the P-δ plot matches the theoretical plot described in Section 3 [26,39]. During the fault, machine A accelerates and can only supply around 500 MW. Machine A active power oscillates from a maximum of 1786 MW to a minimum of 493 MW after the fault is cleared. Two oscillations afterwards, the system practically reaches a steady state. §' 0 0.. For further comparison, the critical clearing time (CCT) is computed for these operating scenarios. The case without SVC has a CCT of 180 ms, the case with SVC in local control mode has a CCT of 186 ms, the proposed RTDS-based WAC-SVC has a CCT of 225 ms, and, finally, the proposed delay-compensated HIL-based WAC-SVC gives a CCT of 218 ms. Notice that the SVC case with local control mode increments the CCT by 6 ms in comparison to the system without SVC; this barely represents an improvement of 3.22%. On the other hand, using the proposed control fully implemented in the RTDS software, the CCT increases 45 ms or 25%. The HIL implementation has a CCT increment of 38 ms (21.1%) due to the use of real industrial devices, different communication protocols, and an online delay compensation. The increase of the CCT also represents an increment of the power transfer capability. Ref. [40] indicates an increment of up to 15 MW for every increased millisecond.

Alternative Case Studies
This section presents some extra studies for a deeper assessment of the WAC-SVC. This case consists of the same test system presented in the previous section but with the SVC-compensated line operating under the SIL. Machine A now supplies 950 MW with a rated capacity of 1000 MVA. In addition, the lagging load power factor changes from 0.85 to 0.95. Figure 15 shows the system response for the three different scenarios: the yellow waveform for the case without SVC, red for the proposed RTDS-based WAC-SVC, and the blue one for the proposed delay-compensated HIL-based WAC-SVC. In this case, the second oscillation problem is present for the no-SVC scenario. For this scenario, the damping is lower than in the previous case study. For the other two scenarios, the second angle swings are smaller than their respective first swings, and the damping is as good as in the over-SIL case. A negligible difference between the RTDS and the HIL implementations of the proposed WAC-SVC is also observed.  Figure 16 shows the machine A angle response against a larger clearing time of 181.67 ms for further validation of the proposed WAC-SVC. In the case without SVC, machine A loses synchronism after three oscillations. In the case with the SVC, the machine can maintain synchronism although with poor damping; after six swings, the system still oscillates. Finally, the systems with the RTDS-based WAC-SVC and delay-compensated HIL-based WAC-SVC reach the steady state after only two oscillations.  Figures 17 and 18 show the P-δ curves from Figure 16. Figure 17 compares the no-SVC (in orange) and delay-compensated HIL-based WAC-SVC (in blue) responses. Point A indicates the steady state of the system before the fault starts. The fault is cleared by opening the faulted line at point B. Note that, from A to B, in both cases, the behavior is similar; however, the WAC-SVC slightly reduces the acceleration area. Points C1 and C2 indicate the maximum angle for the first swing without SVC and with the WAC-SVC, respectively. These points (C1 and C2) show that the power transfer with the WAC-SVC is higher during the deceleration area within the first swing. Notice that the WAC-SVC reduces and increases the acceleration and deceleration areas by injecting reactive power when the machine angle is increasing, but it absorbs reactive power when the angle is decreasing. This process is repeated until the power oscillations dampen out. These important phenomena are spotlighted in zones Z1 and Z2 of Figure 17. Figure 18 compares the SVC with local control (green) and the delay-compensated HIL WAC-SVC (blue) responses. These cases have similar behavior from Point A to point C. After point C, the improvement of the proposed control can be pinpointed within Z1 and Z2. According to Z1, the WAC-SVC reduces the acceleration area more than the local controlled SVC. This is achieved as the former absorbs reactive power while the latter continues injecting reactive power, whereas, in Z2, the WAC-SVC increases the deceleration area by injecting reactive power. The local control also injects reactive power in this part, but it is not enough to dampen the oscillations quickly.

Discussion
The wide-area controlled SVC showed satisfactory results regarding the proposed objectives, increasing loadability and minimizing the maximum current flow through the SVC-compensated transmission line. In addition, CCT increased up to 25% and 21.1% with the proposed WAC-SVC in simulation and HIL implementation, respectively. The maximum current along the SVC-compensated line can be minimized to up to 119 A; due to the capacity of the SVC used, this was reduced to 67 A, which corresponds to a reduction of 8.2% in conduction losses along the line. On the other hand, the WAC-SVC swiftly dampens out the power oscillations as compared with the SVC in local control mode. Furthermore, the proposed machine tripping logic demonstrated that it can detect disconnection instantly, just before the machine loses synchronism.
One of the principal benefits of the proposed WAC-SVC is that its implementation does not depend on a mathematical model. Another significant contribution is that the control was implemented with synchrophasors and control devices, which, in fact, are used for industrial applications.

Conclusions
This paper has presented a wide-area controlled static VAr compensator (WAC-SVC) and its Hardware-in-the-loop implementation with both industrial PMUs and areal-time automatic controller.
The obtained results have demonstrated the feasibility of this type of control systems using the latest technology.
The proposed control allowed to increase the critical clearing time up to 21.1% (38 ms) and 17.2% (32 ms) concerning the cases without SVC and with the local controlled SVC. In addition to this, a generator tripping scheme and a delay compensation algorithm to complement the WAC-SVC were proposed.