New Switched-Dual-Source Multilevel Inverter for Symmetrical and Asymmetrical Operation

Abstract: The increasing integration of large solar PV and wind farms into the power grid has fueled, over the past two decades, growing demands for high-power, high-voltage, utility-scale inverters. Multilevel inverters have emerged as the industry’s choice for megawatt-range inverters because of their reduced voltage stress, capability for generating an almost-sinusoidal voltage, built-in redundancy and other benefits. This paper presents a novel switched-source multilevel inverter (SS MLI) architecture. This new inverter shows superior capabilities when compared to existing topologies. It has reduced voltage stress on the semiconductor, uses fewer switches (i.e., reduced size/weight/cost) and exhibits increased efficiency. The proposed SS MLI is comprised of two voltage sources (V1, V2) and six switches. It is capable of generating five-level output voltage in symmetric mode (i.e., V1 = V2) and seven-level output voltage in asymmetric mode (i.e., V1 6= V2). We present simulations results (using MATLAB R ©/Simulink R ©) for fiveand seven-level output voltages, and they strongly support the validity of the proposed inverter. These positive results are further supported experimentally using a laboratory prototype.


Introduction
The past couple of decades has seen huge investments in renewable resources (RES) as a way to reduce carbon footprint.These initiatives have resulted, in recent years, in the installation of utility scale wind and solar PV farms.The operations of such MW-scale plants require high voltage/power multilevel inverters (MLIs), leading to the proliferation of MLI [1,2].MLIs can be categorized into three types:neutral-point-clamped (NPC) [2,3], flying-capacitor (FC) [4,5], and cascaded H-bridge (CHB) topologies [6,7].Some research have also proposed hybrids of the above types [8,9].The main advantages of MLIs over their traditional 2-level counterparts are improved power quality, reduced filter requirements, lower electromagnetic interference, and lower dv/dt stress on loads [10,11].
A shortcoming of NPC topology is an unbalance of the neutral point leading to uneven thermal distribution among the semiconductor devices, increase in harmonics, and reduction of power quality [12].FC inverters also suffer from capacitor voltage imbalance issues, which lead to a deterioration of power quality and an increase in blocking voltages.They also require larger capacitor banks and additional pre-charging circuitry.CHB MLIs suffer from input DC leakage current that could damage, for example, PV panels and pose safety problems [13,14].However, CHB topology has a lot of advantages -modularity, fewer number of components,symmetric and asymmetric operating modes (i.e., equal and unequal DC sources), etc.
Many recent studies on the CHB topology have focused on generating more voltage levels by using switched-capacitor (SC) or switched-source (SS) MLI configurations.The SC MLIs [15,16] aim to produce more output voltage levels with a single or minimal number of power supplies and a series of self-balancing capacitors.However, they suffer from increased voltage stress on the switches and power dissipation in the increasing number of series diodes [15].Several SS MLIs are proposed in [7,17].Unlike the SC configuration where capacitors are switched in series/parallel combinations, the

Architecture
The basic unit of the proposed MLI (see Fig. 1) is comprise two DC power sources (V 1 and V 2 ), four unidirectional switches (S 1 , S 2 , S 3 and S 4 ), and two bidirectional switches (S 5 and S 6 ).This basic unit, it is capable of generating 5-level output voltage (i.e., V ab ), when V 1 = V 2 (i.e., symmetric mode operation), and 7-level output voltage when V 1 = V 2 (i.e., asymmetric mode operation).The basic unit can be cascaded to generate more voltage levels.If m number of basic units are cascaded as shown in Fig. 2 , the inverter can generate up to (2 m+1 + 1) and (2 2m+1 − 1) (m = 1, 2, 3, . ..) output voltage levels for symmetric and asymmetric operations, respectively.
In order to avoid short-circuiting of the DC power sources, only one of the left side switches (i.e., S 1 , S 3 , S 5 ) can conduct at any instant.Similarly, only one of the right side switches (i.e.,S 2 , S 4 , S 6 ) can be ON at the same time.That is, where S k denotes the switching function of switch k (k = 1, 2 . . ., 6), and takes the value of 1 when ON, and 0 when OFF. Based on (1), Table 1 shows all the switching states of the basic unit and the resulting inverter output voltage.It consists of three null states Based on (1), Table 1 shows all the switching states of the basic unit and the resulting inverter output voltage.It consists of three null states (i.e., . m cascaded units to generate more voltage levels.
Table 1.Switches states for basic unit ) and six active states.The three redundant null states may b utilized to achieve different control objectives.The authors did not investigate this in this paper.In Table 1, the states shown in light-gray (i.e, all except 4) are the states utilized in this paper.The bidirectional switches protect the inverter from short circuits when it operates in asymmetrical mode.
The use of bidirectional switches distorts the output waveform (at low voltage levels, but is insignificant at medium high voltage level applications) due to the voltage drop in each one of the diodes of the rectifier bridge (two diodes forward biased simultaneously, V drop ≈ 2 × 0.7 = 1.4 V).
and six active states Table 1 shows that there are three redundant null states (0V output).The states shown in light-gray are the ones used in this paper.The bidirectional switches protect the inverter from short circuits when it operates in asymmetrical mode.The use of bidirectional switches distorts the output waveform (at low voltage levels, but is insignificant at medium high voltage level applications) due to the voltage drop in each one of the diodes of the rectifier bridge (two diodes forward biased simultaneously, V drop ≈ 2 × 0.7 = 1.4 V).

Operation principle
The generation of the multilevel voltage output is based on the switching states given in Table 1.
For example, to produce a 7-level output (V ab ), at least one null state (i.e., state 1, 4 or 9) and all the active states (i.e.; 2, 3, 5, 6, 7, and 8) are fired in a sequence to achieve the 7-level output.For uniform power dissipation among the six switches, two null states (i.e., 1 and 9) are utilized; with state 1 during the positive half-cycle and state 9 in the negative half-cycle.The Phase Disposition PWM (PD-PWM) is selected based on its superior performance [19], but any PWM method may be used to control the semiconductor switches.Fig. 3 show the current commutation for each switching state.For example, to produce (V 1 + V 2 ) in the positive half-cycle, switches S 1 and S 3 must be turned ON (i.e., state 5 in Table 1).The current flow is as shown in Fig. 3e.Fig. 3 show the current commutations for all the 7 voltage levels.Note that if V 1 = V 2 , a maximum of 5-level output can be realized.

Comparison with similar topologies
In this section, the proposed topology is compared with the topologies presented in [20,21], and the conventional cascaded H-bridge topology also discussed in [21].The comparison is made in terms of (i) total number of semiconductor devices , (ii) number of active components in current path (conduction losses) and voltage stress that each switch will be required to handle.

Number of semiconductor devices
The number of semiconductor devices have an impact on the cost and size/weight of the MLI unit; being able to generate the same number of voltage levels in the output of the inverter by using less number of switches will lower cost and at the same give a compact inverter.Fig. 4a and Fig. 4b show the number of switches (N sw ) needed to generate the same number of voltage levels (N l ) in the output for the different topologies in symmetric and asymmetric mode respectively.In symmetric mode (Fig. 4a), it is obvious that the proposed proposed topology outperforms the 3 other topologies with the lowest switch count for the same voltage level.In asymmetric mode (i.e., Fig. ??, however, the proposed topology fares better at lower voltage levels (N l ≤ 50), but this advantage diminishes at higher voltage levels.

Number of semiconductors in current path
Unlike in deal cases when we assume a switch or diode can turn-on or turn-off instantaneously without any power loss, real semiconductor switches have a finite switching transition time.This finite transition period is accompanied by power losses transients [22].Hence, the less number of switches required to produce a voltage level implies less power losses.Fig. 5a and Fig. 5b show the number of switches in the current path for the same voltage levels for the different topologies in symmetric and asymmetric mode respectively.The proposed topology performs better than in both modes resulting in higher efficiency at every voltage level.

Total standing voltage
Another important factor that should be taken into consideration when comparing the topologies is the minimum voltage rating of the switches.This minimum voltage rating, which will influence on the price and size of the switches, is related to the voltage stress that they need to handle in blocking state.This is also called standing voltage and the total standing voltage is obtained by addition of the blocking voltage requirement of each switch of a topology.
For comparison purposes, a value of 1V was assumed for V dc .Fig. 6a and Fig. 6b show the total standing voltage in symmetric and asymmetric modes respectively for all the topologies.In both symmetric and asymmetric modes, it can be shown that the proposed topology outperforms all others topologies.

Conclusions
In this paper, a new topology for switched-source multilevel inverter (SS MLI) has been proposed.
The structure and principle of operation are discussed and validated by both theoretical simulations and experiments.The basic unit can operated in symmetric and asymmetric modes.The new SS MLI topology is compared to three similar SS MLI topologies in terms of the number of switches required to generate a voltage level, the number of switches in current path (power losses) and total standing voltage the switches need to handle.The proposed topology outperforms the other topologies in most of the scenarios, presenting a significant reduction on the total cost and size of the unit, as well as a reduction in power losses.MATLAB/Simulink simulations and experiments using a laboratory prototype are presented for 5-and 7-level operations. (e)

Figure 1 .
Figure 1.Structure of the proposed topology as standalone.

Fig 7
Fig 7 shows a laboratory prototype built to validate the proposed topology.Simulations were carried out using MATLAB/Simulink.The semiconductor switches are IGBT IXGN120N60A3D1 with voltage and current ratings of 600 V, 120 A, respectively.The gate control signals were implemented using OPAL-RT OP5700 RCP/HIL FPGA-based Real-time Simulator.Two low power DC sources were engaged in supplying the required voltages.Table 2 list specifications of the inverter used for both simulations and experiment.

Fig. 8a shows
Fig. 8a shows the simulation results of the converter output voltage and load current waveforms the 5-level (symmetrical) operation.The THD of the voltage and current waveforms are 28.08% and 1.46%, respectively.The corresponding experimental waveforms for the symmetrical operations are shown in Fig. 8b.The experimental waveforms confirm accurate 5-level output voltage, having a current waveform with small THD.The results of the asymmetrical operation (7-level) are presented in

Fig. 9 .
Fig. 9. Fig. 9a) show simulated voltage and current waveforms whilst Fig. 9b present the corresponding experimental waveforms.The THD of the voltage and current waveforms for the 7-level operation are 19.00% and 1.13%, respectively.As in the case of the symmetrical operation, the experimental waveforms confirm accurate 7-level output voltage, with an almost sinusoidal current waveform.The presented results clearly verify the feasibility of the proposed inverter topology.

Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 12 March 2018 doi:10.20944/preprints201803.0081.v1 SS
[18]iguration uses instead multiple DC sources to achieve the voltage levels.This configuration is inherently suited for applications where there are multiple DC sources such as in battery storage, solar PV or fuel cells.In the SS configuration, a higher number of voltage levels can be obtained when the DC sources have different amplitudes (asymmetric operation)[18]than the symmetric topology (all