HIL Co-Simulation of Finite Set-Model Predictive Control Using FPGA for a Three-Phase VSI System

The conversion and control for the utilization of power generated from energy sources can be performed using a power electronic converter system. The voltage source inverter (VSI) is one of the commonly used converter topologies, being controlled by a switching control algorithm for power conversion. Finite set-model predictive control (FS-MPC) is a modern switching control algorithm and has received significant attention due to its predictive nature. In this paper, the implementation of FS-MPC is presented for the load-side current control of a three-phase VSI system using an integrated platform of MATLAB/Simulink and Xilinx system generator (XSG). The XSG provides the functionality of digital design and intuitive implementation of field-programmable gate array (FPGA) controlled systems. The additional functionality of hardware-in-the-loop (HIL) co-simulation using FPGA is used for the testing and validation of controller performance. The controller performance is validated through three platforms: MATLAB/Simulink, XSG and HIL co-simulation using ZedBoard Zynq evaluation and development FPGA kit.


Introduction
In recent years, the energy demand has been growing at a rapid rate and causing major global concern related to the depletion of nonrenewable energy sources and global warming due to environmental pollution. Accordingly, to fulfill the rise in energy demands and reduce the use of nonrenewable energy sources, energy from renewable sources is required to be generated more and more in the future for clean and green energy without affecting the environment [1][2][3]. Solar energy and wind energy are the prominent renewable sources to generate power. However, power conversion and control is required to use the generated power from solar and wind efficiently. Voltage source inverter (VSI) power topology has been widely utilized for the controlled and efficient conversion of electrical power. The applications of VSI systems include industrial drives, active filters, high power factor ac-dc converters, vehicular systems, uninterruptible power supplies (UPS), and the grid connection of renewable energy systems [4][5][6]. The design of a suitable controller is essential for the efficient and controlled conversion of electrical power. Different current control techniques have been employed for three-phase VSI systems and studied extensively in the last decades.
The current control methods that have been developed for the VSI system can be categorized as conventional and modern controllers/linear and nonlinear controllers. The conventional linear controllers such as pulse width modulation (PWM) and space vector modulation (SVM) require carrier-based modulators. Nonlinear controllers such as hysteresis current controllers (HCC), which are based on comparators, require high switching frequency for effective operation. The conventional linear and nonlinear controllers have been widely studied and developed for the three-phase VSI system applications [7][8][9]. In addition to these conventional control techniques, advanced controllers are also employed to improve the performance of the VSI system. However, the increased complexity and computational burden of the advanced controllers are the prime concern for their implementation.
The model predictive control (MPC) technique is one of the advanced controllers employed for power converters because of their advantages as compared to the conventional controllers, such as better dynamic performance, handling of multi-input multi-output (MIMO) cases, and flexibility for the inclusion of constraints and nonlinearities [10][11][12][13]. The intuitive design of the controller based on the predictive model and cost function-based selection of the optimized switching state are additional features of MPC. MPC strategies are broadly classified as continuous set-MPC (CS-MPC) and finite set-MPC (FS-MPC) [14]. The CS-MPC computes continuous control signals with constant switching frequency by using a modulator, whereas FS-MPC implements the MPC algorithm by utilizing the discrete nature of the power converter and applies the switching signals directly to the power converter without the need for an external modulator. FS-MPC is designed to reduce the computational burden of the algorithm by utilizing the set of possible switching states of power converters for solving the optimization problem online.
MPC has been proven as a mature strategy for power converters and drives applications such as three-phase neutral-point-clamped systems [15,16], active front-end rectifiers [13,17], cascaded H-bridge converters [18,19], flying capacitor converters [16,20], and matrix converters [13,21]. The practical implementations of MPC for power converters are mainly based on software-based control using a microprocessor/digital signal processor (DSP) [13,[22][23][24][25][26]. These micro-programmable solutions have advantages such as simple circuitry, software-based control, and flexible control adaptability to different applications. However, these have some disadvantages, such as delay in the computation of the optimized switching state. This delay problem has been clearly recognized and some modifications have been given for its compensation [13,22]. In addition, they require a high processing power for the implementation of complex controllers.
Considering the above mentioned limitations, the field-programmable gate array (FPGA) represents an effective alternative because of its parallel processing environment for practical implementation [27,28]. FPGA is considered as the better option for controller designing and prototyping due to its characteristics of configurability and programmability [29,30]. However, real-time controller implementation using FPGA has been found to be difficult and requires specialized training in the hardware description language (HDL). Therefore, prototype designing is a complex and time-consuming task, even for skilled researchers or engineers, with an increasing level of complexity [29,31].
The Xilinx system generator (XSG) platform provides a virtual FPGA environment for the designing, testing, and development of digital controllers. The integrated platform of MATLAB/ Simulink-XSG provides the functionality of automatic HDL code generation that can be further utilized for the straightforward implementation of FPGA-based experimental system prototypes without the additional knowledge of HDL [32][33][34]. XSG provides a modelling-based design approach for digital system implementation. Therefore, XSG-based system modelling is required for the development of real-time systems using FPGA through automatic HDL code generation. Further, the recent availability of a model-based FPGA design platform integrated with MATLAB/Simulink provides the functionality of hardware-in-the-loop (HIL) co-simulation.
The HIL co-simulation is a way to test the controller by including actual hardware and moving a step forward towards the realism of the software-based simulated system. The software-based simulation of a plant system or control system can be substituted using actual hardware to perform HIL co-simulation by interacting with a computer. HIL co-simulation can be used as a platform to validate the controller using the actual hardware by interacting with the plant system simulated by the computer. In addition, the platform can be used for the development of novel control strategies without using an actual plant system that can be damaged during the testing of controller. This paper proposes a novel implementation of the FS-MPC through modelling in an XSG environment integrated with MATLAB/Simulink for the current control of a three-phase VSI system using a motor as the load. The modelled FS-MPC algorithm is validated using HIL co-simulation using the FPGA by interacting with the VSI system simulated in MATLAB/Simulink. The step-by-step implementation of the controller includes the design of the FS-MPC in MATLAB/Simulink, the modelling of the controller in XSG, and the HIL co-simulation validation for the three-phase VSI system. The paper is organized as follows: Section 2 reviews the working principle of the FS-MPC, including the three-phase VSI system model. The modelling of the FS-MPC in XSG and HIL co-simulation are presented in Section 3. The performance of the FS-MPC controller is discussed using results of the software-based simulation and the HIL co-simulation in Section 4. Conclusions of the paper are presented in Section 5.

FS-MPC
The FS-MPC is based on the discrete-time model of a three-phase inverter, where a limited number of possible switching states contributes to the evaluation for the prediction of the future behavior of the variables for each switching state. An optimum switching state is selected and directly given to the power switches without any modulation stage in each sampling interval. The schematic diagram of the FS-MPC is demonstrated in Figure 1. The working principle of the FS-MPC is based on the current control of the load using predictive model and optimization criteria to generate the switching signals for the VSI. The motor load in Figure 1 is represented by an RL load with back electromotive force (EMF). The load current i L and back-EMF e of each phase fed to the predictive model and the future load currents are predicted. The predicted load currents i L p are used for generation of switching signals through the minimization of a cost function g. The formulation of the predictive model and the cost function is described in the following subsections.

Inverter System
The power circuit of a three-phase VSI is shown in Figure 2, where V dc is the dc voltage; v aN , v bN , and v cN are the phase-to-neutral voltages of inverter; i La , i Lb , and i Lc are the load currents; R is the load resistance; L is the load inductance; and e a , e b , and e c are the back-EMF in each phase, respectively. The switching states are determined by the gating signals S a , S b , and S c , as shown in Table 1. The switching states S can be expressed in vector form as: The output voltage space vectors generated by the inverter are defined by: Then, the load voltage vector v i can be related to the switching state vector S by: Considering all possible switching combinations of gating signals, eight switching states and hence eight voltage vectors are obtained as shown in Table 2. The load current dynamics can be expressed by the vector equation: where the balance three-phase load current i L and the three-phase load back-EMF e can be represented in space vector form as: e a + e j2π/3 e b + e j4π/3 e c (6) For simplicity and to reduce computational burden, the inverter voltage vector v i , load current i L , and back-EMF e can be represented in a stationary reference frame (α-β) as: Using the Clark transformation, the relation between abc and αβ is given by: where x can be replaced by variables v i , i L , and e.

Predictive Model
The discrete-time model of the load current dynamics continuous-time model (Equation (4)) for a sampling time T S represents the predictive model. It is used for the future predictions of the load current from each voltage vectors and the measured load currents at the present sampling instant k. The discrete-time model can be obtained by a simple approximation of the load current derivative di L /dt by using the forward Euler approximation, given as: After substituting Equation (9) into Equation (4), an expression of the predicted future load current at the next sampling interval k + 1 can be obtained for each of the seven different voltage vectors v i (k) generated by the inverter as: where i L p (k + 1) denotes the predicted future load current at instant k + 1, i L (k) is the measured load current at instant k, the inverter voltage v i (k) is the decision variable to be calculated by the controller, and e(k) is the measured back-EMF voltage at the instant k. These predicted future load currents are used for the calculation of the cost function in the FS-MPC algorithm.

Cost Function
An objective function is required for the selection of the optimum switching state corresponding to a given sampling interval. The cost function is used in the case of MPC to compute the optimized switching state by minimizing the error between the reference and the measured current. The step-by-step explanation of the cost function is as follows:

•
The value of reference current i L ref (k) is obtained from an outer control loop at the sampling instant k.

•
The load current i L (k) and the back-EMF voltage e(k) are measured at the sampling instant k.

•
The discrete-time model of the load (Equation (10)) is used to predict the future value of the load current i L p (k + 1) in the next sampling instant k + 1 for each of the possible switching states of the inverter. • Then, the cost function is evaluated for all the predicted load currents, which is a function of the reference current i ref (k) and the predicted load current i L p (k + 1).

•
The switching state which minimizes the cost function is selected and applied to the inverter in the next sampling interval.
The cost function can be expressed in the stationary reference frame (α-β) as: where i re f Lα and i re f Lβ are the real and imaginary parts of reference current, and i p Lα and i p Lβ are the real and imaginary parts of the predicted load current vector i L p (k + 1), respectively.

HIL Co-Simulation
HIL co-simulation provides an intermediate level of system verification between the software simulation and implementation of the controller on the actual experimental system. The flowchart of the HIL co-simulation using FPGA is shown in Figure 3. At the initial stage, the controller and VSI system are modelled in MATLAB/Simulink and the performance is verified using simulations. Furthermore, the controller modelling is developed using the XSG digital platform and the performance is analyzed considering the model of the control using Simulink. The digital modelling of the controller is validated at the later stage through the real-time HIL co-simulation.

Modelling of the FS-MPC in XSG
The implemented controller in the MATLAB/Simulink platform is required to be modelled for the digital implementation of the controller in the XSG environment. The implementation of the FS-MPC in XSG is performed using the Xilinx blockset available in MATLAB/Simulink. The XSG provides a virtual FPGA platform to perform the HIL co-simulation. The modelling of the controller is described in following two sections.

Computation of the Cost Function
The block diagram for the calculation of cost functions is shown in Figure 4. Initially, the predicted load current is modelled using Equation (10) considering a voltage vector for the three-phase VSI. Finally, the cost function is computed using Equation (11) for the respective predicted load currents. The modelling for the computation of the cost function in Figure 5 is developed in the XSG platform. The measured variables i L (k) and e(k) are used as inputs to compute predicted load currents i L p (k + 1) corresponding to each voltage vectors v i (k). Furthermore, the cost functions corresponding to different voltage vectors are calculated by feeding the predicted load currents and reference current i L ref (k).
The cost function corresponding to each output voltage vector (v 0 -v 7 ) is computed simultaneously through the modelling.

Selection of Optimum Switching Signals
The modelling for the selection of the optimum switching state is developed based upon the block diagram in Figure 6. The index number 0-7 is defined for each of the voltage vectors v 0 -v 7 , respectively. The computed cost functions are further utilized for the selection of the index number corresponding to the minimized cost function. The switching state for the minimized cost function is selected as per the index number according to a 3 × 8 matrix of possible switching states. The modelling for selection of the minimum cost function for the optimum switching state is implemented as in Figure 7, and the generated switching signals are applied to the VSI.

Co-simulation
In this paper, HIL co-simulation is considered for the validation of the controller by implementing it on the hardware system through the interaction with the software system as shown in Figure 8a. The co-simulation is performed using FPGA as an actual hardware by interacting with a computer as shown in Figure 8b. Firstly, the modelling of the controller is developed in the XSG, and further validation is performed using the co-simulation functionality of the XSG platform. The HIL co-simulation is performed by implementing the FS-MPC in the FPGA through its interaction with the VSI system in MATLAB/Simulink as represented in Figure 8b. The co-simulation prototype block is generated by selecting the appropriate FPGA evaluation board using the XSG token in MATLAB/Simulink. The co-simulation prototype block enables the MATLAB/Simulink system to interact with the FPGA. The signal ports are assigned in the co-simulation block corresponding to the input signal from Simulink to the XSG and output signal from the XSG to Simulink.
The co-simulation block of the FS-MPC contains the FPGA files that are programmed in the FPGA while performing a co-simulation, and the input-output signals are exchanged between the FPGA and MATLAB/Simulink. The co-simulation block is generated through the digital system modelling in the XSG as shown in Figure 9. Signal ports of the VSI system are connected through the signal ports assigned for the co-simulation block in MATLAB/Simulink. The validation of the controller system through co-simulation is performed using the Zedboard Zynq evaluation and development FPGA kit. The FPGA kit is physically connected to computer using a micro-USB cable that connects the joint test action group (JTAG) port available in the FPGA and a USB port available in the computer to perform HIL co-simulation.

Results and Discussion
The performance of the three-phase VSI system is validated through the implementation of a controller in MATLAB/Simulink as well as XSG environments and HIL co-simulation. The parameters considered for the VSI system with a motor-type load are depicted in Table 3. The system performance is analyzed considering intermediate results: minimum cost function-index value, sampling time, and tracking performance.

Intermediate Response
The intermediate responses of the selection of the minimum cost function and the index number corresponding to the optimum switching state are analyzed for the modelling and implementation of the FS-MPC. A sampling time of 50 µs was chosen for the selection of the minimum cost function for each sampling interval as depicted in Figure 10. The minimum cost function response results in the minimized current error. The minimized current error is required for improved performance of the system to feed quality power output. The selection of the index number for an optimum switching state in Figure 11 is represented for each sampling interval.  The intermediate responses for Simulink is different as compared to the XSG and HIL co-simulation platforms. The responses for the XSG and HIL co-simulation is quite similar due to digital-based platform. The small difference observed in the XSG and HIL co-simulation might be due to the prompt response during co-simulation as the controller is operating in real-time through the FPGA. The prompt response of the controller for co-simulation as compared to the XSG can be observed for the selection of the minimum cost function in Figure 10. Furthermore, the switching signals are generated corresponding to the index number selection in each sampling interval that will be applied to the VSI. The switching signals in Figure 12 are demonstrated for the leg "a" upper switch of the VSI, considering the controller implementation in all three platforms.

Sampling Time
The performance of the controller depends on the sampling time T S selected for the discretization of the continuous-time model. Different sampling time T S is considered for the discretization of the VSI system to analyze and validate the performance of the controller. The sampling time T S governs the maximum switching frequency that is half of the sampling frequency. Therefore, the increase in T S results in the decrease in the maximum switching frequency of the VSI system, and vice versa. The operation of the FS-MPC is considered for T S = 20, 50, and 100 µs to analyze the effect of T S . In addition, the effect of change in T S is compared for the implementation of the FS-MPC in MATLAB/Simulink, XSG, and HIL co-simulation. The load currents are demonstrated for T S = 50 µs in Figure 13, T S = 100 µs in Figure 14, and T S = 20 µs in Figure 15. The load current for the steady state condition is almost similar for the implementation using all three platforms. However, the transient performances are not similar for the MATLAB/Simulink and HIL co-simulation, as demonstrated in the enlarged view of the load currents. The controller performance is delayed in case of HIL co-simulation for all the sampling times considered for the demonstration. Furthermore, the similar controller response for XSG and HIL co-simulation during transient conditions verified that the delay is due to the response of the controller rather than delay introduced due to the interaction of the actual hardware and computer. The delay in response is higher for a high sampling time due to the operation of the controller at a low sampling frequency.

Tracking Performance
The tracking of the load current with respect to the reference is a significant characteristic to analyze the performance of a given controller. The tracking of the load current real component (i Lα ) and imaginary component (i Lβ ) with respect to the sinusoidal reference current is demonstrated in Figure 16 for the sampling time T S = 50 µs. The tracking performance is analyzed during transient conditions due to perturbation in the reference current, as in Figure 17, to demonstrate the dynamic response of the controller. The good tracking performance is obtained as the load current properly tracks the reference current at each moment during the normal operating conditions as well as during the transient condition. An extreme transient case is considered: change in magnitude and phase at the same instant with respect to normal operating conditions.
The tracking performance for all three platforms are similar under normal operating conditions as well as under dynamic conditions. However, the slight delay in response for the XSG and HIL co-simulation compared to the MATLAB/Simulink platform can be seen in the enlarged view as shown in Figure 16. However, there is no delay in response for XSG and HIL co-simulation, which indicates the advantage of co-simulation through the operation of the controller in a real-time environment.

Conclusions
This paper presents the FS-MPC modelled in XSG and tested through HIL co-simulation using an FPGA for controlled power conversion through a three-phase VSI system considered with a motor load condition. The design and development of efficient controllers are required for controlled power conversion through VSI to use power generated from renewable energy sources. The FS-MPC has gained attention in the field of power electronic and drives for controlled power conversion, possessing the discrete nature of control that readily suits implementation in a digital environment.
The FS-MPC is implemented in MATLAB/Simulink and further in an XSG platform that is used for digital system design. The controller performance is validated for a real-time environment through a HIL co-simulation considering the step-by-step analysis through intermediate outputs: the minimum cost function and selection of an index number. Also, the performance is validated considering the effect of the sampling time and tracking performance under dynamic conditions. The modelling of the FS-MPC in XSG is a viable choice due to the discrete nature of the controller. Furthermore, the real-time HIL co-simulation is a realistic approach for implementation by validating the controller performance before applying it to a real experimental system, to reduce the risk of component damage/whole system failure. In the future, the integrated platform of MATLAB/Simulink-XSG will be used to generate HDL codes for the implementation of FS-MPC in real-time experimental systems using an FPGA. The FS-MPC-controlled VSI system will further be employed for the islanded and grid-connected application of solar photovoltaic systems.