Theoretical and Experimental Investigation of the Voltage Ripple across Flying Capacitors in the Interleaved Buck Converter with Extended Duty Cycle

Abstract: The interleaved buck converter with an extended duty cycle is analyzed in terms of unexplored parasitic switching states that diminish the switch utilization and its safety due to high-magnitude charging and discharging currents. The analysis explains the origin of the states and their effects and demonstrates their correlation with the existing voltage ripple on flying capacitors. The article further demonstrates that the voltage ripple can no longer be arbitrarily chosen as parasitic states emerge whenever the ripple exceeds an identified critical value being equal to the twofold voltage drop on the diode. A simple design criterion for flying capacitance is proposed. For a limited set of battery-powered DC–DC converters, a solution permitting the use of smaller capacitance by adding an extra switch is proposed. The derived findings are verified using experimental and simulation results.


Introduction
DC-DC converters, capable to operate at a high voltage conversion ratio between the input V in and output voltages V out , are gaining noticeable consideration in different applications [1,2], ranging from point-of-load converters to converters in several hybrid vehicle configurations.In these applications, power switches are commonly poorly utilized.Switch utilization is, in general, defined as the ratio between the output power consumed on a load and the product of the maximum voltage and current on the switch, thus being proportional to the duty cycle [3,4].In the past, low switch utilization was successfully addressed in inductor-tapped solutions; with the only drawback of the increased blocking voltage [5][6][7][8].In recent years, the voltage rating of the switch is commonly reduced by applying multi-level DC-DC converters, such as the one with a flying capacitor [9][10][11][12][13][14].In this case, the switch utilization is increased at the price of increased control complexity.On the other hand, the switches with lower voltage ratings exhibit lower conduction and switching losses, consequently increasing the overall efficiency.
Traditionally, switch utilization can be enhanced by sharing the total power among converters operating in parallel.Such a converter is designated as a multi-phase converter [15][16][17][18][19][20].Additional benefits can be further gained by interleaving as the current ripple through the output smoothing capacitor is decreased.In order not to exceed the current rating of the individual switch, the complexity of control becomes problematic not only due to the increased number of current transducers but mostly as the current has to be evenly shared both in the steady state and during transients.
The advantages of both concepts, i.e. multi-level and multi-phase, have been successfully combined in the interleaved multi-phase Buck converter with an extended duty cycle proposed in [19,20].There, two different topologies are presented.Both feature almost the same benefits, differing in the number of switches per phase.In a topology with two metal oxide semiconductor field effect transistors (MOSFET) per output phase (analyzed in this paper-Figure 1), all MOSFETs (T 1 -T 4 ) are subjected to the same current (I load /n, where n denotes the number of phases) and voltage (V in /2) stress.Most importantly, the current sharing among phases takes place spontaneously.Accordingly, only the load current needs to be measured, thus make the analyzed topology an ideal example for high-current applications.
Regardless of the topology, flying capacitors are exposed to large current and thermal stress, which leads to a more rapid ageing of the component [21].Its consequences are reduced capacitance and increased equivalent series resistance (ESR).Accordingly, when selecting capacitors, a wider design margin is needed in order to mitigate the capacitor's degradation and to guarantee error-free operation.
Commonly, when analyzing DC-DC converters, bulky capacitors are implied, assuming the voltage ripple on the capacitor is small enough compared to its average voltage.This is certain for output smoothing capacitor, which has the direct impact on the output voltage quality and on the electromagnetic interference (EMI).On the other hand, in practice, a larger voltage ripple is usually allowed across flying capacitors in order to decrease the required volume in high-density designs.No serious impacts on the basic operation of the converter owed to a higher voltage ripple on flying capacitors have been reported [9][10][11][12][13][14].
This paper offers an in-depth analysis of interleaved buck topology.The paper also derives a condition referring to the minimum capacitance that separates error-free operation from the appearance of the parasitic switching states, and discuss the effects if the condition is not met.The origin of the parasitic switching states is analyzed in detail as not yet reported in references dealing with this topology [19,20].Furthermore, a simple solution that prevents the appearance of parasitic states and their effects is proposed and commented.

The Operating Principle of the Interleaved Buck Converter
Figure 1 depicts the original scheme of the two-phase interleaved buck consisting of four MOSFETs and freewheeling diodes D 11 and D 22 [19].Consistently with the original paper, only the continuous conduction mode (CCM) operation is assumed.The advantages of both concepts, i.e. multi-level and multi-phase, have been successfully combined in the interleaved multi-phase Buck converter with an extended duty cycle proposed in [19,20].There, two different topologies are presented.Both feature almost the same benefits, differing in the number of switches per phase.In a topology with two metal oxide semiconductor field effect transistors (MOSFET) per output phase (analyzed in this paper-Figure 1), all MOSFETs (T 1 -T 4 ) are subjected to the same current (I load n ⁄ , where n denotes the number of phases) and voltage (V in 2 ⁄ ) stress.Most importantly, the current sharing among phases takes place spontaneously.Accordingly, only the load current needs to be measured, thus make the analyzed topology an ideal example for high-current applications.
Regardless of the topology, flying capacitors are exposed to large current and thermal stress, which leads to a more rapid ageing of the component [21].Its consequences are reduced capacitance and increased equivalent series resistance (ESR).Accordingly, when selecting capacitors, a wider design margin is needed in order to mitigate the capacitor's degradation and to guarantee error-free operation.
Commonly, when analyzing DC-DC converters, bulky capacitors are implied, assuming the voltage ripple on the capacitor is small enough compared to its average voltage.This is certain for output smoothing capacitor, which has the direct impact on the output voltage quality and on the electromagnetic interference (EMI).On the other hand, in practice, a larger voltage ripple is usually allowed across flying capacitors in order to decrease the required volume in high-density designs.No serious impacts on the basic operation of the converter owed to a higher voltage ripple on flying capacitors have been reported [9][10][11][12][13][14].
This paper offers an in-depth analysis of interleaved buck topology.The paper also derives a condition referring to the minimum capacitance that separates error-free operation from the appearance of the parasitic switching states, and discuss the effects if the condition is not met.The origin of the parasitic switching states is analyzed in detail as not yet reported in references dealing with this topology [19,20].Furthermore, a simple solution that prevents the appearance of parasitic states and their effects is proposed and commented.

The Operating Principle of the Interleaved Buck Converter
Figure 1 depicts the original scheme of the two-phase interleaved buck consisting of four MOSFETs and freewheeling diodes D 11 and D 22 [19].Consistently with the original paper, only the continuous conduction mode (CCM) operation is assumed.Accordingly, the converter enters four active switching intervals (identified by the conduction of a particular switch) that take part in a predefined sequence-either clockwise (CW sequence: T 4 -T 3 -T 2 -T 1 ) or counter-clockwise (CCW sequence: T 1 -T 2 -T 3 -T 4 ).Between two Accordingly, the converter enters four active switching intervals (identified by the conduction of a particular switch) that take part in a predefined sequence-either clockwise (CW sequence: T 4 -T 3 -T 2 -T 1 ) or counter-clockwise (CCW sequence: T 1 -T 2 -T 3 -T 4 ).Between two consecutive active switching intervals, the freewheeling interval (FW) occurs.In that interval, inductors' currents flow through D 11 and D 22 .All active switching intervals have the same duty cycle (d sw ) which never exceeds 0.25.In the same paper, it is further demonstrated that, assuming the circuit symmetry, the average voltage across the flying capacitor (C 1 , C 2 ) equals V in /2, and the load current is equally shared among inductors.As a result, in steady-state operation, the output voltage is proportional to V in •d sw /2.To sum up, all results and conclusions provided in [19,20] apply only to highly idealized cases due to the assumed bulkiness of C 1 and C 2 .

Deriving the Voltage Ripple on Flying Capacitors
During the operation, C 1 and C 2 are charged and discharged interchangeably by i L1 and i L2 as seen in Figures 2 and 3.As a result, they are inherently subjected to short current pulses of high magnitude that equal I L1 and I L2 respectively.
Energies 2018, 11, x FOR PEER REVIEW 3 of 13 consecutive active switching intervals, the freewheeling interval (FW) occurs.In that interval, inductors' currents flow through D 11 and D 22 .All active switching intervals have the same duty cycle (d sw ) which never exceeds 0.25.In the same paper, it is further demonstrated that, assuming the circuit symmetry, the average voltage across the flying capacitor (C 1 , C 2 ) equals V in 2 ⁄ , and the load current is equally shared among inductors.As a result, in steady-state operation, the output voltage is proportional to V in •d sw 2 ⁄ .To sum up, all results and conclusions provided in [19,20] apply only to highly idealized cases due to the assumed bulkiness of C 1 and C 2 .

Deriving the Voltage Ripple on Flying Capacitors
During the operation, C 1 and C 2 are charged and discharged interchangeably by i L1 and i L2 as seen in Figures 2 and 3.As a result, they are inherently subjected to short current pulses of high magnitude that equal I L1 and I L2 respectively.
Simulation results showing voltages and currents that flow through flying capacitors (details regarding the simulation models built in LTspiceXVII can be found in Section 3).
Energies 2018, 11, x FOR PEER REVIEW 3 of 13 consecutive active switching intervals, the freewheeling interval (FW) occurs.In that interval, inductors' currents flow through D 11 and D 22 .All active switching intervals have the same duty cycle (d sw ) which never exceeds 0.25.In the same paper, it is further demonstrated that, assuming the circuit symmetry, the average voltage across the flying capacitor (C 1 , C 2 ) equals V in 2 ⁄ , and the load current is equally shared among inductors.As a result, in steady-state operation, the output voltage is proportional to V in •d sw 2 ⁄ .To sum up, all results and conclusions provided in [19,20] apply only to highly idealized cases due to the assumed bulkiness of C 1 and C 2 .

Deriving the Voltage Ripple on Flying Capacitors
During the operation, C 1 and C 2 are charged and discharged interchangeably by i L1 and i L2 as seen in Figures 2 and 3.As a result, they are inherently subjected to short current pulses of high magnitude that equal I L1 and I L2 respectively.In Interval I, the capacitor C 1 is charged by the inductor current i L2 .In Interval II, when T 2 is switched ON, C 1 is discharged by current i L1 .
Assuming a lossless capacitor v C1 remains unchanged during the FW interval, as well as in consecutive intervals when v C2 at first decays in Interval III (due to i L2 ) and then in Interval IV rises back (due to i L1 ).In the steady-state, the voltage increase and decrease on the individual flying capacitor are in equilibrium: Assuming symmetrical circuit the voltage ripples, expressed as a peak-peak value, are equal (∆v C1 = ∆v C2 = ∆v C ) on both flying capacitors.
In Interval II (Figure 3b), the diode D 22 is forward-biased.Therefore, the potential in node A is equal to the sum: By neglecting the voltage drop on MOSFET (T 2 ), the potential in node B is: Figure 2 demonstrates that at the end of Interval I, the capacitor voltages v C1 and v C2 tend to reach their maximum values (V in /2 + ∆v C /2) and remain unchanged until the start of Interval II.Consequently, at the start of Interval II, V B reaches its maximum as well: Providing that V B,I I max is lower than V in +v D_body , the body diode in MOSFET (T 4 ) remains reverse-biased.Thus, if an equal voltage drop across the body diode and the freewheeling diode is assumed, the voltage sum across flying capacitors (V in + ∆v C ) should be kept below V in +2v D .The latest can be rephrased into the condition: where 2v D is recognized as a critical value of the voltage ripple ∆v C .In a similar way, at the start of Interval IV (Figure 3d), the body diode in MOSFET (T 2 ) could conduct only if the sum of flying capacitor voltages drops below its minimum V in − ∆v C .In the meantime, node B is fastened to the positive supply, causing: whereas the potential in node A remains unchanged compared to Interval II: However, as voltages on both flying capacitors have already reached their minimum (V in − ∆v C /2), V A,IV drops to: By assuming equal voltage drops across the body diode and the freewheeling diode, the same condition already stated in Equation ( 5) determines whether the body diode in MOSFET (T 2 ) remains biased in reverse or it turns into conduction.

The Origin of the Parasitic Switching States
Referring to the derived Equations ( 2)-( 8), it is evident that the maximum voltage ripple permitted on flying capacitors cannot be chosen arbitrarily during the design process.If the ripple exceeds 2v D , the parasitic switching state emerges as the body diode of the inactive MOSFET is forward-biased.Figure 4a shows an existing current path (dashed red line) during Interval II and an extra path (solid blue line) that appears through the body diode in T 4 .

The Origin of the Parasitic Switching States
Referring to the derived Equations ( 2)-( 8), it is evident that the maximum voltage ripple permitted on flying capacitors cannot be chosen arbitrarily during the design process.If the ripple exceeds 2v D , the parasitic switching state emerges as the body diode of the inactive MOSFET is forward-biased.Figure 4a shows an existing current path (dashed red line) during Interval II and an extra path (solid blue line) that appears through the body diode in T 4 .The extra current path emerges at the beginning of Interval II and exists only for a limited time, being denoted as Interval II*. Figure 5 shows this phenomenon in detail.During this interval, a surplus charge, which has accumulated on flying capacitors, is abruptly discharged back to the voltage source.This overcharging does not jeopardize the validity of the derived Equations (2-8) as these define electric potentials in nodes A and B only in Interval II and Interval IV.In fact, at the end of Interval I, the flying capacitors could be charged to a higher voltage as shown in the zoomed part in Figure 5, depending on the parameters involved in Equation ( 1), thus forcing the voltage ripple over The extra current path emerges at the beginning of Interval II and exists only for a limited time, being denoted as Interval II*. Figure 5 shows this phenomenon in detail.During this interval, a surplus charge, which has accumulated on flying capacitors, is abruptly discharged back to the voltage source.

The Origin of the Parasitic Switching States
Referring to the derived Equations ( 2)-( 8), it is evident that the maximum voltage ripple permitted on flying capacitors cannot be chosen arbitrarily during the design process.If the ripple exceeds 2v D , the parasitic switching state emerges as the body diode of the inactive MOSFET is forward-biased.Figure 4a shows an existing current path (dashed red line) during Interval II and an extra path (solid blue line) that appears through the body diode in T 4 .This overcharging does not jeopardize the validity of the derived Equations (2-8) as these define electric potentials in nodes A and B only in Interval II and Interval IV.In fact, at the end of Interval I, the flying capacitors could be charged to a higher voltage as shown in the zoomed part in Figure 5, depending on the parameters involved in Equation ( 1), thus forcing the voltage ripple over This overcharging does not jeopardize the validity of the derived Equations (2-8) as these define electric potentials in nodes A and B only in Interval II and Interval IV.In fact, at the end of Interval I, the flying capacitors could be charged to a higher voltage as shown in the zoomed part in Figure 5, depending on the parameters involved in Equation ( 1), thus forcing the voltage ripple over the critical value.If this is the case, the capacitors discharge until their ripples drop below 2v D .If the ripples remain inside the boundaries, the error-free operation depicted in Figure 2 takes place.
The shape of the discharging current, which flows simultaneously through both flying capacitors, follows: where V stands for the voltage difference seen in the zoomed section in Figure 5.The shape is defined by R-L-C parameters found in the depicted path (Figure 4a, blue line) where small resistances (R) and inductances L p , both contributed by parasitic components of circuit and flying capacitors (C), have a dominant impact on the magnitude and period of the signal.Its period could be as short as the conduction interval of power switches, whereas its magnitude can easily reach or even surpass the inductor current.Figure 4b indicates a similar parasitic switching state which could occur when T 4 turns ON if in that instant the sum of voltages across C 1 and C 2 is too low to maintain the body diode of T 2 reverse-biased.In that case, the capacitors are abruptly charged from the power source through the forward-biased body diode of MOSFET T 2 .As D 22 is forward biased by the freewheeling current forced by L 2 , the surge current (blue line) can be considered to flow in opposite direction thus decreasing the current through D 22 .
It is apparent that such an operation is not desirable as conduction losses may increase considerably, but also since semiconductors and flying capacitors could be overstressed by the current.In addition, if the front side of the converter includes an overcurrent protection, its level should be high enough to prevent an unintentional tripping.Therefore, to prevent the occurrence of these states and their impacts, the capacitance should be set higher than the critical one: Equation ( 10) is derived from Equation (1) by taking into account that the load current is equally shared among inductors and the voltage ratio V out /V in is proportional to d sw /2.It is important to point out that the form of Equation ( 10) is not significantly different from equations that can be derived for an arbitrary with flying capacitors [9,11,13,14].The critical capacitance in this particular converter is inherently limited by topology itself, as the ripple must not exceed the twofold voltage drop on the diodes (2v D ).This finding is the essential contribution to the original papers [19,20] in order to preserve an error-free operation.

Simulation and Experimental Results
Simulations have been performed using LTspiceXVII.The simulation model did not include any additional inductances besides those already present in the models of transistors and diodes.
Experimental verifications have been carried out in order to prove the theoretical reasoning and simulation results already partially presented when introducing the parasitic switching states and their effects in the previous section.The experimental setup including a custom-made converter with a TMS320F2806 DSP (Texas Instruments, Dallas, TX, USA) is presented in Figure 6.Table 1 summarizes the main parameters of the experimental setup.The converter is deployed on a two-layer PCB.The topology is the same as in Figure 1 but the D 11 and D 22 were replaced with MOSFETs in order to increase the flexibility of converter thus enabling additional research.For measurements, these MOSFETs were permanently OFF to emulate the freewheeling diodes D 11 and D 22 .In order to reduce EMI to the lowest possible level, flying capacitors are placed in a close proximity of switching nodes with a high dv/dt, thus keeping the current loops that are subjected to pulses with a high di/dt short as well.In order to enable the current measurement through flying capacitors, the PCB was not equipped with multilayer ceramic capacitors (MLCC).Instead, they are placed on dedicated holders which are connected to the rest of the circuit by solid wires where a current probe (A6302 from Tektronix, Beaverton, OR, USA) can be clamped on.To simplify the tests, each MLCC holder was populated with three 15 μF/50 V capacitors.According to the known current that flows through parallel capacitors, their capacitance was estimated at 30 μF at an average capacitor voltage (15 V).For tests requiring a critical or higher capacitance, the difference was realized by fastening a temporary capacitor of an adequate capacitance.
The first test was carried out in order to verify the steady-state waveforms of the converter and its numerical model built in LTspiceXVII.Due to the additional inductance introduced by the aforesaid capacitor placement, tests have been performed at a reduced current capability (I load, max* = 20 A) in order to reduce overvoltage on MOSFETs.In accordance with Equation (10), the critical capacitance amounts to 44 μF. Figure 7a,b depict i C1 (blue) and i C2 (red) at different load currents and with a capacitance greater than C crit specified in Equation (10).The shape and magnitude of both currents closely match simulation traces seen in the top part of Figure 7c,d, but there is slight asymmetry of magnitudes between currents due to mismatch of inductance and capacitor values.The converter is deployed on a two-layer PCB.The topology is the same as in Figure 1 but the D 11 and D 22 were replaced with MOSFETs in order to increase the flexibility of converter thus enabling additional research.For measurements, these MOSFETs were permanently OFF to emulate the freewheeling diodes D 11 and D 22 .In order to reduce EMI to the lowest possible level, flying capacitors are placed in a close proximity of switching nodes with a high dv/dt, thus keeping the current loops that are subjected to pulses with a high di/dt short as well.In order to enable the current measurement through flying capacitors, the PCB was not equipped with multilayer ceramic capacitors (MLCC).Instead, they are placed on dedicated holders which are connected to the rest of the circuit by solid wires where a current probe (A6302 from Tektronix, Beaverton, OR, USA) can be clamped on.To simplify the tests, each MLCC holder was populated with three 15 µF/50 V capacitors.According to the known current that flows through parallel capacitors, their capacitance was estimated at 30 µF at an average capacitor voltage (15 V).For tests requiring a critical or higher capacitance, the difference was realized by fastening a temporary capacitor of an adequate capacitance.
The first test was carried out in order to verify the steady-state waveforms of the converter and its numerical model built in LTspiceXVII.Due to the additional inductance introduced by the aforesaid capacitor placement, tests have been performed at a reduced current capability (I load, max * = 20 A) in order to reduce overvoltage on MOSFETs.In accordance with Equation (10), the critical capacitance amounts to 44 µF. Figure 7a,b depict i C1 (blue) and i C2 (red) at different load currents and with a capacitance greater than C crit specified in Equation (10).The shape and magnitude of both currents closely match simulation traces seen in the top part of Figure 7c,d, but there is slight asymmetry of magnitudes between currents due to mismatch of inductance and capacitor values.Current spikes, which appear in experimental traces whenever an individual MOSFET turns ON, are caused by the reverse recovery charge Q rr of the freewheeling diodes.Owing to the increased inductance, the trailing edges of these spikes are additionally prolonged.In addition, a capacitive coupling due to the close proximity between switching nodes with a high dv/dt and the current probe rendered the shape of current measurements, too.When voltages-especially those referenced against one of the switching node-are measured with passive voltage probes, the quality of captured traces on oscilloscope (Tektronix-DPO 4034B) usually worsen substantially.As a result, voltages shown on oscilloscope window were not measured simultaneously with current traces.Instead, they were measured separately and then recalled from internal memories.
In addition, voltage ripples in the middle part of Figure 7c,d exhibit their dependency on the load current (traces at the bottom of the same figures) as identified in the analysis.As it can be noticed, the experimental voltage ripples (at the bottom part of the Figure 7a,b) match the simulated ones quite faithfully, both in the magnitude and the shape.The average value of the flying capacitor voltages differs from V in 2 ⁄ , being theoretically derived with neglected voltage drops on MOSFETs and freewheeling diodes.
The effectiveness of the proposed analytical developments given by Equations ( 2)-( 10) is further confirmed in Figure 8, where an experimental verification was carried out considering the violation of the critical value of flying capacitance.Compared to the simulation results in Figure 8a, Current spikes, which appear in experimental traces whenever an individual MOSFET turns ON, are caused by the reverse recovery charge Q rr of the freewheeling diodes.Owing to the increased inductance, the trailing edges of these spikes are additionally prolonged.In addition, a capacitive coupling due to the close proximity between switching nodes with a high dv/dt and the current probe rendered the shape of current measurements, too.When voltages-especially those referenced against one of the switching node-are measured with passive voltage probes, the quality of captured traces on oscilloscope (Tektronix-DPO 4034B) usually worsen substantially.As a result, voltages shown on oscilloscope window were not measured simultaneously with current traces.Instead, they were measured separately and then recalled from internal memories.
In addition, voltage ripples in the middle part of Figure 7c,d exhibit their dependency on the load current (traces at the bottom of the same figures) as identified in the analysis.As it can be noticed, the experimental voltage ripples (at the bottom part of the Figure 7a,b) match the simulated ones quite faithfully, both in the magnitude and the shape.The average value of the flying capacitor voltages differs from V in /2, being theoretically derived with neglected voltage drops on MOSFETs and freewheeling diodes.
The effectiveness of the proposed analytical developments given by Equations ( 2)-( 10) is further confirmed in Figure 8, where an experimental verification was carried out considering the violation of the critical value of flying capacitance.Compared to the simulation results in Figure 8a, it can be noticed that the experimental currents in Figure 8b exhibit a longer duration of parasitic intervals.Referring to Equation ( 9), this deviation can be explained as simulation did not include any additional parasitic inductances which were present in the circuit (PCB traces, transistor terminals, equivalent series inductance of capacitors, capacitor holder).
Energies 2018, 11, x FOR PEER REVIEW 9 of 13 it can be noticed that the experimental currents in Figure 8b exhibit a longer duration of parasitic intervals.Referring to Equation ( 9), this deviation can be explained as simulation did not include any additional parasitic inductances which were present in the circuit (PCB traces, transistor terminals, equivalent series inductance of capacitors, capacitor holder). (a)

Discussion
All in all, the benefit of knowing the critical capacitance can be of higher importance in the converter with n larger than 2, particularly if the converter works at higher operational temperatures.There, the selection and placement of flying capacitors in a confined volume are strengthened in order to satisfy thermal and EMI specifications.Commonly, MLCCs of type X8R, X7R or X5R are implemented [22,23].Nowadays, they can be produced with high-temperature grades (150 °C) and with a high rated capacitance (22 μF/100 V) in a relatively small package of size 2220.On the other hand, MLCC faces a considerable voltage dependency.As a result, its rated capacitance could be met only at a reduced voltage.For high volumetric parts, the decrease of C with voltage can be greater than 50% of its rated value [23].Furthermore, a current derating has to be taken into account in order to reduce the dissipating power inside of the flying capacitors.All this increases the chance that in space-confined designs the flying capacitance has to be chosen close to its critical value, thus increasing the probability to violate Equation (10).Taking into account the ageing effects of MLCC as well [24][25][26], the aforesaid becomes even more likely.Furthermore, the situation becomes even worse if diodes D 11 and D 22 are replaced with a synchronous MOSFET, in order to boost the efficiency even further.In this case, the peak-peak voltage ripple across C 1 and

Discussion
All in all, the benefit of knowing the critical capacitance can be of higher importance in the converter with n larger than 2, particularly if the converter works at higher operational temperatures.There, the selection and placement of flying capacitors in a confined volume are strengthened in order to satisfy thermal and EMI specifications.Commonly, MLCCs of type X8R, X7R or X5R are implemented [22,23].Nowadays, they can be produced with high-temperature grades (150 • C) and with a high rated capacitance (22 µF/100 V) in a relatively small package of size 2220.On the other hand, MLCC faces a considerable voltage dependency.As a result, its rated capacitance could be met only at a reduced voltage.For high volumetric parts, the decrease of C with voltage can be greater than 50% of its rated value [23].Furthermore, a current derating has to be taken into account in order to reduce the dissipating power inside of the flying capacitors.All this increases the chance that in space-confined designs the flying capacitance has to be chosen close to its critical value, thus increasing the probability to violate Equation (10).Taking into account the ageing effects of MLCC as well [24][25][26], the aforesaid becomes even more likely.Furthermore, the situation becomes even worse if diodes D 11 and D 22 are replaced with a synchronous MOSFET, in order to boost the efficiency even further.In this case, the peak-peak voltage ripple across C 1 and C 2 falls under the voltage drop of a single body diode, basically halving the voltage ripple given in Equation (5).
As an additional remark, it was found out that, if the sequence changes from CCW to CW, parasitic switching states occur at the beginning of Interval I and Interval III.Since the body diodes of T 1 and T 3 are biased in the forward direction, the flying capacitors are again exposed to charging and discharging currents.All together, tests show that despite high expectations, the applicability of the converter could be significantly limited due to Equation (10).
Nevertheless, simulation results additionally exhibit that in the case of battery-powered converters-equipped with a MOSFET for battery reversal protection-the parasitic switching states vanish completely.Figure 9a As an additional remark, it was found out that, if the sequence changes from CCW to CW, parasitic switching states occur at the beginning of Interval I and Interval III.Since the body diodes of T 1 and T 3 are biased in the forward direction, the flying capacitors are again exposed to charging and discharging currents.All together, tests show that despite high expectations, the applicability of the converter could be significantly limited due to Equation (10).
Nevertheless, simulation results additionally exhibit that in the case of battery-powered converters-equipped with a MOSFET for battery reversal protection-the parasitic switching states vanish completely.Figure 9a The extra MOSFETs are switched simultaneously with T 1 and T 4 .As a result, no discharging current could flow back to the voltage supply irrespective of the CW or CCW sequence.In this case, the flying capacitor is not required to fulfil Equation ( 5).Thus, a larger voltage ripple may be accepted.In fact, traces on the left and right side in Figure 9 correspond to a flying capacitance of just 5 μF.Traces i C1 and i C2 are similar to those in Figure 7d obtained with a much larger capacitance (60 μF).Although the voltage ripples in Figures 9a,b are more than five times larger than the ones in Figure 7d, the load current is ideally shared among both inductors.In Figure 10, current sharing is proved even in the case when the resistance of one inductor has been intentionally increased to fivefold.
As it can be noticed in Figures 9 and 10, not only the ripple voltages increase, the average voltage across flying capacitors tends to increase as well.In this particular case, the converter remains functional at the price of an uneven voltage stress of the individual MOSFET (T 1 -T 4 ).Furthermore, as extra MOSFETs are switched simultaneously with T 1 and T 4 and at the zero-current condition, the total losses of the switches remain more or less unaffected.The control itself remains simple and straightforward.The additional MOSFETs are placed at the bottom side of PCB in order to be efficiently cooled and to keep the parasitic inductance as low as possible.The extra MOSFETs are switched simultaneously with T 1 and T 4 .As a result, no discharging current could flow back to the voltage supply irrespective of the CW or CCW sequence.In this case, the flying capacitor is not required to fulfil Equation ( 5).Thus, a larger voltage ripple may be accepted.In fact, traces on the left and right side in Figure 9 correspond to a flying capacitance of just 5 µF.Traces i C1 and i C2 are similar to those in Figure 7d obtained with a much larger capacitance (60 µF).Although the voltage ripples in Figure 9a,b are more than five times larger than the ones in Figure 7d, the load current is ideally shared among both inductors.In Figure 10, current sharing is proved even in the case when the resistance of one inductor has been intentionally increased to fivefold.
As it can be noticed in Figures 9 and 10, not only the ripple voltages increase, the average voltage across flying capacitors tends to increase as well.In this particular case, the converter remains functional at the price of an uneven voltage stress of the individual MOSFET (T 1 -T 4 ).Furthermore, as extra MOSFETs are switched simultaneously with T 1 and T 4 and at the zero-current condition, the total losses of the switches remain more or less unaffected.The control itself remains simple and straightforward.The additional MOSFETs are placed at the bottom side of PCB in order to be efficiently cooled and to keep the parasitic inductance as low as possible.

Conclusions
The voltage ripple in the interleaved buck converter with an extended duty cycle has been analyzed in this paper, as the converter has been recognized as an ideal candidate for high-current DC-DC applications from many points of view.Specifically, in contrast to other converters being referenced, it provides an equal current and voltage stress on all MOSFETs.And most importantly, it requires less current transducers as the current sharing in output inductors takes place automatically.
The analysis presented in this paper focuses on unexplored switching states which occur under specific conditions in the two-phase interleaved converter.As their occurrence has a significant negative impact on the converter operation, a critical capacitance was derived in order to avoid them.This been verified with a simulation model and confirmed by the measurements performed on the prototype converter.Furthermore, a simple mitigation solution based on the additional switch per converter's phase is proposed and verified.The solution is justified for battery-powered converters enabling to install a smaller flying capacitance as required by Equation (10).

Conclusions
The voltage ripple in the interleaved buck converter with an extended duty cycle has been analyzed in this paper, as the converter has been recognized as an ideal candidate for high-current DC-DC applications from many points of view.Specifically, in contrast to other converters being referenced, it provides an equal current and voltage stress on all MOSFETs.And most importantly, it requires less current transducers as the current sharing in output inductors takes place automatically.
The analysis presented in this paper focuses on unexplored switching states which occur under specific conditions in the two-phase interleaved converter.As their occurrence has a significant negative impact on the converter operation, a critical capacitance was derived in order to avoid them.This has been verified with a simulation model and confirmed by the measurements performed on the prototype converter.Furthermore, a simple mitigation solution based on the additional switch per converter's phase is proposed and verified.The solution is justified for battery-powered converters enabling to install a smaller flying capacitance as required by Equation (10).

Figure 1 .
Figure 1.The interleaved two-phase buck converter with an extended duty cycle.

Figure 1 .
Figure 1.The interleaved two-phase buck converter with an extended duty cycle.

Figure 2 .
Figure 2. Simulation results showing voltages and currents that flow through flying capacitors (details regarding the simulation models built in LTspiceXVII can be found in Section 3).

Figure 2 .
Figure 2. Simulation results showing voltages and currents that flow through flying capacitors (details regarding the simulation models built in LTspiceXVII can be found in Section 3).

Figure 3 .
Figure 3. Equivalent circuits with indicated current paths (in red) when ∆v C (see text) is below a critical value in: (a) Interval I; (b) Interval II; (c) Interval III; (d) Interval IV.

Figure 4 .
Figure 4. Equivalent circuits showing extra current paths (in blue) that occur when ∆v C exceeds the critical value: (a) in Interval II*; (b) in Interval IV*.

Figure 5 .
Figure 5. Simulation results showing flying capacitor currents and voltages with zoomed voltage waveforms in parasitic Interval II*.

Figure 4 .
Figure 4. Equivalent circuits showing extra current paths (in blue) that occur when ∆v C exceeds the critical value: (a) in Interval II*; (b) in Interval IV*.

Figure 4 .
Figure 4. Equivalent circuits showing extra current paths (in blue) that occur when ∆v C exceeds the critical value: (a) in Interval II*; (b) in Interval IV*.
Figure 5  shows this phenomenon in detail.During this interval, a surplus charge, which has accumulated on flying capacitors, is abruptly discharged back to the voltage source.

Figure 5 .
Figure 5. Simulation results showing flying capacitor currents and voltages with zoomed voltage waveforms in parasitic Interval II*.

Figure 5 .
Figure 5. Simulation results showing flying capacitor currents and voltages with zoomed voltage waveforms in parasitic Interval II*.

Figure 6 .
Figure 6.Pictures of the experimental setup: (a) an unpopulated printed circuit board (PCB) with a marked (yellow) section consisting of six MOSFETs and flying capacitors; (b) converter at the test bench.

Figure 6 .
Figure 6.Pictures of the experimental setup: (a) an unpopulated printed circuit board (PCB) with a marked (yellow) section consisting of six MOSFETs and flying capacitors; (b) converter at the test bench.

Figure 7 .
Figure 7. Experimental and simulation results obtained at C 1 = C 2 = 60 µF, C crit = 44 µF @ I load,max * = 20 A .Flying capacitors' currents (blue: i C1 ; red: i C2 ) and voltages (AC components only) on flying capacitors (top black: v C1 ; bottom black: v C2 ), both measured at an average inductor current: (a) 5 A; (b) 10 A. Simulated results at an average inductor current: (c) 5 A and (d) 10 A: the upper part, flying capacitors' currents: the middle part, voltages on flying capacitors: the lower part, inductors' currents.

Figure 8 .
Figure 8. Simulation and experimental results obtained at an average inductor current 10 A and at C 1 = C 2 = 35 μF: (a) simulated results: the upper part, flying capacitors' currents: the middle part, voltages on the flying capacitors: the lower part, inductors' currents; (b) measured results: flying capacitors' currents (blue: i C1 ; red: i C2 ); (c) voltages on the flying capacitors (blue: v C1 ; black: v C2 ).

Figure 8 .
Figure 8. Simulation and experimental results obtained at an average inductor current 10 A and at C 1 = C 2 = 35 µF: (a) simulated results: the upper part, flying capacitors' currents: the middle part, voltages on the flying capacitors: the lower part, inductors' currents; (b) measured results: flying capacitors' currents (blue: i C1 ; red: i C2 ); (c) voltages on the flying capacitors (blue: v C1 ; black: v C2 ).

13 C 2
,b show results obtained when extra MOSFETs were added in series with the top positioned MOSFETs T 1 and T 4 , forming a back-to-back switch.Energies 2018, 11, x FOR PEER REVIEW 10 of falls under the voltage drop of a single body diode, basically halving the voltage ripple given in Equation (5).

Figure 9 .
Figure 9.Comparison of results obtained at an average inductor current 10 A, with inserted extra switches and with C 1 = C 2 = 5 μF: (a) simulation results: the upper part, flying capacitors' currents: the middle part, voltages on flying capacitors: the lower part, inductors' currents: (b) measured results: the upper part, flying capacitors' currents (blue: i C1 ; red: i C2 ): the lower part, voltages on flying capacitors (bottom black: v C1 ; top black: v C2 ).

Figure 9 .
Figure 9.Comparison of results obtained at an average inductor current 10 A, with inserted extra switches and with C 1 = C 2 = 5 µF: (a) simulation results: the upper part, flying capacitors' currents: the middle part, voltages on flying capacitors: the lower part, inductors' currents: (b) measured results: the upper part, flying capacitors' currents (blue: i C1 ; red: i C2 ): the lower part, voltages on flying capacitors (bottom black: v C1 ; top black: v C2 ).

Figure 10 .
Figure 10.Simulation results obtained at an average inductor current 10 A, with inserted extra switches, with C 1 = C 2 = 5 μF and with unsymmetrical inductors' resistances R L2 = 5R L1 : the upper part, flying capacitors' currents: the middle part, voltages on flying capacitors: the lower part, inductors' currents.

Figure 10 .
Figure 10.Simulation results obtained at an average inductor current 10 A, with inserted extra switches, with C 1 = C 2 = 5 µF and with unsymmetrical inductors' resistances R L2 = 5R L1 : the upper part, flying capacitors' currents: the middle part, voltages on flying capacitors: the lower part, inductors' currents.

Table 1 .
Parameters of the prototype converter and its simulation model.

Table 1 .
Parameters of the prototype converter and its simulation model.