Line-to-Line Fault Analysis and Location in a VSC-Based Low-Voltage DC Distribution Network

A DC cable short-circuit fault is the most severe fault type that occurs in DC distribution networks, having a negative impact on transmission equipment and the stability of system operation. When a short-circuit fault occurs in a DC distribution network based on a voltage source converter (VSC), an in-depth analysis and characterization of the fault is of great significance to establish relay protection, devise fault current limiters and realize fault location. However, research on short-circuit faults in VSC-based low-voltage DC (LVDC) systems, which are greatly different from high-voltage DC (HVDC) systems, is currently stagnant. The existing research in this area is not conclusive, with further study required to explain findings in HVDC systems that do not fit with simulated results or lack thorough theoretical analyses. In this paper, faults are divided into transientand steady-state faults, and detailed formulas are provided. A more thorough and practical theoretical analysis with fewer errors can be used to develop protection schemes and short-circuit fault locations based on transientand steady-state analytic formulas. Compared to the classical methods, the fault analyses in this paper provide more accurate computed results of fault current. Thus, the fault location method can rapidly evaluate the distance between the fault and converter. The analyses of error increase and an improved handshaking method coordinating with the proposed location method are presented.


Introduction
In recent years, distributed generation has been promoted on a large scale, primarily for DC current systems.For this reason, hybrid AC/DC power systems have developed considerably.Voltage source converters (VSCs) attracted widespread attention because of their excellent control and operation characteristics in low-voltage DC distribution networks [1,2].Hence, technology to protect VSC-based DC distribution networks has become a heavily researched topic.However, the relevant research is limited, especially in the area of fault analysis and location.Some papers have been published in the last two years, with the relevant results summarized below.
For DC relay protection, Baran et al. [3] proposed a protection method based on early overcurrent.Yang et al. [4] considered that freewheel diodes were very easy to damage because of the severe overcurrent resulting from a capacitance discharge.Next, Baran et al. [3] proposed replacing the diodes with emitter turn-off devices (ETOs) to provide diodes with the capacity to block the current.Moreover, Baran et al. [3] adopted an ETO-based capacitance DC circuit breaker to cut off the capacitance branches and block the discharge current.However, this method increased the power loss to some extent.Deng et al. [5] developed an expression establishing the relationship between the peak value of the discharge current and the current-limiting inductance with the result that a simple inductance was effectively used to protect the diodes.Several papers have investigated the superconducting fault current limiter [6][7][8][9].location method adopting both transient and steady fault components was proposed based on the theoretical analyses.The computed results of fault current base on theoretical formulas in [4] and this paper are compared to verify the improvement in the computed accuracy.In addition, the reasons for the increase in errors in high fault resistance short-circuit faults is explained in brief.Finally, an improved location method is proposed by coordinating with the classical handshaking method, by which the performance of the handshaking method is enhanced.This paper is organized as follows: Section 2 presents the comparison of fault processes, detailed fault analyses, and a theoretical solution for transient and steady-state short-circuit faults is developed.Specific parameters and simulations in PSCAD/EMTDC are provided in Section 3. The fault location method, data on the location results, error analysis and coordination with other methods are presented in Section 4.

Fault Stages Comparison
When a short-circuit fault occurs, all DC-linked capacitances in the system will discharge to the fault location.This discharge leads the system voltage to collapse and the fault current to surge.As the classical theory proposed in [4], a whole fault progresses in three stages: (i) Capacitor discharges stage (Natural Response); (ii) Diode freewheel stage (Natural Response under the circumstance of = 0); and (iii) Grid-side current feeding stage (Forced Response).The classical equivalent circuits and electrical waveforms of different stages are shown as Figures 1 and 2a, respectively.The fact that stage 2 is the most challenging for freewheel diodes is generally accepted.However, stage 2 merely arise under the specified condition.Classically, the DC voltage will oscillate under the condition  However, a fault progresses differently in the LVDC distribution system, and the main differences are reflected in stage 1.Note that the derivatives of grid-side current are as follows: where ∆ is the difference in DC voltage and AC line voltage _ .In the HVDC transmission system, is much higher _ .This means that . . is high enough and that time is sufficient for the freewheel diodes to be blocked swiftly before gets lower than _ in stage 1.Just the natural response arises in a 2nd-order circuit in this stage (Figure 2a).In the LVDC distribution system, is not so high.This means that . .and ∆ are low; therefore, time is insufficient for the freewheel diodes to be blocked before gets lower than _ in stage 1.Once inequality < _ is established, freewheel diodes will not be blocked.Both the natural and forced responses arise in a However, a fault progresses differently in the LVDC distribution system, and the main differences are reflected in stage 1.Note that the derivatives of grid-side current are as follows: where ∆u is the difference in DC voltage U dc and AC line voltage u l_l .In the HVDC transmission system, U dc is much higher u l_l .This means that i g a.b.c is high enough and that time is sufficient for the freewheel diodes to be blocked swiftly before U dc gets lower than u l_l in stage 1.Just the natural response arises in a 2nd-order circuit in this stage (Figure 2a).In the LVDC distribution system, U dc is not so high.This means that i g a.b.c and ∆u are low; therefore, time is insufficient for the freewheel diodes to be blocked before U dc gets lower than u l_l in stage 1.Once inequality U dc < u l_l is established, freewheel diodes will not be blocked.Both the natural and forced responses arise in a 3rd-order circuit in this stage (Figure 2b).Thus, considerable errors arise in fault current computation and fault location if analyzed results in [4] continue to be adopted.Moreover, the criterion for DC voltage oscillation and estimated time when voltage reaches zero in HVDC system is unsuitable for LVDC system as the whole forced response feeding from AC-side is omitted.Whether DC voltage oscillates and when it drops to zero are depend on the actual expression of transient-state fault current.Fault analysis in a 3rd-order circuit must be proposed.In this paper, the fault process is divided into two stages: the transient-and the steady-state stages.According to the simulated results, the transient duration is generally approximately 2 ms, and the surge current is more than ten times the normal current.The steady-state develops as the DC-side power steadies.Until all breakers trip, this stage lasts approximately 100 ms [21].The fault current is a steady DC current with 6 waves, where the amplitude is influenced by the AC-side resistance, inductance and DC-side resistance.The amplitude of the steady fault current is much lower than that of the surge current, but it has a long duration.Therefore, the freewheel diodes will be damaged without appropriate current-limiting measures.
Energies 2018, 11, x FOR PEER REVIEW 4 of 15 3rd-order circuit in this stage (Figure 2b).Thus, considerable errors arise in fault current computation and fault location if analyzed results in [4] continue to be adopted.Moreover, the criterion for DC voltage oscillation and estimated time when voltage reaches zero in HVDC system is unsuitable for LVDC system as the whole forced response feeding from AC-side is omitted.Whether DC voltage oscillates and when it drops to zero are depend on the actual expression of transient-state fault current.Fault analysis in a 3rd-order circuit must be proposed.In this paper, the fault process is divided into two stages: the transient-and the steady-state stages.According to the simulated results, the transient duration is generally approximately 2 ms, and the surge current is more than ten times the normal current.The steady-state develops as the DC-side power steadies.Until all breakers trip, this stage lasts approximately 100 ms [21].The fault current is a steady DC current with 6 waves, where the amplitude is influenced by the AC-side resistance, inductance and DC-side resistance.The amplitude of the steady fault current is much lower than that of the surge current, but it has a long duration.Therefore, the freewheel diodes will be damaged without appropriate current-limiting measures.Thus, the peak value of the surge current and the amplitude of the steady current are the most significant parameters in fault analyses.

Fault Stages Comparison
DC-linked capacitance and inductance have no influence on the amplitude of the steady fault current.Therefore, a simplified circuit model is adopted as depicted in Figure 3a.The actual waveforms of the model in Figure 3a are presented as Figure 4. R 1 , L and R 2 are the total AC resistance, AC inductance and DC resistance, respectively.
During the steady-state process, all freewheel diodes conduct for half of a primitive period, which is different from the situation observed in a three-phase rectification circuit (freewheel diodes conduct for one third of a primitive period).This finding is attributable to the freewheel effect of the AC-side inductance when the AC voltage U abc is lower than the DC voltage U dc .However, when the current of the AC-side inductance decreases to 0 (point A in Figure 4), the freewheel diodes prevent the current from decreasing further.Therefore, the rate of change in the current of the AC-side inductance di 1 /dt abruptly changes to 0, which results in U abl = U abs < U dc , with the result that diode 1 is blocking and diode 4 is conducting.Note that each diode conducts for less than half of a primitive period when R 2 /wL > 3 √ 3.
Energies 2018, 11, x FOR PEER REVIEW 5 of 15 Thus, the peak value of the surge current and the amplitude of the steady current are the most significant parameters in fault analyses.

Fault Stages Comparison
DC-linked capacitance and inductance have no influence on the amplitude of the steady fault current.Therefore, a simplified circuit model is adopted as depicted in Figure 3a.The actual waveforms of the model in Figure 3a are presented as Figure 4. , and are the total AC resistance, AC inductance and DC resistance, respectively.
During the steady-state process, all freewheel diodes conduct for half of a primitive period, which is different from the situation observed in a three-phase rectification circuit (freewheel diodes conduct for one third of a primitive period).This finding is attributable to the freewheel effect of the AC-side inductance when the AC voltage is lower than the DC voltage .However, when the current of the AC-side inductance decreases to 0 (point A in Figure 4), the freewheel diodes prevent the current from decreasing further.Therefore, the rate of change in the current of the ACside inductance d d ⁄ abruptly changes to 0, which results in = < , with the result that diode 1 is blocking and diode 4 is conducting.Note that each diode conducts for less than half of a primitive period when ⁄ > 3√3.Thus, the peak value of the surge current and the amplitude of the steady current are the most significant parameters in fault analyses.

Fault Stages Comparison
DC-linked capacitance and inductance have no influence on the amplitude of the steady fault current.Therefore, a simplified circuit model is adopted as depicted in Figure 3a.The actual waveforms of the model in Figure 3a are presented as Figure 4. , and are the total AC resistance, AC inductance and DC resistance, respectively.
During the steady-state process, all freewheel diodes conduct for half of a primitive period, which is different from the situation observed in a three-phase rectification circuit (freewheel diodes conduct for one third of a primitive period).This finding is attributable to the freewheel effect of the AC-side inductance when the AC voltage is lower than the DC voltage .However, when the current of the AC-side inductance decreases to 0 (point A in Figure 4), the freewheel diodes prevent the current from decreasing further.Therefore, the rate of change in the current of the ACside inductance d d ⁄ abruptly changes to 0, which results in = < , with the result that diode 1 is blocking and diode 4 is conducting.Note that each diode conducts for less than half of a primitive period when ⁄ > 3√3.A primitive period can be divided into 6 equivalent periods based on the conducting status of the freewheel diodes, where each period corresponds to three different conducting freewheel diodes.Because all periods are the same, any one period can be chosen for analysis.In this paper, period 3 , in which diodes 1, 2 and 6 are conducting, is analyzed in detail.The current path and direction are shown in Figure 3b.Assume that the starting time of period 3 is 0 and the coordinate system is established as shown in Figure 4.
The differential equations of the circuit in Figure 3b are listed as follows: Because of the equivalence relations-u abs + u acs = 3u a , i a + i b + i c = 0 and di a /dt + di b /dt + di c /dt = 0-we obtain a 1-order differential equation after plugging the above relationships into Equations ( 2) + (3): where u a = U an cos(ωt + ϕ 0 ).The solution of the above equation is where Note that C = 0 and ϕ 0 − ϕ = −π/6 in the steady-state process.Thus, the amplitude of the steady-state voltage can be estimated as In a similar way, the amplitude of the steady-state current can be estimated as

Transient-State Fault
The transient-state fault is more difficult to analyze than the steady-state fault.Based on the boost effect of the VSC, the voltage at the DC side is always higher than that of the AC side.Especially in the HVDC transmission system, the voltage of the DC side is much higher (like AC/DC is 0.392 kV/1.0 kV in [4]).Thus, all freewheel diodes will be blocked in stage 1 and each side will be isolated.Therefore, it is simple and reasonable to analyze this system in the 2nd-order circuit model.However, in the LVDC distribution system, the voltage of the DC side is not sufficiently high.As the analysis in Section 2.1, the fault should be analyzed using the 3rd-order circuit model.
In this paper, the transient-state fault process is divided into the natural response process and the forced response process.Compared to the transient fault current, the normal current is very small and Energies 2018, 11, 536 7 of 16 can be omitted.To simplify the analysis, the DC-side circuit is regarded as open.Thus, the transient fault corresponding circuits are shown in Figure 5.
Figure 5a is the circuit representing the natural response process.R 1 and L 1 are the equivalent parameters of the AC-side components.Two of the three-phase branches are always in parallel connection, connected with the remaining branch in series (circuit structure in Figure 4a).Thus, considerR 1 and L 1 to be equal to 1.5R ac and 1.5L ac , respectively.R 2 and L 2 are the total parameters of the DC-side components.C is the parameter of DC-linked capacitance.The DC-linked capacitance discharges to each branch at the voltage of the operating value, U c (0). Figure 5b depicts the circuit representing the forced response process.Considering that the DC source is connected to the circuit at the moment of fault occurrence, the magnitude of the source can be equal to the step signal, the amplitude of which is derived from the output voltage of three-phase full-wave bridge circuit 2.34U p−p .
Energies 2018, 11, x FOR PEER REVIEW 7 of 15 Figure 5a is the circuit representing the natural response process.′ and ′ are the equivalent parameters of the AC-side components.Two of the three-phase branches are always in parallel connection, connected with the remaining branch in series (circuit structure in Figure 4a).Thus, consider ′ and ′ to be equal to 1.5 and 1.5 , respectively.and are the total parameters of the DC-side components.
is the parameter of DC-linked capacitance.The DC-linked capacitance discharges to each branch at the voltage of the operating value, (0). Figure 5b depicts the circuit representing the forced response process.Considering that the DC source is connected to the circuit at the moment of fault occurrence, the magnitude of the source can be equal to the step signal, the amplitude of which is derived from the output voltage of three-phase full-wave bridge circuit 2.34 .(1) Forced response of the transient-state fault: The differential equations describing the circuit in Figure 5a are According to Equations ( 9)-( 11), the state equations are Applying Formula | − | = 0, the characteristic equation can be obtained as follows: where Thus, applying the radical formula for a cubic equation, a real root = − and dual conjugate complex roots , = − ± • can be obtained as follows: (1) Forced response of the transient-state fault: The differential equations describing the circuit in Figure 5a are According to Equations ( 9)-( 11), the state equations are Applying Formula |sI − A| = 0, the characteristic equation can be obtained as follows: where Thus, applying the radical formula for a cubic equation, a real root s 1 = −α 1 and dual conjugate complex roots s 2,3 = −α 2 ± i•ω 2 can be obtained as follows: Hence, the analytic expression of the forced response surge current in Figure 4a is Under the initial conditions of and the final analytical expression of the forced response surge current is (2) Natural response of the transient-state fault: The DC-linked capacitance discharges to two resistance-inductance (R-L) branches in the natural response circuit.An equivalent branch is adopted to replace the two RL branches as shown in Figure 6.Hence, the RLC circuit shown in Figure 6 simplifies the analysis.
Energies 2018, 11, x FOR PEER REVIEW 8 of 15 Hence, the analytic expression of the forced response surge current in Figure 4a is Under the initial conditions of = + = 0, (0) = 0 and (0) ⁄ = 0. Note that (∞) = ( + ) ⁄ .Thus, the constant terms = ( + ) ⁄ , = ( + ) ⁄ , = 0, and the final analytical expression of the forced response surge current is (2) Natural response of the transient-state fault: The DC-linked capacitance discharges to two resistance-inductance (R-L) branches in the natural response circuit.An equivalent branch is adopted to replace the two RL branches as shown in Figure 6.Hence, the RLC circuit shown in Figure 6 simplifies the analysis.Assuming that Z 1 = R 1 + jω 2 L 1 and Z 2 = R 2 + jω 2 L 2 , the following equations can be obtained: where Energies 2018, 11, 536 Hence, the inherent frequency, attenuation coefficient and natural oscillation frequency of the above RLC circuit are ω 0 = 1/L eq C, α 0 = R eq /2L eq and ω 1 = ω 2 0 − α 2 0 , respectively.Thus, the analytical expression of the natural response surge current in the capacitance branch is The current content is inversely proportional to the impedance of each RL branch.Thus, the analytical expression of the natural response surge current in the DC branch is Note that the above analytical results are reasonable under the circumstance of and error increases considerably if Equation ( 23) is unsatisfied.
(3) Computation of the complete response the surge current: The analysis presented above shows that the complete response of the short-circuit fault surge current equals the sum of the forced response surge current and the natural response surge current in an equivalent linear circuit Theoretically, applying Equation ( 24), the peak value of the surge current can be calculated.Because the derivative of the current equals 0 at the time of the peak, the peak time can be obtained by Thus, the peak value of the current can be obtained as I 2 t p .

Case Studies
Simulations were completed in PSCAD/EMTDC 4.5 (Manitoba HVDC Research Centre, Manitoba, Canada).The parameters of the low-voltage distribution network are shown in Table 1.The RMS of the AC side line voltage U l−l = 380 V and phase voltage U p−p = 220 V. Therefore, the DC voltage source in the equivalent circuit U dc = 513 V.The cables adopt π-model parameters, and grounding capacitances are omitted.Figure 7 shows the comparison between the theoretical waveform1 obtained by Equation ( 24), theoretical waveform2 obtained by formulas in [4] and the simulated waveform of the surge current, Energies 2018, 11, 536 10 of 16 with a metal short-circuit fault occurring on 2 km of the whole cable.As the figure shows, nearly no errors are observed between the theoretical waveform1 and simulated waveform when the fault occurs with no resistance.However, considerable errors appear between the theoretical waveform2 and simulated waveform.The theoretical value is much lower than the simulated value, as the forced response from AC-side is omitted.
Table 2 shows the theoretical value, simulated value and the error when a metal short-circuit fault occurs over a different distance.Moreover, the theoretical value of the surge current includes a theoretical value obtained by Equation ( 24) (theoretical transient-state peak current1) and a theoretical value obtained by formulas in [4] (theoretical transient-state peak current2).As Table 2 shows, in the metal short-circuit fault case, current1 has little error, which is slightly higher than the simulated results.The simulated results demonstrate that the error is approximately 2%, and not more than 4%.Meanwhile, current2 is much lower than simulated results, and the error increases up to 15%.Note that the error increases with increasing fault distance.The error in the steady-state fault current decreases with increasing fault distance.The error is more than 5% within a fault distance of 3 km and less than 5% at a fault distance of 4 km or more.Moreover, the error of the steady-state fault current stabilized approximately 5%.
Energies 2018, 11, x FOR PEER REVIEW 10 of 15 metal short-circuit fault case, current1 has little error, which is slightly higher than the simulated results.The simulated results demonstrate that the error is approximately 2%, and not more than 4%.Meanwhile, current2 is much lower than simulated results, and the error increases up to 15%.Note that the error increases with increasing fault distance.The error in the steady-state fault current decreases with increasing fault distance.The error is more than 5% within a fault distance of 3 km and less than 5% at a fault distance of 4 km or more.Moreover, the error of the steady-state fault current stabilized approximately 5%.
Referring to the simulation result and Equation ( 8), the value of the resistance on the DC side can be obtained.Due to the 5% computational error, 1.05-fold of the steady-state fault current should be plugged into Equation (8).The DC-side resistance R x can be obtained as follows: Based on the transient-state fault analysis, a function establishing a relationship among the DC-side resistance R x , DC-side inductance L x and transient-state surge peak current I peak can be obtained as follows: Obviously, L x can be obtained when R x and I 2 are given.Based on the linear relationship between L x and fault distance d, a location result can be obtained.
The location results and errors of the proposed location method for different fault distances are shown in Table 3 at fault resistances of 0 and 0.05 Ω.The error increases with increasing fault distance and resistance.The method has high with an error less than 5% in the metal short-circuit fault case.However, the error increases significantly in the non-metal short-circuit case due to the following causes: (i) dissatisfying the circumstance Equation ( 23) or (ii) the impedance of the DC side is much higher than that of the AC side.This can be explained as follows: Note that I peak is mainly supplied by natural response current I 2 .According to Equation ( 22), I peak can be approximatively expressed as follows: where K is regarded as constant.
Taking Equation (28)'s partial derivative respect to Z 2 , the derivative function can be obtained as follows: (29) Equation ( 30) means that a small measured or computed error of I peak will result in high deviation of Z 2 under the circumstance of Z 2 Z 1 .Therefore, the fault distance determined by Z 2 is inaccurate.Moreover, according to Equation (30), the location error can be reduced by enlarging the value of Z 1 .Thus, a limiter is installed at AC-side to reduce the error in Table 3.The limiter's parameters are R limit = 0.15 Ω and L limit = 0.75 mH.The location results and errors are shown in Table 4. Obviously, the location error declines dramatically with the limiter installed.In addition, reliable measurement, monitoring and sensor devices are required for error elimination.

Coordination with the Handshaking Method
As analyzed above, the location method proposed has a higher error in a remote fault condition with high resistance.Thus, it has limited advantage when adopted as an independent location method.However, the biggest advantage of this method is easy to realize.The faults are rapidly located without any control and with small quantities of computation.Hence, it is more suitable for fast fault estimation and coordinate with other locations.
In [19], Tang and Ooi proposed a handshaking method for a location fault without any communications in the multi-terminal loop-type DC system.In this method, faults are located according to the following principles: 1.
Disconnect all the sources; 2.
Open the switches that carry the fault current from the bus to the line; 3.
Reconnect all the sources; and 4.
Re-close the switches with both of their poles connected to an energized bus.
This method can effectively locate and isolate the fault extent.However, too many switch operation times and limited selectivity are its disadvantages.For instance, a multi-terminal loop-type DC distribution network is operating as Figure 8 shows.The system parameters are the same as those shown in Table 1, and the length of each cable is 1 km.To ensure safety, the system is open-loop so S1 and S5 are opened.If a fault occurs as Figure 8 shows, according to principle 2 above, S3, S6, S8, S9 and S11 will be opened (Figure 9a).However, according to principle 4 above, only S1 is re-closed after all the sources are reconnected (Figure 9b).Obviously, the fault is located and isolated, but the power supply of load1 and load2 are interrupted.
Energies 2018, 11, x FOR PEER REVIEW 12 of 15 located without any control and with small quantities of computation.Hence, it is more suitable for fast fault estimation and coordinate with other locations.
In [19], Tang and Ooi proposed a handshaking method for a location fault without any communications in the multi-terminal loop-type DC system.In this method, faults are located according to the following principles: 1. Disconnect all the sources; 2. Open the switches that carry the fault current from the bus to the line; 3. Reconnect all the sources; and 4. Re-close the switches with both of their poles connected to an energized bus.This method can effectively locate and isolate the fault extent.However, too many switch operation times and limited selectivity are its disadvantages.For instance, a multi-terminal loop-type DC distribution network is operating as Figure 8 shows.The system parameters are the same as those shown in Table 1, and the length of each cable is 1 km.To ensure safety, the system is open-loop so S1 and S5 are opened.If a fault occurs as Figure 8 shows, according to principle 2 above, S3, S6, S8, S9 and S11 will be opened (Figure 9a).However, according to principle 4 above, only S1 is re-closed after all the sources are reconnected (Figure 9b).Obviously, the fault is located and isolated, but the power supply of load1 and load2 are interrupted.The handshaking method loses its selectivity because not all the buses are connected to a source.However, the location method proposed in Section 4.1 can be adopted to coordinate with the handshaking method to reduce switch operation times and ensure selectivity under this circumstance.The improved principles are as follows: p1.Estimate the fault distance according to the current of each VSC branch; p2.Determine if the operation instructions of switches connected to the same active bus with VSC should be blocked according to the estimated fault distance; Then, the remaining switches operate as steps 1-4 of the original principles.The criterion to block the switch operation instructions is L m < 1.2L min , where L min is the minimal length of cables connected to active bus, and L m is the fault distance calculated by the method proposed in Section 4.1.For instance, the same fault occurs in the DC system, and the peak currents of VSC are I p1 = 0.850 kA, I p2 = 0.720 kA and I p3 = 1.470 kA, respectively.According to Equations ( 26) and ( 27), the distances of the fault to VSC1, VSC2 and VSC3 are 1.45 km, 2.01 km and 0.63 km, respectively (Data in detail are given in appendices).According to step p2, the operation instructions of switches connected to Bus1 and Bus2 should be blocked.Thus, S1, S2, S3, S11 and S12 will not be opened or re-closed until the last step.The remaining switches S6, S8 and S9 will be opened according to step 2 (Figure 10a), and only S6 will be reclosed according to step 4 (Figure 10b).
Hence, switch operation times are reduced and selectivity is ensured after the handshaking method is improved by coordinating with the fault distance estimation.
currents of VSC are = 0.850 kA, = 0.720 kA and = 1.470 kA, respectively.According to Equations ( 26) and ( 27), the distances of the fault to VSC1, VSC2 and VSC3 are 1.45 km, 2.01 km and 0.63 km, respectively (Data in detail are given in appendices).According to step p2, the operation instructions of switches connected to Bus1 and Bus2 should be blocked.Thus, S1, S2, S3, S11 and S12 will not be opened or re-closed until the last step.The remaining switches S6, S8 and S9 will be opened according to step 2 (Figure 10a), and only S6 will be reclosed according to step 4 (Figure 10b).Hence, switch operation times are reduced and selectivity is ensured after the handshaking method is improved by coordinating with the fault distance estimation.

Conclusions
This paper identified the difference in fault analyses between the HVDC-VSC and LVDC-VSC systems.The steady-state fault analyses and the transient-state fault analyses considering forced response and adopting the 3rd-order circuit model are proposed.The new theories are in accordance with the line-to-line short-circuit fault characteristics in a LVDC distribution network based on a VSC.Simulation results demonstrate that the steady-state fault current and transient-state surge peak current can be computed through analytical expressions derived to describe the fault.Compared to the classical theories neglecting the forced response in [4], the analytical expressions in this paper have fewer errors and more significant implications for current limiter designs and fault locations.The proposed fault location method adopting steady-state and transient-state components is effective and meaningful in the case of line-to-line short-circuit faults.The reason for the increase in location

Conclusions
This paper identified the difference in fault analyses between the HVDC-VSC and LVDC-VSC systems.The steady-state fault analyses and the transient-state fault analyses considering forced response and adopting the 3rd-order circuit model are proposed.The new theories are in accordance with the line-to-line short-circuit fault characteristics in a LVDC distribution network based on a VSC.Simulation results demonstrate that the steady-state fault current and transient-state surge peak current can be computed through analytical expressions derived to describe the fault.Compared to the classical theories neglecting the forced response in [4], the analytical expressions in this paper have fewer errors and more significant implications for current limiter designs and fault locations.The proposed fault location method adopting steady-state and transient-state components is effective and meaningful in the case of line-to-line short-circuit faults.The reason for the increase in location error with increased fault distance and resistance is analyzed at the end of the paper, and the corresponding measure is proposed to improve the location accuracy effectively.For implementation in practice, the location method is adopted to coordinate with the handshaking method.Obviously, the improved method has decreased switch operation times and higher selectivity.Further research may lead to further method improvements to reduce location error.

Figure 2 .
Figure 2. The electrical waveforms of different stages: (a) The waveforms in the HVDC system: DC-side voltage V_c (in kV), DC-side current I_dc (in kA), capacitor current I_C (in kA), AC-side feeding current I_ac (in kA), and AC-side three-phase current I_sa,b,c (in kA); (b) The waveforms in the LVDC system: DC-side voltage V_c (in kV), DC-side current I_dc (in kA), capacitor current I_C (in kA), AC-side feeding current I_ac (in kA), and AC-side three-phase current I_sa,b,c (in kA).

Figure 2 .
Figure 2. The electrical waveforms of different stages: (a) The waveforms in the HVDC system: DC-side voltage V_c (in kV), DC-side current I_dc (in kA), capacitor current I_C (in kA), AC-side feeding current I_ac (in kA), and AC-side three-phase current I_sa,b,c (in kA); (b) The waveforms in the LVDC system: DC-side voltage V_c (in kV), DC-side current I_dc (in kA), capacitor current I_C (in kA), AC-side feeding current I_ac (in kA), and AC-side three-phase current I_sa,b,c (in kA).

Figure 3 .
Figure 3.The equivalent circuit for analysis: (a)The simplified circuit model of VSC; (b) The current path and direction.

Figure 3 .
Figure 3.The equivalent circuit for analysis: (a)The simplified circuit model of VSC; (b) The current path and direction.

Figure 3 .
Figure 3.The equivalent circuit for analysis: (a)The simplified circuit model of VSC; (b) The current path and direction.

Figure 4 .
Figure 4.The waveform of steady-state quantities in Figure 3: I dc , I 1 , I 2 , and I 6 (in kA); U dc , U abl , U abs and U an (in kV).

Figure 5 .
Figure 5.The equivalent transient-state circuit model of VSC: (a) the natural response process equivalent circuit; and (b) the forced response process equivalent circuit.

Figure 5 .
Figure 5.The equivalent transient-state circuit model of VSC: (a) the natural response process equivalent circuit; and (b) the forced response process equivalent circuit.

Figure 6 .
Figure 6.The equivalent convert of the RLC circuit.

Figure 8 .
Figure 8.The structure of a multi-terminal loop-type DC distribution network.Figure 8.The structure of a multi-terminal loop-type DC distribution network.

Figure 8 .
Figure 8.The structure of a multi-terminal loop-type DC distribution network.Figure 8.The structure of a multi-terminal loop-type DC distribution network.

Figure 8 .
Figure 8.The structure of a multi-terminal loop-type DC distribution network.

Figure 9 .
Figure 9. Switch operations of the classical handshaking method: (a) Switches state after step 2; (b) Switches state after step 4.

Figure 9 .
Figure 9. Switch operations of the classical handshaking method: (a) Switches state after step 2; (b) Switches state after step 4.

Figure 10 .
Figure 10.Switch operations of the improved handshaking method: (a) Switches state after step 2; (b) Switches state after step 4.

Figure 10 .
Figure 10.Switch operations of the improved handshaking method: (a) Switches state after step 2; (b) Switches state after step 4.

Table 1 .
Simulation parameters and computed initial values.

Table 3 .
Results for the proposed location method.

Table 4 .
Results for the improved proposed location method.