Enhanced Control for Improving the Operation of Grid-Connected Power Converters under Faulty and Saturated Conditions

Mahdi Shahparasti 1,2,* ID , Pedro Catalán 3, Nurul Fazlin Roslan 1, Joan Rocabert 1, Raúl-Santiago Muñoz-Aguilar 1 and Alvaro Luna 1 1 Department of Electrical Engineering, Technical University of Catalonia, 08222 Barcelona, Spain; nurulfazlin@unikl.edu.my (N.F.R.); rocabert@ee.upc.edu (J.R.); raul.munoz-aguilar@upc.edu (R.-S.M.-A.); luna@ee.upc.edu (A.L.) 2 Department of Electrical Engineering, Islamic Azad University, East Tehran Branch, Tehran 14778-93855, Iran 3 Ingeteam Power Technology, Parque Tecnológico de Bizkaia, Edificio 110, 48170 Zamudio, Spain; pedro.catalan@ingeteam.com * Correspondence: mshahparasti@yahoo.com; Tel.: +34-93-739-8549


Introduction
Two-level three-phase voltage source converters (VSCs) are widely used as grid-feeding inverters, which are controlled resembling a current source in many applications, especially in renewable energy systems, high voltage DC transmission systems and microgrids [1][2][3][4][5][6][7], among others.Among linear current controllers, the most extended solutions are those based on using the following reference frames: natural abc, synchronous dq0 and stationary αβ0.No matter the final selection, the resulting controller for the VSC shall be able to track the reference signal fast and with zero steady-state error, as the current control is the inner and fastest control layer [8,9].
Although synchronous dq0 and stationary are mathematically equivalents, using stationary αβ0 reference frame controllers is a very attractive option as it gives rise to a simple digital implementation.In the αβ0 domain, the coordinate transformations are simple and less costly from a computational point of view.Likewise, in this reference frame the cross-coupling terms between control axes are not necessary, as a difference with implementations based on dq0 axis [10].
Among linear controllers Proportional-Integral (PI) controllers and Proportional-Resonant (PR) controllers are the most popular ones.The transient and steady state response of PR controllers in the αβ stationary frame and PI controllers in the dq synchronous frame have the same performance [11].However, using PR controllers in the αβ reference frame give some extra advantages, such as the fact that a single controller is able to control simultaneously the negative and the positive sequences and eliminates the need of using Park transformations, meanwhile its implementation is simple and does not imply a relevant computational cost [12,13].
In renewable energy applications, the limitation of the converter's capacity may give rise to the saturation of the integral terms of the controllers and the system can become unstable or uncontrollable.Therefore, using appropriate methods to avoid saturation of integral terms are vital.In linear applications, two solutions can be employed to prevent system uncontrollability: (1) reference modifier; (2) using a controller with anti-windup capability.In [23] a scheme based on a PI controller is used to reduce the reactive current set point to prevent system uncontrollability, but this is too slow and it is not applicable to transient situations.A PR controller with anti-wind up has been proposed in [7,24] which clamps the output of controller in case of the integrator's saturation, however clamping the output give rise to distortions at the output.
Until now, there are no references in the literature proposing a unified and specific scheme to prevent uncontrollability of GC-VSC.In this paper, a new scheme in the stationary reference frame is proposed to address this issue.The proposed scheme includes a reference modifier located in an outer loop, and a PR controller with anti-wind capability in the inner loop.The reference modifier modifies the references to keep the GC-VSC under control measuring the converter current and the voltage at the output filter of the converter.In the proposed PR controller, the output of the controller is always an AC signal without any dc component.In order to show the good performance of this proposal a real grid-connected VSC application is used to implement the proposed controller.
This paper is organized as follows: in Section 2, the description of the development of proposed control scheme is addressed.Section 3 provides validation results to verify the performance of the proposed controller.The conclusion of the work is presented in Section 4.

Control Strategy
The schematic of a typical grid connected voltage source inverter is shown in Figure 1.In this case the current reference (i * αβ ) is defined based on the active/reactive power references or the current references that should be injected to the grid.In the current loop, the PR controller is tuned to ensure zero steady error and a fast transient response.In the schematic of Figure 1, in order to enhance the dynamic response, a feedforward of the voltage is used.This voltage feedforward, which is multiplied by the coefficient k f , improves the transient response and decrease startup current [25], but, on the other hand, it makes the loop more sensitive to distortions that may affect the voltage.
The schematic of the outer loop block is shown in Figure 2, where the current reference in the stationary reference frame is obtained using the current/power set points and the PCC voltage using the following expression: where, I * a± and I * r± are the active and the reactive components of the converter current set points in the positive/negative reference frame respectively.In this paper a Dual Second Order Generalized Integrator Frequency Locked Loop (DSOGI-FLL), is used for estimating the magnitude of the symmetrical components of the voltage at the PCC.This synchronization system was proven accurate and fast under unbalanced and distorted conditions of the electrical network [26,27].
Energies 2018, 11, x FOR PEER REVIEW 3 of 21 components of the voltage at the PCC.This synchronization system was proven accurate and fast under unbalanced and distorted conditions of the electrical network [26,27].According to standards, the converter should inject reactive currents to support the grid during faults.In grid codes, as the VDE-AR-N 4120 [28], the reactive current reference iq± is defined based on the PCC voltage drop/rise multiplied by the droop coefficient kv±.As in many applications, a dead-band is considered in this case.The value of * is obtained from the reactive current command * plus iq+.The * equals to zero according to standard and the * is equal to iq−.The contribution of GC-VSC to the PCC voltage support is mathematically written in (3) and ( 4) according to VDE-AR-N 4120 [23,28].

( ) ( )
where Vband± is the threshold voltage in which GC-VSC has to work in voltage supporting mode by injecting reactive current to the PCC.Also, ∆| | and | | are equal to 1 | | and | |, in per unit, respectively.components of the voltage at the PCC.This synchronization system was proven accurate and fast under unbalanced and distorted conditions of the electrical network [26,27].According to standards, the converter should inject reactive currents to support the grid during faults.In grid codes, as the VDE-AR-N 4120 [28], the reactive current reference iq± is defined based on the PCC voltage drop/rise multiplied by the droop coefficient kv±.As in many applications, a dead-band is considered in this case.The value of * is obtained from the reactive current command * plus iq+.The * equals to zero according to standard and the * is equal to iq−.The contribution of GC-VSC to the PCC voltage support is mathematically written in (3) and ( 4) according to VDE-AR-N 4120 [23,28].

( ) ( )
where Vband± is the threshold voltage in which GC-VSC has to work in voltage supporting mode by injecting reactive current to the PCC.Also, ∆| | and | | are equal to 1 | | and | |, in per unit, respectively.According to standards, the converter should inject reactive currents to support the grid during faults.In grid codes, as the VDE-AR-N 4120 [28], the reactive current reference i q± is defined based on the PCC voltage drop/rise multiplied by the droop coefficient k v± .As in many applications, a dead-band is considered in this case.The value of I * r+ is obtained from the reactive current command I * q+ plus i q+ .The I * a− equals to zero according to standard and the I * r− is equal to i q− .The contribution of GC-VSC to the PCC voltage support is mathematically written in (3) and ( 4) according to VDE-AR-N 4120 [23,28].

Rate limiter i q+ i q-
where V band± is the threshold voltage in which GC-VSC has to work in voltage supporting mode by injecting reactive current to the PCC.Also, ∆|V + | and |V − | are equal to 1 − |V + | and |V − |, in per unit, respectively.In high power converters the current/power reference does not change following a step, but the set point variations track normally a ramp.In Figure 2, the rate limiter is used to implement these set point changes [25].The current limiter is used to reduce the active current reference in case of grid faults when the reactive current is increased to support the grid voltage [23].Depending on the application, the country and the technology this rate limiter may be different.

Saturation and Uncontrollability Scenarios of a GC-VSC
To show how the VSC can lose the controllability, a VSC is modeled as a controllable voltage source V i which is connected to the PCC through a LC filter, as shown in Figure 3.The grid is simplified as a voltage source, V g , connected in series with an impedance Z g .Only the voltage at the PCC and the inverter current are measured to control the system.In the case of the inductor of the LC filter, the resistive part is neglected as its value is not significant compared to the inductive part.Moreover, the inherent resistor in a real application would introduce damping, what benefits the performance.Therefore, avoiding the resistor makes the analysis even more restrictive and hence the proposed method should perform even better.In this case, the GC-VSC is controlled within the following operating boundaries: (1) Using a space vector modulation the linear control range of the output fundamental component can be extended a 15%.However, for a six-step square-wave controlled inverter, the magnitude of the output fundamental voltage is equal to (2/π) V dc = 0.6366 V dc .Increasing the output voltage of a PWM-controlled inverter from 0.575 V dc to the limit of 0.6366 V dc , is done by entering to the nonlinear region.The region of operation between the loss of linear control (m = 1.15) and complete loss of control (uncontrollability) (m = 1.27) is called the over-modulation region.When over modulation occurs, the modulation index m exceeds the triangle wave in modulator.Note that when m > 1, or m > 1.15 as appropriate, the actual resultant fundamental component does not linearly follow m, and the controller is saturated.Consequently, the shape of the output voltage waveform is only partially under control.Since the modulator effectively loses control of the output waveform during the saturation intervals, the output waveform becomes progressively distorted and includes low-frequency harmonics [29].Therefore, the amplitude and phase of V i is determined by the input voltage of the switching modulator, the switching method and the dc bus voltage V dc .The peak of V i cannot be higher than 0.6366 V dc for any switching methods.When an inverter works in grid-supporting mode or grid-feeding mode, the inverter voltage has to be higher than the PCC voltage to deliver reactive power to the grid.To inject reactive power, if the input of switching modulator is higher than triangle wave, the current controller becomes saturated, hence the inverter becomes uncontrollable and the waveforms of the injected current gets distorted.(2) The GC-VSC current has to be under the semiconductor's current rating.In transient conditions, as for instance: power/current reference sudden change, inverter's start-up or when there is a grid fault, the inverter current may experience some overshoots, due to the delay of the current controller, and the wind-up effect at the integrators of the controllers.However, a high current overshoot might give rise to an undesired converter trip or to a critical damage of the semiconductors.(3) The GC-VSC should help the grid in case of grid faults according to the Low Voltage Ride Through (LVRT) curve.Typically the reactive current coefficient k v± is higher than 2 [23,28]; therefore the active current should be set to zero under severe grid faults to keep the VSC current under the rated value.
Energies 2018, 11, x FOR PEER REVIEW 4 of 21 In high power converters the current/power reference does not change following a step, but the set point variations track normally a ramp.In Figure 2, the rate limiter is used to implement these set point changes [25].The current limiter is used to reduce the active current reference in case of grid faults when the reactive current is increased to support the grid voltage [23].Depending on the application, the country and the technology this rate limiter may be different.

Saturation and Uncontrollability Scenarios of a GC-VSC
To show how the VSC can lose the controllability, a VSC is modeled as a controllable voltage source Vi which is connected to the PCC through a LC filter, as shown in Figure 3.The grid is simplified as a voltage source, Vg, connected in series with an impedance Zg.Only the voltage at the PCC and the inverter current are measured to control the system.In the case of the inductor of the LC filter, the resistive part is neglected as its value is not significant compared to the inductive part.Moreover, the inherent resistor in a real application would introduce damping, what benefits the performance.Therefore, avoiding the resistor makes the analysis even more restrictive and hence the proposed method should perform even better.In this case, the GC-VSC is controlled within the following operating boundaries: (1) Using a space vector modulation the linear control range of the output fundamental component can be extended a 15%.However, for a six-step square-wave controlled inverter, the magnitude of the output fundamental voltage is equal to (2/π) Vdc = 0.6366 Vdc.Increasing the output voltage of a PWM-controlled inverter from 0.575 Vdc to the limit of 0.6366 Vdc, is done by entering to the nonlinear region.The region of operation between the loss of linear control (m = 1.15) and complete loss of control (uncontrollability) (m = 1.27) is called the over-modulation region.When over modulation occurs, the modulation index m exceeds the triangle wave in modulator.Note that when m > 1, or m > 1.15 as appropriate, the actual resultant fundamental component does not linearly follow m, and the controller is saturated.Consequently, the shape of the output voltage waveform is only partially under control.Since the modulator effectively loses control of the output waveform during the saturation intervals, the output waveform becomes progressively distorted and includes low-frequency harmonics [29].Therefore, the amplitude and phase of Vi is determined by the input voltage of the switching modulator, the switching method and the dc bus voltage Vdc.The peak of Vi cannot be higher than 0.6366 Vdc for any switching methods.When an inverter works in grid-supporting mode or grid-feeding mode, the inverter voltage has to be higher than the PCC voltage to deliver reactive power to the grid.To inject reactive power, if the input of switching modulator is higher than triangle wave, the current controller becomes saturated, hence the inverter becomes uncontrollable and the waveforms of the injected current gets distorted.(2) The GC-VSC current has to be under the semiconductor's current rating.In transient conditions, as for instance: power/current reference sudden change, inverter's start-up or when there is a grid fault, the inverter current may experience some overshoots, due to the delay of the current controller, and the wind-up effect at the integrators of the controllers.However, a high current overshoot might give rise to an undesired converter trip or to a critical damage of the semiconductors.(3) The GC-VSC should help the grid in case of grid faults according to the Low Voltage Ride Through (LVRT) curve.Typically the reactive current coefficient kv± is higher than 2 [23,28]; therefore the active current should be set to zero under severe grid faults to keep the VSC current under the rated value.As it can be seen in Figure 3, the output voltage of the inverter, namely V i , can be decomposed into its symmetrical components.In this case, just the positive and negative sequence will be considered, as it is a three-phase three-wire system and thus zero-sequence circuit analysis is not required due to the absence of zero sequence current components.For the positive sequence, the active current, responsible of the active power delivery and the positive sequence voltage are in phase, but the reactive current is shifted 90 degrees with respect to the positive sequence voltage.Regarding the negative sequence, only reactive current is injected to the PCC according to the VDE-AR-N 4120.The negative sequence reactive current is shifted 90 degrees with respect to the negative sequence voltage.In Figures 4-9, the phasor diagrams and numerical results of GC-VSI are shown based on several simulations.The values of voltages and currents are captured from simulation results.As it can be seen in Figure 3, the output voltage of the inverter, namely Vi, can be decomposed into its symmetrical components.In this case, just the positive and negative sequence will be considered, as it is a three-phase three-wire system and thus zero-sequence circuit analysis is not required due to the absence of zero sequence current components.For the positive sequence, the active current, responsible of the active power delivery and the positive sequence voltage are in phase, but the reactive current is shifted 90 degrees with respect to the positive sequence voltage.Regarding the negative sequence, only reactive current is injected to the PCC according to the VDE-AR-N 4120.The negative sequence reactive current is shifted 90 degrees with respect to the negative sequence voltage.In Figures 4-9, the phasor diagrams and numerical results of GC-VSI are shown based on several simulations.The values of voltages and currents are captured from simulation results.
i q-= -0.388 p.u.As it can be seen in Figure 3, the output voltage of the inverter, namely Vi, can be decomposed into its symmetrical components.In this case, just the positive and negative sequence will be considered, as it is a three-phase three-wire system and thus zero-sequence circuit analysis is not required due to the absence of zero sequence current components.For the positive sequence, the active current, responsible of the active power delivery and the positive sequence voltage are in phase, but the reactive current is shifted 90 degrees with respect to the positive sequence voltage.Regarding the negative sequence, only reactive current is injected to the PCC according to the VDE-AR-N 4120.The negative sequence reactive current is shifted 90 degrees with respect to the negative sequence voltage.In Figures 4-9, the phasor diagrams and numerical results of GC-VSI are shown based on several simulations.The values of voltages and currents are captured from simulation results.
i q-= -0.275 p.u.  Figure 4 shows the representation of the positive sequence vector of the voltage and the current in case of balanced voltage sags, when the delivery of reactive power to the grid is required.For balanced voltages, the amplitude of the negative sequence in the grid voltage is zero.Therefore, it is only necessary to analyze the positive sequence performance.However, as it can be deducted from Figure 4, for injecting reactive power to the grid, the amplitude of the inverter voltage must be bigger than the voltage at the PCC.Generally, in the case of balanced voltage sags, there is no difficulty to inject reactive power to grid because the PCC voltage decreases while the DC bus voltage is constant.Hence, the controller will not saturate because of the lack of control action.As an example, the amplitude of currents and voltages for three-phase 70% voltage sag are shown in Figure 4, where the inverter voltage is lower than 1.15 p.u. and anti-saturation is not necessary.However, under normal conditions, the controller can be saturated when the inverter injects reactive power to the grid.In these conditions, the implementation of an effective reference modifier scheme is essential to limit the reactive current set point.
The voltages and currents vector representation considering the occurrence of an unbalanced voltage sag are shown in Figure 5.In addition, the numerical values of two-phase 100% voltage sags are depicted in this figure.In this faulty scenario, in order to improve the positive sequence voltage at the PCC, the inverter should inject reactive power.For injecting reactive power to the PCC (capacitive mode), the positive sequence amplitude of the inverter voltage must be higher than the  Figure 4 shows the representation of the positive sequence vector of the voltage and the current in case of balanced voltage sags, when the delivery of reactive power to the grid is required.For balanced voltages, the amplitude of the negative sequence in the grid voltage is zero.Therefore, it is only necessary to analyze the positive sequence performance.However, as it can be deducted from Figure 4, for injecting reactive power to the grid, the amplitude of the inverter voltage must be bigger than the voltage at the PCC.Generally, in the case of balanced voltage sags, there is no difficulty to inject reactive power to grid because the PCC voltage decreases while the DC bus voltage is constant.Hence, the controller will not saturate because of the lack of control action.As an example, the amplitude of currents and voltages for three-phase 70% voltage sag are shown in Figure 4, where the inverter voltage is lower than 1.15 p.u. and anti-saturation is not necessary.However, under normal conditions, the controller can be saturated when the inverter injects reactive power to the grid.In these conditions, the implementation of an effective reference modifier scheme is essential to limit the reactive current set point.
The voltages and currents vector representation considering the occurrence of an unbalanced voltage sag are shown in Figure 5.In addition, the numerical values of two-phase 100% voltage sags are depicted in this figure.In this faulty scenario, in order to improve the positive sequence voltage at the PCC, the inverter should inject reactive power.For injecting reactive power to the PCC (capacitive mode), the positive sequence amplitude of the inverter voltage must be higher than the Anti-saturation scheme considering positive and negative sequence current references.
Figure 4 shows the representation of the positive sequence vector of the voltage and the current in case of balanced voltage sags, when the delivery of reactive power to the grid is required.For balanced voltages, the amplitude of the negative sequence in the grid voltage is zero.Therefore, it is only necessary to analyze the positive sequence performance.However, as it can be deducted from Figure 4, for injecting reactive power to the grid, the amplitude of the inverter voltage must be bigger than the voltage at the PCC.Generally, in the case of balanced voltage sags, there is no difficulty to inject reactive power to grid because the PCC voltage decreases while the DC bus voltage is constant.Hence, the controller will not saturate because of the lack of control action.As an example, the amplitude of currents and voltages for three-phase 70% voltage sag are shown in Figure 4, where the inverter voltage is lower than 1.15 p.u. and anti-saturation is not necessary.However, under normal conditions, the controller can be saturated when the inverter injects reactive power to the grid.In these conditions, the implementation of an effective reference modifier scheme is essential to limit the reactive current set point.
The voltages and currents vector representation considering the occurrence of an unbalanced voltage sag are shown in Figure 5.In addition, the numerical values of two-phase 100% voltage sags are depicted in this figure.In this faulty scenario, in order to improve the positive sequence voltage at the PCC, the inverter should inject reactive power.For injecting reactive power to the PCC (capacitive mode), the positive sequence amplitude of the inverter voltage must be higher than the PCC voltage.On other hand, the negative sequence reactive current go through the inverter until reaching the PCC.Therefore, the voltage of the inverter contains both positive and negative sequence components.As in the previous case, by making the vector addition of the inverter's voltage components in Figure 5a, it can be seen that the probability of losing controllability is low.
The numerical results and the vector diagrams of a single-phase voltage sag without injecting negative sequence currents are shown in Figure 6.As it can be seen in this plot, if the positive sequence reactive current is bigger than 0.32 p.u., then the controller will be saturated.In fact, the system is working at the border of its controllability, as it can be seen in Figure 6.
The previous case depicted in Figure 6 is repeated again in Figure 7; but in this case, the negative sequence current is injected.As it can be seen, the maximum value of the inverter voltage is reduced from 1.2 p.u. to 1 p.u.In addition, the active positive sequence current is reduced to 0.885 if compared to Figure 6, due to the converter's current limitation.
The vector diagrams and simulation results of the inverter in case of voltage swell are shown in Figure 8.The inverter, by delivering inductive reactive power, contributes to support the operation of the grid and to keep PCC voltage in the standard range.In this case, the value of reactive current is determined based on the PCC voltage deviation multiplied to k v± .For i q+ and i q− equal to −0.79 and −0.517 p.u., the V i+ and V i− have to 1.04 p.u. and 0.21 p.u. respectively.Therefore, the inverter has to produce a V i around 1.25 p.u., which is quite the controllability limit.In these conditions, the controller will become saturated because the value of reactive current (i q+ ) is not suitable, so the value of i q+ needs to be modified and limited by the saturation scheme.

Development of the Proposed Anti-Saturation Scheme
In this section, a new analytical anti-saturation scheme will be proposed.As a difference with other techniques, this proposal does not need information about the equivalent grid impedance (Z g ) or the grid voltage (V g ) and permits the converter to remain stable at normal and faulty situations.The importance of this anti-saturation block is once the vector diagrams of currents and voltages in different conditions were reviewed in the previous section.
In Figure 3 by writing the KVL, the inverter positive sequence voltage can be found as: In the negative sequence domain, only reactive current is injected to the PCC according to VDE-AR-N 4120.The negative sequence reactive current is shifted 90 degrees with respect to the negative sequence voltage.The amplitude of the inverter's voltage in the negative sequence can be written as: where the value of i q− can be positive or negative depending on the transformations, but the Equation ( 6) is correct for any value of i q− .The negative sequence voltage rotates at twice the frequency with respect to the positive sequence voltage.In the worst case, the maximum value of the inverter voltage can be found when the positive sequence voltage and negative sequence voltage have the same direction as shown in Figures 4-8.Therefore: Energies 2018, 11, 525 9 of 21 For an inverter with specific DC voltage, the maximum phase voltage can be found as: Hence, the maximum reactive current can be found by substituting ( 8) into (7): The scheme of the anti-saturation principle written in ( 9) is shown using a block diagram in Figure 9.In Figure 9, the value of i q− is found by multiplying k v− by the negative sequence voltage, meanwhile i q+ is related to the reactive power set point and droop function of the PCC's positive sequence voltage.The DC bus voltage measurement is filtered in order to remove ripples and high frequency noises.In (9) and Figure 9, i p+ is equal to I * a+ .The scheme in Figure 9 is proposed to find the maximum value of reactive current reference to prevent saturation of the controller.In many systems, only the control of the active and reactive power in the positive sequence is important and the current reference can be found from the following equation in Figure 1 [15]: In this section, a new scheme is proposed to determine the maximum of reactive power reference to prevent from controller saturation.
Considering the diagram of Figure 3, the apparent power injected by the inverter to the PCC can be written as: Figure 10 can be used to simplify (11).According to Figure 10, the relationships between voltages can be described by: Hence, the maximum reactive current can be found by substituting ( 8) into (7): The scheme of the anti-saturation principle written in ( 9) is shown using a block diagram in Figure 9.In Figure 9, the value of iq− is found by multiplying kv− by the negative sequence voltage, meanwhile iq+ is related to the reactive power set point and droop function of the PCC's positive sequence voltage.The DC bus voltage measurement is filtered in order to remove ripples and high frequency noises.In (9) and Figure 9, ip+ is equal to * .
The scheme in Figure 9 is proposed to find the maximum value of reactive current reference to prevent saturation of the controller.In many systems, only the control of the active and reactive power in the positive sequence is important and the current reference can be found from the following equation in Figure 1 [15]: In this section, a new scheme is proposed to determine the maximum of reactive power reference to prevent from controller saturation.
Considering the diagram of Figure 3, the apparent power injected by the inverter to the PCC can be written as: Figure 10 can be used to simplify (11).According to Figure 10, the relationships between voltages can be described by: , cos , sin , co s , sin Figure 10.Vector representation of voltages of Figure 3.
Vector representation of voltages of Figure 3. Substituting ( 12) into (11), yields: Squaring the equations of P&Q in ( 14) and ( 15) and rearranging, The maximum apparent power injected by the inverter to the PCC can be found by substituting (8) into (13): Therefore, the maximum reactive power can be found by combining ( 17) and ( 16): The final anti-saturation scheme based of this analytical method is shown in Figure 11.
Energies 2018, 11, x FOR PEER REVIEW 10 of 21 Substituting ( 12) into (11), yields: . sin sin , ( ) Squaring the equations of P&Q in ( 14) and ( 15) and rearranging, ( ) ( ) The maximum apparent power injected by the inverter to the PCC can be found by substituting (8) into (13): Therefore, the maximum reactive power can be found by combining ( 17) and ( 16): The final anti-saturation scheme based of this analytical method is shown in Figure 11.

PR Controller with Anti-Windup Capability
In fact, the anti-wind up of the PR controller and the anti-saturation scheme should work complementary together.In the transient case, the anti-windup block of the PR controller limits the input of the switching modulator and prevents the saturation of the integral terms of the PR controller.In steady state, the anti-saturation reference modifier reduces the reactive current/power reference and prevents the saturation of the controller.
The PR controller can be expressed as: where Kp, Ki, ωo and ωc are the proportional gain, the resonant gain, the resonant frequency and the resonant bandwidth, respectively.The PR controller is used to ensure zero steady-state error and a fast dynamic response.Because of limitations in practical implementations an ideal resonant controller (ωc = 0) cannot be used.The frequency response of PR controller, at frequencies higher than or lower than the resonant frequency all the plots converge to the 20 dB per decade asymptotic response regardless of the value of ωc.The major difference between the different plots is the Anti-saturation scheme considering active and reactive power references.

PR Controller with Anti-Windup Capability
In fact, the anti-wind up of the PR controller and the anti-saturation scheme should work complementary together.In the transient case, the anti-windup block of the PR controller limits the input of the switching modulator and prevents the saturation of the integral terms of the PR controller.In steady state, the anti-saturation reference modifier reduces the reactive current/power reference and prevents the saturation of the controller.
The PR controller can be expressed as: where K p , K i , ω o and ω c are the proportional gain, the resonant gain, the resonant frequency and the resonant bandwidth, respectively.The PR controller is used to ensure zero steady-state error and a fast dynamic response.Because of limitations in practical implementations an ideal resonant controller (ω c = 0) cannot be used.The frequency response of PR controller, at frequencies higher than or lower than the resonant frequency all the plots converge to the 20 dB per decade asymptotic response regardless of the value of ω c .The major difference between the different plots is the increasing peak amplitude at the resonant frequency (ω o ) for smaller values of ω c .The infinite gain benefit of the ideal resonant term only happens at the resonant frequency and any perturbation will lead to a reduction of the generated gain.Hence, the resonant regulator is potentially sensitive to the alignment between the regulator's resonant frequency (ω o ) and the fundamental frequency of the grid.To solve this issue, instantaneous estimation of frequency from FLL is fed to PR controller and the value of resonant bandwidth is set 2 rad/s in this paper.The implemented PR controller based on two integrators is shown in Figure 12.
Energies 2018, 11, x FOR PEER REVIEW 11 of 21 increasing peak amplitude at the resonant frequency (ωo) for smaller values of ωc.The infinite gain benefit of the ideal resonant term only happens at the resonant frequency and any perturbation will lead to a reduction of the generated gain.Hence, the resonant regulator is potentially sensitive to the alignment between the regulator's resonant frequency (ωo) and the fundamental frequency of the grid.To solve this issue, instantaneous estimation of frequency from FLL is fed to PR controller and the value of resonant bandwidth is set 2 rad/s in this paper.The implemented PR controller based on two integrators is shown in Figure 12.The output of the PR controller (input switching modulator (SM)) must be lower than the specific value Omax, otherwise there will be over modulation.In over modulation, the switching frequency is reduced and the waveforms at the inverter's output are distorted [29].The proposed AC limiter (ACL) to limit the input of SM can be expressed as: It is worth mentioning that in common limiters the output is clamped in case of wind up.However, by the proposed method, the input of SM has no clamp and it is always sinusoidal.The value of Omax is chosen based on the switching method.
When a limiter inhibits the output of a controller, any integrators within the controller may experience wind-up, as it can be concluded from Figure 12.In this paper, a new PR controller with anti-windup capability is proposed in Figure 13.The difference between the controller's output and the AC limiter (ACL) lays mainly on the feedback signal to compensate the inputs of the integrators.In this controller, the ACL is used inside of anti-wind-up as the main block.The maximum available output of the PR controller Omax is the main important variable in the anti-windup strategy, which should be selected based on Vdc.The value of Omax (Vimax) depends on the switching method of inverter according to (8).The Vimax is needed for two parts: anti-saturation scheme and anti-windup of PR controller.For anti-saturation scheme is set √3 ⁄ to prevent uncontrollability.For PR controller with anti-windup, mmax is chosen based on the switching method according to Equations ( 21) and (22).Therefore, the allowed maximum value of for three different switching methods: Sinusoidal pulse width modulation (SPWM), Space Vector Pulse Width Modulation (SV-PWM) and Square wave modulation can be found from: 3 The output of the PR controller (input switching modulator (SM)) must be lower than the specific value O max , otherwise there will be over modulation.In over modulation, the switching frequency is reduced and the waveforms at the inverter's output are distorted [29].The proposed AC limiter (ACL) to limit the input of SM can be expressed as: It is worth mentioning that in common limiters the output is clamped in case of wind up.However, by the proposed method, the input of SM has no clamp and it is always sinusoidal.The value of O max is chosen based on the switching method.
When a limiter inhibits the output of a controller, any integrators within the controller may experience wind-up, as it can be concluded from Figure 12.In this paper, a new PR controller with anti-windup capability is proposed in Figure 13.The difference between the controller's output and the AC limiter (ACL) lays mainly on the feedback signal to compensate the inputs of the integrators.In this controller, the ACL is used inside of anti-wind-up as the main block.The maximum available output of the PR controller O max is the main important variable in the anti-windup strategy, which should be selected based on V dc .The value of O max (V imax ) depends on the switching method of inverter according to (8).The V imax is needed for two parts: anti-saturation scheme and anti-windup of PR controller.For anti-saturation scheme is set V dc / √ 3 to prevent uncontrollability.For PR controller with anti-windup, m max is chosen based on the switching method according to Equations ( 21) and (22).Therefore, the allowed maximum value of for three different switching methods: Sinusoidal pulse width modulation (SPWM), Space Vector Pulse Width Modulation (SV-PWM) and Square wave modulation can be found from: where t dead and Ts are the switching dead time and the switching period, respectively.where tdead and Ts are the switching dead time and the switching period, respectively.

Real Time Simulation Results
In order to test the performance of the proposed controller a Typhoon HIL 600 (Typhoon HIL GmbH, Zurich, Switzerland) has been used to emulate the converter and the grid in real time.The proposed control has been implemented in a TI DSP28335 (Texas Instruments Inc., Dallas, TX, USA) hosted in a controller box that includes the acquisition layer and the digital outputs that would take the signals from the sensors and provide the pulses to the inverter.In this way, not only the proposed controller is tested under realistic conditions but also its implementation is made in a commercial platform.
The schematic and the parameters of 4MVA GC-VSC are shown in Figure 14 and Table 1, respectively.The GC-VSC consists of an inverter bridge with six IGBTs, while the grid-side filter consist of a three-phase inductor with a parallel capacitor, as shown in Figure 14.The nominal dclink voltage of the inverter is 1150 V DC.The GC-VSC is connected to the grid through a Dyn1 30/0.69 kV three-phase transformer with a 6% impedance.The maximum acceptable inverter current Imax is 7200A (1.5211 p.u.) and Vimax is considered √3 ⁄ (1.1785 p.u.).The SCR of grid from high voltage side of transformer and X/R of grid impedance are chosen to be 5 and 7, respectively.

Real Time Simulation Results
In order to test the performance of the proposed controller a Typhoon HIL 600 (Typhoon HIL GmbH, Zurich, Switzerland) has been used to emulate the converter and the grid in real time.The proposed control has been implemented in a TI DSP28335 (Texas Instruments Inc., Dallas, TX, USA) hosted in a controller box that includes the acquisition layer and the digital outputs that would take the signals from the sensors and provide the pulses to the inverter.In this way, not only the proposed controller is tested under realistic conditions but also its implementation is made in a commercial platform.
The schematic and the parameters of 4MVA GC-VSC are shown in Figure 14 and Table 1, respectively.The GC-VSC consists of an inverter bridge with six IGBTs, while the grid-side filter consist of a three-phase inductor with a parallel capacitor, as shown in Figure 14.The nominal dc-link voltage of the inverter is 1150 V DC.The GC-VSC is connected to the grid through a Dyn1 30/0.69 kV three-phase transformer with a 6% impedance.The maximum acceptable inverter current I max is 7200A (1.5211 p.u.) and V imax is considered V dc / √ 3 (1.1785p.u.).The SCR of grid from high voltage side of transformer and X/R of grid impedance are chosen to be 5 and 7, respectively.
The tuning procedure for the current controller parameters (K p , K i and k f ) is the one described in [25].In this study case V band± in ( 3) and ( 4) is considered to be 0.1 p.u. and also the droop coefficients k v± have to be higher than 2 according to VDE-AR-N 4120.where tdead and Ts are the switching dead time and the switching period, respectively.

Real Time Simulation Results
In order to test the performance of the proposed controller a Typhoon HIL 600 (Typhoon HIL GmbH, Zurich, Switzerland) has been used to emulate the converter and the grid in real time.The proposed control has been implemented in a TI DSP28335 (Texas Instruments Inc., Dallas, TX, USA) hosted in a controller box that includes the acquisition layer and the digital outputs that would take the signals from the sensors and provide the pulses to the inverter.In this way, not only the proposed controller is tested under realistic conditions but also its implementation is made in a commercial platform.
The schematic and the parameters of 4MVA GC-VSC are shown in Figure 14 and Table 1, respectively.The GC-VSC consists of an inverter bridge with six IGBTs, while the grid-side filter consist of a three-phase inductor with a parallel capacitor, as shown in Figure 14.The nominal dclink voltage of the inverter is 1150 V DC.The GC-VSC is connected to the grid through a Dyn1 30/0.69 kV three-phase transformer with a 6% impedance.The maximum acceptable inverter current Imax is 7200A (1.5211 p.u.) and Vimax is considered √3 ⁄ (1.1785 p.u.).The SCR of grid from high voltage side of transformer and X/R of grid impedance are chosen to be 5 and 7, respectively.
The analysis will be performed in two steps: in the first one the operation of the PR controller with anti-windup will be tested.In a second stage, the capability and operation of the entire proposed scheme including reference modifier and PR controller with anti-windup will be tested.In this regard, it is worth to mention that the Real Time Simulator is an essential device as it permits to emulate all kind of scenarios, which will be almost impossible to find in a conventional experimental setup.

Test of the PR Controller with Anti-Windup Capability
In this section, only the operation of the PR controller is considered and the reference modifier is not employed.In order to show the performance of the PR controller a validation scenario is defined where the reference modifier, which is a part of the proposed scheme (anti-saturation), is not enabled.In this scenario we can show how the performance of the PR controller with the anti-wind up is able to prevent the saturation of the integrators.The plots in Figure 15 gathers the obtained results where I * a+ is set to 0.5 p.u. and I * r+ changes from 0, at t = 0.24 s, to 0.6 p.u. at t = 0.3 s. Figure 15a shows the results obtained from a typical PR controller.As it is proven, the controller is saturated when the reactive current set point I * r+ is higher than 0.5 p.u. and it cannot track the reference current.It is evident from Figure 15a that a PR controller without anti-windup cannot track the current reference after decreasing I * r+ at t = 0.3 s and the system become unstable due to the saturation of the integrators.
The results of a conventional PR controller [7] with anti-windup are shown in Figure 15b.It can be observed that the system is stable after reducing I * r+ at t = 0.3, because the anti-windup prevents the saturation of the integrators.However, when I * r+ increases, the input of the switching modulator is cropped and the quality of injected current is declined.
Energies 2018, 11, x FOR PEER REVIEW 13 of 21 The tuning procedure for the current controller parameters (Kp, Ki and kf) is the one described in [25].In this study case Vband± in (3) and ( 4) is considered to be 0.1 p.u. and also the droop coefficients kv± have to be higher than 2 according to VDE-AR-N 4120.
The analysis will be performed in two steps: in the first one the operation of the PR controller with anti-windup will be tested.In a second stage, the capability and operation of the entire proposed scheme including reference modifier and PR controller with anti-windup will be tested.In this regard, it is worth to mention that the Real Time Simulator is an essential device as it permits to emulate all kind of scenarios, which will be almost impossible to find in a conventional experimental setup.

Test of the PR Controller with Anti-Windup Capability
In this section, only the operation of the PR controller is considered and the reference modifier is not employed.In order to show the performance of the PR controller a validation scenario is defined where the reference modifier, which is a part of the proposed scheme (anti-saturation), is not enabled.In this scenario we can show how the performance of the PR controller with the anti-wind up is able to prevent the saturation of the integrators.The plots in Figure 15 gathers the obtained results where * is set to 0.5 p.u. and * changes from 0, at t = 0.24 s, to 0.6 p.u. at t = 0.3 s.
Figure 15a shows the results obtained from a typical PR controller.As it is proven, the controller is saturated when the reactive current set point * is higher than 0.5 p.u. and it cannot track the reference current.It is evident from Figure 15a that a PR controller without anti-windup cannot track the current reference after decreasing * at t = 0.3 s and the system become unstable due to the saturation of the integrators.
The results of a conventional PR controller [7] with anti-windup are shown in Figure 15b.It can be observed that the system is stable after reducing * at t = 0.3, because the anti-windup prevents the saturation of the integrators.However, when * increases, the input of the switching modulator is cropped and the quality of injected current is declined.
Finally, the performance of the proposed PR controller of this paper with anti-wind-up capability are shown in Figure 15c.It is evident that this scheme prevents from saturation integrators and the system become stable after decreasing * .Also, during the period where uncontrollability may arise, from t = 0.24 s until t = 0.3 s, the injected current is almost sinusoidal thanks to the proposed AC limiter.

Test of the Entire Proposed Scheme
In this section, some situations are considered where the whole proposed scheme has been implemented in order to prevent uncontrollability issues.
First, a grid with Vag = 0.5 p.u., Vbg = 1.8 p.u. and Vcg = 1.8 p.u. is considered.It worth to mention that without anti-saturation the system becomes unstable.The results for SCR = 5 are shown from Figures 16-18, where the voltage fault happens from t = 0.25 s until t = 0.4 s.
As shown in Figure 16, when the voltage fault occurs at t = 0.25 seconds, the following actions are performed: (1) Positive sequence reactive current reference becomes negative value −0.45 p.u. according to the VDE-AR-N 4120 for grid supporting.However, this value is not suitable and it should be reduced more for stabilizing of the control system.(2) The anti-saturation scheme reduces positive sequence reactive current set point to −1 p.u. to prevent system uncontrollability.(3) The negative sequence reactive current set point is increased from zero p.u. to 0.5 p.u. to decrease the negative sequence voltage at the PCC.(4) The positive sequence active current set point is reduced to zero to limit the converter's current.
It can be seen from Figure 16 that the duty cycle is lower than 1 during the fault, due to the action of the anti-saturation scheme.
The final set point of the active and the reactive current in the positive sequence is shown in Figure 17, where * and * are zero and −1 during voltage fault, respectively.
Figure 18 shows the voltage and current waveforms at both, PCC and grid side, for the first scenario.In this case, at the high voltage side of the transformer a severe fault has occurred, as the voltage of two phases increases an 80% and the third phase voltage is reduced 50%.However, it is clear that the proposed scheme forces GC-VSC to inject a suitable current in order to support the grid voltage.Therefore, the voltage at the PCC is almost balanced and compensated compared to the one measured at the high voltage side of the transformer.
The outer loop generates the current reference in the stationary reference frame (two sinusoidal current references) based on the positive and negative sequence of the PCC voltage and the active Finally, the performance of the proposed PR controller of this paper with anti-wind-up capability are shown in Figure 15c.It is evident that this scheme prevents from saturation integrators and the system become stable after decreasing I * r+ .Also, during the period where uncontrollability may arise, from t = 0.24 s until t = 0.3 s, the injected current is almost sinusoidal thanks to the proposed AC limiter.

Test of the Entire Proposed Scheme
In this section, some situations are considered where the whole proposed scheme has been implemented in order to prevent uncontrollability issues.
First, a grid with V ag = 0.5 p.u., V bg = 1.8 p.u. and V cg = 1.8 p.u. is considered.It worth to mention that without anti-saturation the system becomes unstable.The results for SCR = 5 are shown from Figures 16-18, where the voltage fault happens from t = 0.25 s until t = 0.4 s.
As shown in Figure 16, when the voltage fault occurs at t = 0.25 seconds, the following actions are performed: (1) Positive sequence reactive current reference becomes negative value −0.45 p.u. according to the VDE-AR-N 4120 for grid supporting.However, this value is not suitable and it should be reduced more for stabilizing of the control system.(2) The anti-saturation scheme reduces positive sequence reactive current set point to −1 p.u. to prevent system uncontrollability.(3) The negative sequence reactive current set point is increased from zero p.u. to 0.5 p.u. to decrease the negative sequence voltage at the PCC.(4) The positive sequence active current set point is reduced to zero to limit the converter's current.
It can be seen from Figure 16 that the duty cycle is lower than 1 during the fault, due to the action of the anti-saturation scheme.
The final set point of the active and the reactive current in the positive sequence is shown in Figure 17, where I * a+ and I * r+ are zero and −1 during voltage fault, respectively.Figure 18 shows the voltage and current waveforms at both, PCC and grid side, for the first scenario.In this case, at the high voltage side of the transformer a severe fault has occurred, as the voltage of two phases increases an 80% and the third phase voltage is reduced 50%.However, it is clear that the proposed scheme forces GC-VSC to inject a suitable current in order to support the grid voltage.Therefore, the voltage at the PCC is almost balanced and compensated compared to the one measured at the high voltage side of the transformer.
The outer loop generates the current reference in the stationary reference frame (two sinusoidal current references) based on the positive and negative sequence of the PCC voltage and the active and reactive current references.The resulting current reference is followed with a zero-steady state error and a suitable transient response, as it can be seen in Figure 18.It is worth to remark that the current of the converter has always been below the maximum value, hence within safety margins.and reactive current references.The resulting current reference is followed with a zero-steady state error and a suitable transient response, as it can be seen in Figure 18.It is worth to remark that the current of the converter has always been below the maximum value, hence within safety margins.
In the second scenario, a single-phase to ground unbalanced voltage sag for the grid with SCR = 2 is presented all while the negative sequence current is not injected to the PCC during voltage fault.The value negative sequence voltage for grid, PCC and inverter are the same due to the negative current is zero.The kv+ droop coefficient is set to 6 to show the performance of anti-saturation scheme.The obtained results are shown in Figures 19-21.and reactive current references.The resulting current reference is followed with a zero-steady state error and a suitable transient response, as it can be seen in Figure 18.It is worth to remark that the current of the converter has always been below the maximum value, hence within safety margins.
In the second scenario, a single-phase to ground unbalanced voltage sag for the grid with SCR = 2 is presented all while the negative sequence current is not injected to the PCC during voltage fault.The value negative sequence voltage for grid, PCC and inverter are the same due to the negative current is zero.The kv+ droop coefficient is set to 6 to show the performance of anti-saturation scheme.The obtained results are shown in Figures 19-21.In the second scenario, a single-phase to ground unbalanced voltage sag for the grid with SCR = 2 is presented all while the negative sequence current is not injected to the PCC during voltage fault.The value negative sequence voltage for grid, PCC and inverter are the same due to the negative current is zero.The k v+ droop coefficient is set to 6 to show the performance of anti-saturation scheme.The obtained results are shown in Figures 19-21.
As it can be seen in the plots the V band is 0.1 p.u. and the magnitude of positive sequence voltage is lower 0.9 and it has some fluctuations.Hence, ∆V + = 1 − |V + | is higher than 0.1 and the inverter has to inject reactive current (reactive power) to PCC.Based on (3): i q+ = K v+ (∆V + − 0.1).According to [28], k v+ droop coefficient has to be higher than 2. To show performance of proposed scheme in limiting reactive current set point (I * r+ ), k v+ is set 6. From Figure 19, it can be seen that during the fault the value of the positive sequence reactive current reference i q+ is around 0.6 p.u., which leads to the controller saturation.Therefore, i q+ is cropped by the anti-saturation scheme to around 0.25 p.u. to prevent uncontrollability.Therefore, i q+ is around 0.6 p.u. and I * r+ is around 0.25 p.u.The results in Figure 20 show the set points of positive sequence active and reactive currents.The active current is not limited because the converter current is lower than the nominal value.
The voltage and current waveforms of the grid and the PCC in the case of a single-phase unbalanced sag (type B-second scenario) are shown in Figure 21.In the high voltage side of transformer, only the voltage of phase A is reduced.Likewise, the voltage of the PCC is unbalanced and distorted similar to the high side of transformer.As it can be seen, in spite of the voltage at the PCC, the proposed outer loop generates correctly the reference currents.The PR controller later tracks this current reference without giving rise to any overshoot or steady state error, endorsing thus the good performance of the proposed control scheme.It is clear from the current waveforms that the peak value is below than the maximum nominal value.In addition, the grid and the converter currents have a satisfactory performance.As it can be seen in the plots the Vband is 0.1 p.u. and the magnitude of positive sequence voltage is lower 0.9 and it has some fluctuations.Hence, ΔV+ = 1 − |V+| is higher than 0.1 and the inverter has to inject reactive current (reactive power) to PCC.Based on (3): iq+ = Kv+(ΔV+ − 0.1).According to [28], kv+ droop coefficient has to be higher than 2. To show performance of proposed scheme in limiting reactive current set point ( * ), kv+ is set 6.
From Figure 19, it can be seen that during the fault the value of the positive sequence reactive current reference iq+ is around 0.6 p.u., which leads to the controller saturation.Therefore, iq+ is cropped by the anti-saturation scheme to around 0.25 p.u. to prevent uncontrollability.Therefore, iq+

Conclusions
In this paper, a proposal for overcoming the uncontrollability and instability issues of GC-VSC that appear under certain conditions linked to the fulfilment of LVRT requirement was presented.In this work, it was mathematically proven that GC-VSC may lose controllability under different operating conditions.For instance, under normal grid conditions when absorbing/injecting a high value of reactive power in capacitive/inductive mode or under severe grid fault scenarios due to the generation of unsuitable current/power references.In order to keep the GC-VSC under control, a new scheme with two parts were embedded to the outer reference generation loop and the inner current loop.A new PR controller with anti-windup capability was introduced as a controller in the current loop.Compared to other anti-windup implementations, the proposed solution has shown a good performance for integrating wind-up in PR controller, as well as to keep the output currents always limited and sinusoidal.Concerning the reference generation loop, the proposed reference modifier has shown that it is able to adjust the reactive reference taking into account the grid conditions and the operation points, with no need of knowing the grid voltage and impedance.The validation carried out in this work has permitted to demonstrate that the proposed scheme is a very suitable solution for accurately keeping the GC-VSC within its optimal operation boundaries under generic grid conditions.
was in charge of the real time validation of the proposed system.Alvaro Luna proposed contributed to select the topic, determine the study case and he conducted the overall supervision of the paper.

Conflicts of Interest:
The authors declare no conflict of interest.V α1+ , V β1+ fundamental components of positive sequence of PCC voltage in stationary reference frame V α1− , V β1− fundamental components of negative sequence of PCC voltage in stationary reference frame V + , V − space vector of PCC voltage in positive and negative sequences V αg1+ , V βg1+ fundamental components of positive sequence of grid voltage in stationary reference frame V αg1− , V βg1− fundamental components of negative sequence of grid voltage in stationary reference frame V g+ , V g− space vector of grid voltage in positive and negative sequences Zg equivalent grid impedance

Nomenclature
resonant frequency in rad/s and resonant bandwidth in rad/s

Figure 2 .
Figure 2. Schematic of the outer loop including the proposed anti-saturation scheme to generate the current reference.

Figure 2 .
Figure 2. Schematic of the outer loop including the proposed anti-saturation scheme to generate the current reference.

Figure 2 .
Figure 2. Schematic of the outer loop including the proposed anti-saturation scheme to generate the current reference.

Figure 4 .
Figure 4. Vector representation of voltages and currents of GC-VSC working at normal grid conditions or balanced voltage changes while injecting reactive power.

Figure 5 .
Figure 5. Vector representation of voltages and currents GC-VSC when there is an unbalanced voltage sag.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in the worst case. i

Figure 4 .
Figure 4. Vector representation of voltages and currents of GC-VSC working at normal grid conditions or balanced voltage changes while injecting reactive power.

Figure 4 .
Figure 4. Vector representation of voltages and currents of GC-VSC working at normal grid conditions or balanced voltage changes while injecting reactive power.

Figure 5 .
Figure 5. Vector representation of voltages and currents GC-VSC when there is an unbalanced voltage sag.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in the worst case. i

Figure 5 .Figure 6 .
Figure 5. Vector representation of voltages and currents GC-VSC when there is an unbalanced voltage sag.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in the worst case.

Figure 7 .
Figure 7. Vector representation of voltages and currents of GC-VSC for unbalanced one phase 100% voltage sag injecting negative sequence current during the fault.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in worst case. i

Figure 6 . 21 Figure 6 .
Figure 6.Vector representation of voltages and currents GC-VSC for unbalanced voltage sag without injecting negative sequence current during the fault.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in the worst case.

Figure 7 .
Figure 7. Vector representation of voltages and currents of GC-VSC for unbalanced one phase 100% voltage sag injecting negative sequence current during the fault.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in worst case. i

Figure 7 . 21 Figure 8 .
Figure 7. Vector representation of voltages and currents of GC-VSC for unbalanced one phase 100% voltage sag injecting negative sequence current during the fault.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in worst case.

Figure 9 .
Figure 9. Anti-saturation scheme considering positive and negative sequence current references.

Figure 8 . 21 Figure 8 .
Figure 8. Vector representation of voltages and currents of GC-VSC for voltage swell.(a) Positive sequence.(b) Negative sequence.(c) Inverter voltage in the worst case.

Figure 9 .
Figure 9. Anti-saturation scheme considering positive and negative sequence current references.

Figure 11 .
Figure 11.Anti-saturation scheme considering active and reactive power references.

Figure 12 .
Figure 12.Block diagram of PR controller with two integrators.

Figure 13 .
Figure 13.Block diagram of proposed PR controller with anti-wind-up capability.

Figure 14 .
Figure 14.Schematic of the validation layout.

Figure 13 .
Figure 13.Block diagram of proposed PR controller with anti-wind-up capability.

Figure 13 .
Figure 13.Block diagram of proposed PR controller with anti-wind-up capability.

Figure 14 .
Figure 14.Schematic of the validation layout.

Figure 14 .
Figure 14.Schematic of the validation layout.

Figure 16 .
Figure 16.Voltage faults: Vag = 0.5 p.u., Vbg = 1.8 p.u., Vcg = 1.8 p.u., with anti-saturation for SCR = 5.From top to bottom: in first figure active current reference, reactive current reference and the maximum available reactive current reference; in second figure active and reactive output power of converter; in third figure duty cycle; and in fourth figure magnitude of positive and negative sequence of PCC voltage and grid voltage.

Figure 16 .
Figure 16.Voltage faults: V ag = 0.5 p.u., V bg = 1.8 p.u., V cg = 1.8 p.u., with anti-saturation for SCR = 5.From top to bottom: in first figure active current reference, reactive current reference and the maximum available reactive current reference; in second figure active and reactive output power of converter; in third figure duty cycle; and in fourth figure magnitude of positive and negative sequence of PCC voltage and grid voltage.

Figure 16 .
Figure 16.Voltage faults: Vag = 0.5 p.u., Vbg = 1.8 p.u., Vcg = 1.8 p.u., with anti-saturation for SCR = 5.From top to bottom: in first figure active current reference, reactive current reference and the maximum available reactive current reference; in second figure active and reactive output power of converter; in third figure duty cycle; and in fourth figure magnitude of positive and negative sequence of PCC voltage and grid voltage.

Figure 18 .
Figure 18.Voltage faults: Vag = 0.5 p.u., Vbg = 1.8 p.u., Vcg = 1.8 p.u. From top to bottom: in first figure the voltage of grid; in second figure PCC voltage; in third figure converter current; and in fourth figure the current of grid and in fifth figure actual and reference currents in αβ axes.

Figure 19 .
Figure 19.Voltage faults: 1ph 100% voltage sag without injecting negative sequence current with antisaturation for SCR = 2. From top to bottom: in first figure active current reference, reactive current reference and the maximum available reactive current reference; in second figure active and reactive output power of converter; in third figure duty cycle; and in fourth figure magnitude of positive and negative sequence of PCC voltage and grid voltage.

Figure 18 .
Figure 18.Voltage faults: V ag = 0.5 p.u., V bg = 1.8 p.u., V cg = 1.8 p.u. From top to bottom: in first figure the voltage of grid; in second figure PCC voltage; in third figure converter current; and in fourth figure the current of grid and in fifth figure actual and reference currents in αβ axes.

Figure 18 .
Figure 18.Voltage faults: Vag = 0.5 p.u., Vbg = 1.8 p.u., Vcg = 1.8 p.u. From top to bottom: in first figure the voltage of grid; in second figure PCC voltage; in third figure converter current; and in fourth figure the current of grid and in fifth figure actual and reference currents in αβ axes.

Figure 19 .
Figure 19.Voltage faults: 1ph 100% voltage sag without injecting negative sequence current with antisaturation for SCR = 2. From top to bottom: in first figure active current reference, reactive current reference and the maximum available reactive current reference; in second figure active and reactive output power of converter; in third figure duty cycle; and in fourth figure magnitude of positive and negative sequence of PCC voltage and grid voltage.

Figure 19 .
Figure 19.Voltage faults: 1ph 100% voltage sag without injecting negative sequence current with anti-saturation for SCR = 2. From top to bottom: in first figure active current reference, reactive current reference and the maximum available reactive current reference; in second figure active and reactive output power of converter; in third figure duty cycle; and in fourth figure magnitude of positive and negative sequence of PCC voltage and grid voltage.Energies 2018, 11, x FOR PEER REVIEW 17 of 21

Figure 20 .
Figure 20.Set points of active and reactive currents in positive sequence in case of 1ph 100% voltage sag without injecting negative sequence current.

Figure 20 .
Figure 20.Set points of active and reactive currents in positive sequence in case of 1ph 100% voltage sag without injecting negative sequence current.

Figure 20 .
Figure 20.Set points of active and reactive currents in positive sequence in case of 1ph 100% voltage sag without injecting negative sequence current.

Figure 21 .
Figure 21.Voltage faults: 1ph 100% voltage sag without injecting negative sequence current.From top to bottom: in first figure the voltage of grid; in second figure PCC voltage; in third figure converter current; and in fourth figure the current of grid and in fifth figure actual and reference currents in αβ axes.

Figure 21 .
Figure 21.Voltage faults: 1ph 100% voltage sag without injecting negative sequence current.From top to bottom: in first figure the voltage of grid; in second figure PCC voltage; in third figure converter current; and in fourth figure the current of grid and in fifth figure actual and reference currents in αβ axes.

PR controller with anti-wind up capability [7]
The Real Time Simulation of inverter with different PR controller for SCR = 5.From top to bottom: in first figure active and reactive current references; in second figure actual and reference currents in αβ axes; in third figure duty cycle; and in fourth figure converter current and in fifth figure PCC voltage.
negative sequence components of converter current reference in stationary reference frame i p+ , i q+ active and reactive components of inverter current in positive sequence i p− , i q− active and reactive components of inverter current in negative sequence I * a+ , I * r+ set points of active and reactive current in positive sequence I * a− , I * r− set points of active and reactive current in negative sequence I * p+ , I * q+ active and reactive current command in positive sequence