Design of Peak Efficiency of 85.3% WPC/PMA Wireless Power Receiver Using Synchronous Active Rectifier and Multi Feedback Low-Dropout Regulator

Using Synchronous Active Rectifier and Multi Feedback Low-Dropout Regulator Authors: Zaffar Hayat Nawaz Khan, Young-Jun Park, Seong Jin Oh, Byeong Gi Jang, Seong-Mun Park, Hamed Abbasizadeh, Young Gun Pu, Keum Cheol Hwang, Youngoo Yang, Minjae Lee, Kang-Yoon Lee Date Submitted: 2020-02-24


Introduction
Wireless power transfer (WPT) technology is getting significant attention in recent research, especially with mobile phone chargers. Its applications vary from medical components to automobiles [1]. The inductive coupling method is one of the popular WPT methods applicable for a distance below 0.5 cm with a transfer frequency in the range of 87 kHz to 375 kHz. This method is standardized by two consortiums: Wireless Power Consortium (WPC) and the Power Matters Alliance (PMA). Whatever we use the charging technique for, maintaining a high efficiency is necessary which is important because low efficiency will produce heat from the receiver which creates several problems. Under normal conditions, a WPT system has more than 5 W of power at its input, low efficiency of the receiver causes heat which reduces the receiver efficiency [2][3][4][5][6]. Usually, the whole efficiency of wireless power receiver (WPR) is controlled by the rectifier [7]. As low-dropout (LDO) regulators get their DC supply from the rectifier, rectifier efficiency is crucial. The output voltage of rectifier determines the LDO regulator's efficiency. Protection functions like over current protection (OCP), over voltage protection (OVP), and adaptive communication limit (ACL) are unified with the LDO regulator.
This study proposes an efficient active rectifier and multi-feedback LDO (MF-LDO) regulator coupled with a wireless power receiver. Section 2 describes the architecture and building blocks of inductive coupling WPR. The simulation results are presented in Sections 3 and 4 summarizes the paper.

Architecture
The simplified block diagram of the wireless power receiver is depicted in Figure 1 where the power is transmitted to the receiver through the coil. The impedance matching network maximizes the power transfer from the receiving coil to active rectifier. The active rectifier converts the input AC signals (AC 1 and AC 2 ) to DC voltage. The proposed active rectifier uses synchronous control by tracking input frequency by ZCS (zero current sensing) with a monostable circuit to eliminate the double pulse problem. The battery needs regulated DC voltage which is generated by the MF-LDO regulator. Protection functions are integrated to the proposed MF-LDO in this work. A 10-bit ADC converts the internal analog signals from several blocks into digital signals. The digital control block collects them and arranges the packets based on them. To perform the load modulation, it serializes the parallel data into serial data and finally delivers to the modulator. In this work, a complete wireless power receiver (WPR) is designed with proposed active rectifier and MF-LDO.

Architecture
The simplified block diagram of the wireless power receiver is depicted in Figure 1 where the power is transmitted to the receiver through the coil. The impedance matching network maximizes the power transfer from the receiving coil to active rectifier. The active rectifier converts the input AC signals (AC1 and AC2) to DC voltage. The proposed active rectifier uses synchronous control by tracking input frequency by ZCS (zero current sensing) with a monostable circuit to eliminate the double pulse problem. The battery needs regulated DC voltage which is generated by the MF-LDO regulator. Protection functions are integrated to the proposed MF-LDO in this work. A 10-bit ADC converts the internal analog signals from several blocks into digital signals. The digital control block collects them and arranges the packets based on them. To perform the load modulation, it serializes the parallel data into serial data and finally delivers to the modulator. In this work, a complete wireless power receiver (WPR) is designed with proposed active rectifier and MF-LDO.

Active Rectifier
A design of active rectifier is proposed in this work which receives AC input voltage, the polarity of this input voltage decides which metal oxide semiconductor (MOS) transistor will turn on and off actively in the active rectifier, as exhibited in Figure 2. High power conversion efficiency is achieved because, at MOS transistors, less voltage drop can be made as compared to diode-based passive rectifier [8].
The rectifier efficiency is calculated by Equation (1). In this equation; Vdo = Voltage drop in conducting path Iloss = Current loss, defined by the reverse current leakage in power stage As the power transfer begins, the active rectifier operates in passive mode and operates in active mode when VRECT gets voltage of the required power level.
The received AC power input rectification power conversion efficiency will be low with high output power level, therefore, the power efficiency of the rectifier is maximized by minimizing Vdo [9]. Passive diodes have some forward voltage drop which can limit the efficiency of a rectifier [8,10,11].
On the other hand, MOS transistors have a bidirectional current flow where current flow will be from DC output to AC input. Power conversion efficiency is extremely reduced by this leakage current [12][13][14][15][16].

Active Rectifier
A design of active rectifier is proposed in this work which receives AC input voltage, the polarity of this input voltage decides which metal oxide semiconductor (MOS) transistor will turn on and off actively in the active rectifier, as exhibited in Figure 2. High power conversion efficiency is achieved because, at MOS transistors, less voltage drop can be made as compared to diode-based passive rectifier [8].
The rectifier efficiency is calculated by Equation (1). In this equation; V do = Voltage drop in conducting path I loss = Current loss, defined by the reverse current leakage in power stage As the power transfer begins, the active rectifier operates in passive mode and operates in active mode when V RECT gets voltage of the required power level.
The received AC power input rectification power conversion efficiency will be low with high output power level, therefore, the power efficiency of the rectifier is maximized by minimizing V do [9]. Passive diodes have some forward voltage drop which can limit the efficiency of a rectifier [8,10,11].
On the other hand, MOS transistors have a bidirectional current flow where current flow will be from DC output to AC input. Power conversion efficiency is extremely reduced by this leakage current [12][13][14][15][16]. In Figure 3, the ZCS circuit senses the current of the active rectifier to prevent the reverse leakage current. To generate the gate signals (LI1, HI1) that turn on and off MLS1 and MHS1 respectively, the ZCS circuit senses source voltages (VSEN1) of the sensing MOSFET (MSEN1). Also, gate control signals of LI2 and HI2 are generated by MSEN2 in the same way. The gate control signals (LI1, HI1) are turned and off based on Equations (2) and (3). The efficiency of the active rectifier is improved by the ZCS circuits because reverse currents of the active rectifier are prevented. The resistors of R0, R1, R2, and R3 with a low-temperature variation are used in ZCS circuit. The VREF1 and VCS voltages are generated by resistive ratio. Therefore, the ZCS circuit is designed strongly against the change in PVT variation. The monostable circuit and SR latch in the ZCS circuits are used to prevent the double pulse problem by glitches in the gate signals (LI1,2 and HI1,2).
The timing diagram of the ZCS circuit is shown in Figure 4a. At zero crossing point of ZCS_SET is generated. In Figure 2 In Figure 3, the ZCS circuit senses the current of the active rectifier to prevent the reverse leakage current. To generate the gate signals (LI 1 , HI 1 ) that turn on and off M LS1 and M HS1 respectively, the ZCS circuit senses source voltages (V SEN1 ) of the sensing MOSFET (M SEN1 ). Also, gate control signals of LI 2 and HI 2 are generated by M SEN2 in the same way. The gate control signals (LI 1 , HI 1 ) are turned and off based on Equations (2) and (3). In Figure 3, the ZCS circuit senses the current of the active rectifier to prevent the reverse leakage current. To generate the gate signals (LI1, HI1) that turn on and off MLS1 and MHS1 respectively, the ZCS circuit senses source voltages (VSEN1) of the sensing MOSFET (MSEN1). Also, gate control signals of LI2 and HI2 are generated by MSEN2 in the same way. The gate control signals (LI1, HI1) are turned and off based on Equations (2) and (3). The efficiency of the active rectifier is improved by the ZCS circuits because reverse currents of the active rectifier are prevented. The resistors of R0, R1, R2, and R3 with a low-temperature variation are used in ZCS circuit. The VREF1 and VCS voltages are generated by resistive ratio. Therefore, the ZCS circuit is designed strongly against the change in PVT variation. The monostable circuit and SR latch in the ZCS circuits are used to prevent the double pulse problem by glitches in the gate signals (LI1,2 and HI1,2).
The timing diagram of the ZCS circuit is shown in Figure 4a. At zero crossing point of ZCS_SET is generated. In Figure  The efficiency of the active rectifier is improved by the ZCS circuits because reverse currents of the active rectifier are prevented. The resistors of R 0 , R 1 , R 2 , and R 3 with a low-temperature variation are used in ZCS circuit. The V REF1 and V CS voltages are generated by resistive ratio. Therefore, the ZCS circuit is designed strongly against the change in PVT variation. The monostable circuit and SR latch in the ZCS circuits are used to prevent the double pulse problem by glitches in the gate signals (LI 1,2 and HI 1,2 ).
The timing diagram of the ZCS circuit is shown in Figure 4a. At zero crossing point of ZCS_SET is generated. In The simulation results of the Active rectifier are shown Figure 4b. When I AC is 20 mA, the LG 1 and HG 1 are turned on. On the other hand, when the I AC is less than 5 mA, LG 1 , and HG 1 are turned off and the reverse leakage current is blocked.
Energies 2017, 10, x FOR PEER REVIEW 4 of 10 The simulation results of the Active rectifier are shown Figure 4b. When IAC is 20 mA, the LG1 and HG1 are turned on. On the other hand, when the IAC is less than 5 mA, LG1, and HG1 are turned off and the reverse leakage current is blocked.

Multi Feedback LDO (MF-LDO) Regulator
A regulated DC output is provided to the charger IC before the battery and this is provided by the LDO regulator. In the WPR system, the receiver needs various protection functions. In a conventional LDO regulator, the voltage feedback loop is implemented. A MF-LDO regulator is proposed in Figure 5, in which the protection functions are incorporated to low-dropout regulator. The MF-LDO regulator shares the power transistor MP1, to save die area. Figure 6 shows simplified functional diagram of multi feedback LDO. The load current, IOUT, is defined by VG, VRECT, and VOUT voltages. VOUT and VRECT voltages are defined by the specification and the active rectifier respectively. Therefore, only VG controls the IOUT, and is derived from Equation (4).

Multi Feedback LDO (MF-LDO) Regulator
A regulated DC output is provided to the charger IC before the battery and this is provided by the LDO regulator. In the WPR system, the receiver needs various protection functions. In a conventional LDO regulator, the voltage feedback loop is implemented. A MF-LDO regulator is proposed in Figure 5, in which the protection functions are incorporated to low-dropout regulator. The MF-LDO regulator shares the power transistor M P1 , to save die area. Figure 6 shows simplified functional diagram of multi feedback LDO. The load current, I OUT , is defined by V G , V RECT , and V OUT voltages. V OUT and V RECT voltages are defined by the specification and the active rectifier respectively. Therefore, only V G controls the I OUT , and is derived from Equation (4).
Energies 2017, 10, x FOR PEER REVIEW 4 of 10 The simulation results of the Active rectifier are shown Figure 4b. When IAC is 20 mA, the LG1 and HG1 are turned on. On the other hand, when the IAC is less than 5 mA, LG1, and HG1 are turned off and the reverse leakage current is blocked.

Multi Feedback LDO (MF-LDO) Regulator
A regulated DC output is provided to the charger IC before the battery and this is provided by the LDO regulator. In the WPR system, the receiver needs various protection functions. In a conventional LDO regulator, the voltage feedback loop is implemented. A MF-LDO regulator is proposed in Figure 5, in which the protection functions are incorporated to low-dropout regulator. The MF-LDO regulator shares the power transistor MP1, to save die area. Figure 6 shows simplified functional diagram of multi feedback LDO. The load current, IOUT, is defined by VG, VRECT, and VOUT voltages. VOUT and VRECT voltages are defined by the specification and the active rectifier respectively. Therefore, only VG controls the IOUT, and is derived from Equation (4). In the normal operation mode of MF-LDO, the I SINK current discharges the V G node constantly. Also, the I FB current is generated by voltage feedback loop. Therefore, V OUT voltage is regulated constantly, and the V G voltage is changed depending on I OUT currents. In the protection modes of MF-LDO-such as OCP, OVP, or ACL modes-I OCP , I OVP , and I ACL are not zero current sources. When the I OCP , I OVP , and I ACL are not zero current sources, V G voltage is increased and the I OUT current is blocked or limited since the I SINK current is constant. In the normal operation mode of MF-LDO, the ISINK current discharges the VG node constantly. Also, the IFB current is generated by voltage feedback loop. Therefore, VOUT voltage is regulated constantly, and the VG voltage is changed depending on IOUT currents. In the protection modes of MF-LDO-such as OCP, OVP, or ACL modes-IOCP, IOVP, and IACL are not zero current sources. When the IOCP, IOVP, and IACL are not zero current sources, VG voltage is increased and the IOUT current is blocked or limited since the ISINK current is constant.  In order to prevent it, IOUT is limited by the ACL circuit. The input signals of control circuits are the VCOMM signal, the output signal (VIACL) of the current sensor, and references (REF1,2,3). The ACL is enabled by the VCOMM signal and the current limit level is determined depending on the voltage level of VIACL signal. When the VON is high, the parasitic gate capacitor (CG) of MP1 is charged by the limit level block through the diode, D4. Therefore, the voltage level of VG is increased, and the output current (IOUT) is limited.   (REF 1,2,3 ). The ACL is enabled by the V COMM signal and the current limit level is determined depending on the voltage level of V IACL signal. When the V ON is high, the parasitic gate capacitor (C G ) of M P1 is charged by the limit level block through the diode, D4. Therefore, the voltage level of V G is increased, and the output current (I OUT ) is limited. In the normal operation mode of MF-LDO, the ISINK current discharges the VG node constantly. Also, the IFB current is generated by voltage feedback loop. Therefore, VOUT voltage is regulated constantly, and the VG voltage is changed depending on IOUT currents. In the protection modes of MF-LDO-such as OCP, OVP, or ACL modes-IOCP, IOVP, and IACL are not zero current sources. When the IOCP, IOVP, and IACL are not zero current sources, VG voltage is increased and the IOUT current is blocked or limited since the ISINK current is constant.   (REF1,2,3). The ACL is enabled by the VCOMM signal and the current limit level is determined depending on the voltage level of VIACL signal. When the VON is high, the parasitic gate capacitor (CG) of MP1 is charged by the limit level block through the diode, D4. Therefore, the voltage level of VG is increased, and the output current (IOUT) is limited.

Experimental Results
The proposed WPR chip is fabricated in 0.18 µ m 1P4M with MIM capacitors and high sheet resistance poly resistors. Figure 9 shows the chip layout pattern of the WPR. The die area in the WPR is 16.0 mm 2 . The measurement environment of wireless power receiver is displayed in Figure 10. Inductive wireless power is generated by power transmitter. Below the receiver coil, a transmitter coil is placed.
The measured waveform of the active rectifier is revealed in Figure 11. The ZCS circuit operates the active rectifier. MHS1 and MLS1 start to be turned on at 10 mA current of IAC and are active during the interval time T1. On the other hand, MHS2 and MLS2 start to be turned on at −15 mA current of IAC and are active during the interval time T2.
The measured waveform of MF-LDO is shown in Figure 12

Experimental Results
The proposed WPR chip is fabricated in 0.18 µm 1P4M with MIM capacitors and high sheet resistance poly resistors. Figure 9 shows the chip layout pattern of the WPR. The die area in the WPR is 16.0 mm 2 .

Experimental Results
The proposed WPR chip is fabricated in 0.18 µ m 1P4M with MIM capacitors and high sheet resistance poly resistors. Figure 9 shows the chip layout pattern of the WPR. The die area in the WPR is 16.0 mm 2 . The measurement environment of wireless power receiver is displayed in Figure 10. Inductive wireless power is generated by power transmitter. Below the receiver coil, a transmitter coil is placed.
The measured waveform of the active rectifier is revealed in Figure 11. The ZCS circuit operates the active rectifier. MHS1 and MLS1 start to be turned on at 10 mA current of IAC and are active during the interval time T1. On the other hand, MHS2 and MLS2 start to be turned on at −15 mA current of IAC and are active during the interval time T2.
The measured waveform of MF-LDO is shown in Figure 12. The measurement environment of wireless power receiver is displayed in Figure 10. Inductive wireless power is generated by power transmitter. Below the receiver coil, a transmitter coil is placed.
The measured waveform of the active rectifier is revealed in Figure 11. The ZCS circuit operates the active rectifier. M HS1 and M LS1 start to be turned on at 10 mA current of IAC and are active during the interval time T1. On the other hand, M HS2 and M LS2 start to be turned on at −15 mA current of I AC and are active during the interval time T2.
The measured waveform of MF-LDO is shown in Figure 12. The value of load current (I OUT ) varies from 200 mA to 600 mA to check the performance of MF-LDO. When the MF-LDO is in the normal operation mode, VOUT is regulated to 5.0 V. On the other hand, when the ACL is enabled, I OUT is limited to 450 mA.   In Figure 13, the rectifier output voltage (VRECT) can change from 6 V to 8 V, whereas the variation of MF-LDO output voltage (VOUT) is less than 89 mV/A. For this measurement, VRECT is provided from the power supply.
When the value of load current is 800 mA in Figure 14, the maximum measured PCE of the active rectifier and wireless power receiver are 94.2% and 85.3%, respectively.   In Figure 13, the rectifier output voltage (VRECT) can change from 6 V to 8 V, whereas the variation of MF-LDO output voltage (VOUT) is less than 89 mV/A. For this measurement, VRECT is provided from the power supply.
When the value of load current is 800 mA in Figure 14, the maximum measured PCE of the active rectifier and wireless power receiver are 94.2% and 85.3%, respectively.   In Figure 13, the rectifier output voltage (VRECT) can change from 6 V to 8 V, whereas the variation of MF-LDO output voltage (VOUT) is less than 89 mV/A. For this measurement, VRECT is provided from the power supply.
When the value of load current is 800 mA in Figure 14, the maximum measured PCE of the active rectifier and wireless power receiver are 94.2% and 85.3%, respectively. In Figure 13, the rectifier output voltage (V RECT ) can change from 6 V to 8 V, whereas the variation of MF-LDO output voltage (V OUT ) is less than 89 mV/A. For this measurement, V RECT is provided from the power supply.
When the value of load current is 800 mA in Figure 14, the maximum measured PCE of the active rectifier and wireless power receiver are 94.2% and 85.3%, respectively.
The performance comparison with prior works is shown in Table 1 [8,17,18]. The examples from [8,17] are active rectifiers for A4WP standard operating at 6.78 MHz and their efficiencies are 91.5% and 94.2% respectively. The maximum efficiency of [18] is 92.7% when the input frequency is 150 kHz. Therefore, this work achieves an efficiency of 92.4% and has the best performance when the input frequency is 150 kHz. This work shows the highest overall efficiency of a rectifier compared with references. The performance comparison with prior works is shown in Table 1 [8,17,18]. The examples from [8,17] are active rectifiers for A4WP standard operating at 6.78 MHz and their efficiencies are 91.5% and 94.2% respectively. The maximum efficiency of [18] is 92.7% when the input frequency is 150 kHz. Therefore, this work achieves an efficiency of 92.4% and has the best performance when the input frequency is 150 kHz. This work shows the highest overall efficiency of a rectifier compared with references.   The performance comparison with prior works is shown in Table 1 [8,17,18]. The examples from [8,17] are active rectifiers for A4WP standard operating at 6.78 MHz and their efficiencies are 91.5% and 94.2% respectively. The maximum efficiency of [18] is 92.7% when the input frequency is 150 kHz. Therefore, this work achieves an efficiency of 92.4% and has the best performance when the input frequency is 150 kHz. This work shows the highest overall efficiency of a rectifier compared with references.

Conclusions
This work describes an inductive coupling (WPC/PMA) WPR having high-efficiency Active rectifier and MF-LDO Regulator. The synchronous Active rectifier with ZCS is proposed to get high efficiency in order to reduce the reverse leakage current. MF-LDO Regulator is proposed to implement the output voltage regulation, OVP, over current limit (OCL), and ACL sharing the single power transistor.
This chip is implemented in the 0.18 µm BCD technology having die area of 16.0 mm 2 . The maximum PCE of the Active rectifier is 94.2% at 800 mA load current.