Common Grounded H-Type Bidirectional DC-DC Converter with a Wide Voltage Conversion Ratio for a Hybrid Energy Storage System

: Hybrid energy storage systems (HESS) play an important role in maintaining the power balance of a direct current (DC) micro-grid. A HESS is mainly composed of high power density super-capacitors (SCs) and high energy density batteries. According to the operational requirements of an SC, a bidirectional DC-DC converter with the characteristics of a good dynamic response and a wide voltage conversion ratio is needed to interface the SC and a high-voltage DC bus. In this paper, a novel common grounded H-type bidirectional converter characterized by a good dynamic response, a low inductor current ripple, and a wide voltage conversion ratio is proposed. In addition, it can avoid the narrow pulse of pulse width modulation (PWM) voltage waveforms when a high voltage conversion ratio is achieved. All of these features are beneﬁcial to the operation of the SC connected to a DC bus. The operating principle and characteristics of the proposed converter are presented in this paper. A 320 W prototype with a wide voltage conversion ranging from 3.3 to 8 in step-up mode and 1/8 to 1/3 in step-down mode has been constructed to validate the feasibility and effectiveness of the proposed converter.


Introduction
With the high penetration of direct current (DC) energy sources, storage, and loads, DC micro-grids are becoming more prevalent due to a lower number of power converters compared with an alternating current (AC) micro-grid [1][2][3]. Because of the intermittent nature of renewable energy sources and unpredictable load fluctuations in DC micro-grids, the problem of power imbalance may appear and affect the operation of DC micro-grids. Therefore, energy storage systems (ESs) are always installed to maintain the power balance of the DC micro-grid [4,5]. ESs can be divided into a power density type and an energy density type based on their characteristics [6,7]. Unfortunately, there is no single type of ES that fulfills all expected features [8]. Therefore, it is an economic and effective solution to use a hybrid energy storage system (HESS) composed by different characteristics of ESs [9][10][11]. Generally, a HESS is mainly composed of high power density super-capacitors (SCs) and high energy density batteries. It is desirable to balance the steady-state power imbalance by the batteries and compensate for the transient power imbalance by an SC with fast dynamics [12][13][14]. As a result, the degradation impact on the batteries caused by sudden load changes can be greatly reduced, and the dynamic response of the whole DC micro-grid can also be improved [15,16].
As mentioned above, high power density SCs play an important role in a HESS. However, the output voltage of an SC is relatively low and changes widely. In order to connect the SC to a high voltage level DC bus and to achieve a bidirectional power flow for the SC, a wide voltage conversion

Configuration of the Proposed Converter
The configuration of the proposed converter is depicted in Figure 2. This converter is composed of a capacitor-clamped H-type structure (Q1-Q4 and C1), an inductor, a power switch Q5, and two filter capacitors Chigh and Clow. To simplify the analysis, it is assumed that the capacitors and inductor are large enough and all of the power semiconductors are ideal. In order to protect the SC, the proposed converter operates in the input current continuous model (CCM). Step-down Step-up

Step-Up Mode of the Proposed Converter
As shown in Figure 2, Ulow can be stepped-up to Uhigh by controlling the power semiconductors Q1, and Q2. The relationship between d1 and d2 can be written as d1 = d2 = dBoost, where d1 and d2 are the duty cycles of Q1 and Q2, respectively. The phase difference between the gate-driving signals S1 and S2 is 180°. During one switching period, the converter has three switching states, and their sequence is "10-00-01-00-10". Figure 3 shows the energy flow paths and Figure 4 shows the typical waveforms. Due to using the clamp capacitor C1, all of the power semiconductors turn on and off only once during each switching period. When S1S2 = 10: As shown in Figure 3a, where switch S1 is ON and S2 is OFF. The anti-parallel diodes of Q4 and Q5 are forward biased, while the anti-parallel diode of Q3 is reverse biased. The inductor L is charged from the input source. Current iL rises linearly. The load is supplied by C1 and Chigh. Clamp capacitor C1 maintains the forward bias of the anti-parallel diodes of Q5.

Configuration of the Proposed Converter
The configuration of the proposed converter is depicted in Figure 2. This converter is composed of a capacitor-clamped H-type structure (Q 1 -Q 4 and C 1 ), an inductor, a power switch Q 5 , and two filter capacitors C high and C low . To simplify the analysis, it is assumed that the capacitors and inductor are large enough and all of the power semiconductors are ideal. In order to protect the SC, the proposed converter operates in the input current continuous model (CCM).

Configuration of the Proposed Converter
The configuration of the proposed converter is depicted in Figure 2. This converter is composed of a capacitor-clamped H-type structure (Q1-Q4 and C1), an inductor, a power switch Q5, and two filter capacitors Chigh and Clow. To simplify the analysis, it is assumed that the capacitors and inductor are large enough and all of the power semiconductors are ideal. In order to protect the SC, the proposed converter operates in the input current continuous model (CCM). Step-down Step-up

Step-Up Mode of the Proposed Converter
As shown in Figure 2, Ulow can be stepped-up to Uhigh by controlling the power semiconductors Q1, and Q2. The relationship between d1 and d2 can be written as d1 = d2 = dBoost, where d1 and d2 are the duty cycles of Q1 and Q2, respectively. The phase difference between the gate-driving signals S1 and S2 is 180°. During one switching period, the converter has three switching states, and their sequence is "10-00-01-00-10". Figure 3 shows the energy flow paths and Figure 4 shows the typical waveforms. Due to using the clamp capacitor C1, all of the power semiconductors turn on and off only once during each switching period. When S1S2 = 10: As shown in Figure 3a, where switch S1 is ON and S2 is OFF. The anti-parallel diodes of Q4 and Q5 are forward biased, while the anti-parallel diode of Q3 is reverse biased. The inductor L is charged from the input source. Current iL rises linearly. The load is supplied by C1 and Chigh. Clamp capacitor C1 maintains the forward bias of the anti-parallel diodes of Q5.

2.2.1.
Step-Up Mode of the Proposed Converter As shown in Figure 2, U low can be stepped-up to U high by controlling the power semiconductors Q 1 , and Q 2 . The relationship between d 1 and d 2 can be written as d 1 = d 2 = d Boost , where d 1 and d 2 are the duty cycles of Q 1 and Q 2 , respectively. The phase difference between the gate-driving signals S 1 and S 2 is 180 • . During one switching period, the converter has three switching states, and their sequence is "10-00-01-00-10". Figure 3 shows the energy flow paths and Figure 4 shows the typical waveforms. Due to using the clamp capacitor C 1 , all of the power semiconductors turn on and off only once during each switching period.
When S 1 S 2 = 10: As shown in Figure 3a, where switch S 1 is ON and S 2 is OFF. The anti-parallel diodes of Q 4 and Q 5 are forward biased, while the anti-parallel diode of Q 3 is reverse biased. The inductor L is charged from the input source. Current i L rises linearly. The load is supplied by C 1 and C high . Clamp capacitor C 1 maintains the forward bias of the anti-parallel diodes of Q 5 . When S1S2 = 00: As shown in Figure 3b, both switches S1 and S2 are OFF. The anti-parallel diodes of Q3, Q4, and Q5 are forward biased. Capacitors C1 and Chigh are charged from L. The load is supplied by L. There is no energy exchange between capacitors C1 and Chigh.
When S1S2 = 01: As shown in Figure 3c, where switch S1 is OFF and S2 is ON. The anti-parallel diode of Q3 is forward biased, while the anti-parallel diodes of Q4 and Q5 are reverse biased. Inductor L is charged from the input source. Current iL rises linearly. The load is supplied by output capacitor Chigh. In this case, the voltage of capacitor C1 remains steady.
10 00 00 01 Figure 4. Typical waveforms of the proposed converter in the step-up mode.

2.2.2.
Step-Down Mode of the Proposed Converter As shown in Figure 2, Uhigh can be stepped down to Ulow by controlling the power semiconductors Q3, Q4, and Q5. The relationship between d3, d4, and d5 can be written as d3 = d4 = d5 = dBuck, where d3, d4, and d5 are the duty cycles of Q3, Q4, and Q5, respectively. The phase difference between the gate-driving signals S3 and S4 is 180°. The gate-driving signal S5 = S4. During one switching period, the converter has three switching states, and their sequence is "111-100-111-011-111". Figure 5 shows the energy flow paths and Figure 6 shows the typical waveforms. During each switching period, all of the power semiconductors also turn on and off once.
When S3S4S5 = 111: The switching state is shown in Figure 5a, where switches S3, S4, and S5 are ON. The anti-parallel diodes of Q1 and Q2 are forward biased. The high-voltage side Uhigh and capacitor C1 charge the inductor L, and simultaneously provide energy to the load in the low-voltage side. The current iL rises linearly.
When S3S4S5 = 100: The switching state is shown in Figure 5b, where switch S3 is ON and switches S4 and S5 are OFF. The anti-parallel diode of Q2 is forward biased, while the anti-parallel diode of Q1 is reverse biased. Inductor L provides energy to the load in the low-voltage side. The current iL decreases linearly.
When S3S4S5 = 011: The switching state is shown in Figure 5c, where switches S4 and S5 are ON and S3 is OFF. The anti-parallel diode of Q1 is forward biased, while the anti-parallel diode of Q2 is reverse biased. Inductor L provides energy to the load in the low-voltage side. The current iL decreases linearly. Capacitor C1 is charged by the high-voltage side Uhigh. The clamp capacitor C1 maintains the power switch Q5 ON.

2.2.2.
Step-Down Mode of the Proposed Converter As shown in Figure 2, U high can be stepped down to U low by controlling the power semiconductors Q 3 , Q 4 , and Q 5 . The relationship between d 3 , d 4 , and d 5 can be written as d 3 = d 4 = d 5 = d Buck , where d 3 , d 4 , and d 5 are the duty cycles of Q 3 , Q 4 , and Q 5 , respectively. The phase difference between the gate-driving signals S 3 and S 4 is 180 • . The gate-driving signal S 5 = S 4 . During one switching period, the converter has three switching states, and their sequence is "111-100-111-011-111". Figure 5 shows the energy flow paths and Figure 6 shows the typical waveforms. During each switching period, all of the power semiconductors also turn on and off once.
When S 3 S 4 S 5 = 111: The switching state is shown in Figure 5a, where switches S 3 , S 4 , and S 5 are ON. The anti-parallel diodes of Q 1 and Q 2 are forward biased. The high-voltage side U high and capacitor C 1 charge the inductor L, and simultaneously provide energy to the load in the low-voltage side. The current i L rises linearly.
When S 3 S 4 S 5 = 100: The switching state is shown in Figure 5b, where switch S 3 is ON and switches S 4 and S 5 are OFF. The anti-parallel diode of Q 2 is forward biased, while the anti-parallel diode of Q 1 is reverse biased. Inductor L provides energy to the load in the low-voltage side. The current i L decreases linearly.
When S 3 S 4 S 5 = 011: The switching state is shown in Figure 5c, where switches S 4 and S 5 are ON and S 3 is OFF. The anti-parallel diode of Q 1 is forward biased, while the anti-parallel diode of Q 2 is reverse biased. Inductor L provides energy to the load in the low-voltage side. The current i L decreases linearly. Capacitor C 1 is charged by the high-voltage side U high . The clamp capacitor C 1 maintains the power switch Q 5 ON.

Synchronous Rectification Mode of the Proposed Converter
The on-state resistance of the power switch is lower than its corresponding anti-parallel diode. As mentioned above, current flow into the corresponding anti-parallel diodes of the slave power switches will result in higher conduction losses and lower efficiency. In order to improve the efficiency, the proposed converter uses synchronous rectifier technology [33,34].
The synchronous rectification operation principle of the proposed converter is shown in Figure 7. Figure 7a shows the gate signals of S1-S5 in step-up mode and Figure 7b shows the gate signals of S1-S5 in step-down mode. In step-up mode, the current has to fully flow into the corresponding antiparallel diodes of the slave power switches Q3, Q4, and Q5 at the dead time td. When the slave power switches are ON, the current almost flows into the MOSFETS due to their lower on-resistance as shown in Figure 7c. In step-down mode, the current flow path is the same as with the step-up mode as shown in Figure 7d. The only difference is that the slave power switches are Q1 and Q2.
When the current flows into the corresponding anti-parallel diodes of the slave power switches at dead time, the forward voltage drops of the anti-parallel diodes are close to zero. As a result, the slave active power switches turn on and turn off with zero voltage. The turn on/off losses of the slave active power switches will not be increased and the efficiency of the converter can be improved.

Synchronous Rectification Mode of the Proposed Converter
The on-state resistance of the power switch is lower than its corresponding anti-parallel diode. As mentioned above, current flow into the corresponding anti-parallel diodes of the slave power switches will result in higher conduction losses and lower efficiency. In order to improve the efficiency, the proposed converter uses synchronous rectifier technology [33,34].
The synchronous rectification operation principle of the proposed converter is shown in Figure 7. Figure 7a shows the gate signals of S 1 -S 5 in step-up mode and Figure 7b shows the gate signals of S 1 -S 5 in step-down mode. In step-up mode, the current has to fully flow into the corresponding anti-parallel diodes of the slave power switches Q 3 , Q 4 , and Q 5 at the dead time t d . When the slave power switches are ON, the current almost flows into the MOSFETS due to their lower on-resistance as shown in Figure 7c. In step-down mode, the current flow path is the same as with the step-up mode as shown in Figure 7d. The only difference is that the slave power switches are Q 1 and Q 2 .
When the current flows into the corresponding anti-parallel diodes of the slave power switches at dead time, the forward voltage drops of the anti-parallel diodes are close to zero. As a result, the slave active power switches turn on and turn off with zero voltage. The turn on/off losses of the slave active power switches will not be increased and the efficiency of the converter can be improved. Energies 2018, 11, x FOR PEER REVIEW 8 of 22

Control Strategy for Bidirectional Power Flow
For a HESS, the SC interface converter should be able to respond to fast bidirectional power fluctuations immediately. Therefore, a virtual capacitor droop (VCD) control is adopted for this converter. At the same time, the battery interface converter uses a virtual resistance droop (VRD) control to make the battery provide total power at steady state. Due to using the VCD and VCR control, the HESS can adapt to the distributed nature of the DC micro-grid and increase system reliability and scalability [35,36]. The specific control strategy is shown in Figure 8. As shown in Figure 8, the voltage controller is used to follow the reference voltage Uref. The voltage Uhigh and the currents ihigh-sc and ihigh-bat are obtained by the sensor samplings. ihigh-sc refers to the output current of the SC interface converter and ihigh-bat refers to the output current of the battery interface converter.

PWM Generator
The proposed Converter DC bus Voltage Controller d S1~S5

Control Strategy for Bidirectional Power Flow
For a HESS, the SC interface converter should be able to respond to fast bidirectional power fluctuations immediately. Therefore, a virtual capacitor droop (VCD) control is adopted for this converter. At the same time, the battery interface converter uses a virtual resistance droop (VRD) control to make the battery provide total power at steady state. Due to using the VCD and VCR control, the HESS can adapt to the distributed nature of the DC micro-grid and increase system reliability and scalability [35,36]. The specific control strategy is shown in Figure 8. As shown in Figure 8, the voltage controller is used to follow the reference voltage U ref . The voltage U high and the currents i high-sc and i high-bat are obtained by the sensor samplings. i high-sc refers to the output current of the SC interface converter and i high-bat refers to the output current of the battery interface converter.

Control Strategy for Bidirectional Power Flow
For a HESS, the SC interface converter should be able to respond to fast bidirectional power fluctuations immediately. Therefore, a virtual capacitor droop (VCD) control is adopted for this converter. At the same time, the battery interface converter uses a virtual resistance droop (VRD) control to make the battery provide total power at steady state. Due to using the VCD and VCR control, the HESS can adapt to the distributed nature of the DC micro-grid and increase system reliability and scalability [35,36]. The specific control strategy is shown in Figure 8. As shown in Figure 8, the voltage controller is used to follow the reference voltage Uref. The voltage Uhigh and the currents ihigh-sc and ihigh-bat are obtained by the sensor samplings. ihigh-sc refers to the output current of the SC interface converter and ihigh-bat refers to the output current of the battery interface converter.    The operation modes of the proposed converter switch between the step-down and step-up modes according to the necessary conditions of a general load. The current relationship at the DC bus is expressed as where iHESS is the equivalent load current of the HESS and can be either positive or negative. The output voltage-current (V-I) relationship of the battery interface converter under the VRD control and that of the SC interface converter under the VCD control are given by where Rvb is the virtual resistance and Cvc is the virtual capacitance. Based on (1) and (2), the currentsharing relationship between battery and SC is derived as high-bat HESS vb vc vb vc high-sc HESS vb vc 1 1 (3)

Voltage Conversion Ratio in Step-Up Mode
For the proposed converter shown in Figure 2, the voltage conversion ratio can be derived from the volt-sec balance of the inductor L. According to Figure 3a, Q4 and Q5 are ON, so that the voltages of C1 and Chigh are equal. In the low-voltage side current continuous model, the equations can be obtained as follows: where UC1 is the voltage over C1. By simplifying (1), the following equation can be derived: The voltage conversion ratio MBoost of the proposed converter is The operation modes of the proposed converter switch between the step-down and step-up modes according to the necessary conditions of a general load. The current relationship at the DC bus is expressed as where i HESS is the equivalent load current of the HESS and can be either positive or negative. The output voltage-current (V-I) relationship of the battery interface converter under the VRD control and that of the SC interface converter under the VCD control are given by where R vb is the virtual resistance and C vc is the virtual capacitance. Based on (1) and (2), the currentsharing relationship between battery and SC is derived as

Voltage Conversion Ratio in Step-Up Mode
For the proposed converter shown in Figure 2, the voltage conversion ratio can be derived from the volt-sec balance of the inductor L. According to Figure 3a, Q 4 and Q 5 are ON, so that the voltages of C 1 and C high are equal. In the low-voltage side current continuous model, the equations can be obtained as follows: where U C1 is the voltage over C 1 . By simplifying (1), the following equation can be derived: The voltage conversion ratio M Boost of the proposed converter is where 0 < d Boost < 0.5.

Voltage Conversion Ratio in
Step-Down Mode According to Figure 5c, the power switches Q 4 and Q 5 are ON, so that the voltages of C 1 and C high are equal. By applying the volt-second balance principle on L, the voltage conversion ratio in CCM can be obtained as By simplifying (7), the following equation can be derived: The voltage conversion ratio M Buck in step-down mode is Under the same voltage conversion ratio, 0 shows the comparison between the proposed and the traditional two-level bidirectional converters. According to Figure 9, when the voltage conversion ratio is 8 in the step-up mode, the duty cycles of the proposed and the traditional converters are 0.4375 and 0.875, respectively; in step-down mode, when the voltage conversion ratio is 0.125, the duty cycles of the proposed and the traditional converters are 0.5625 and 0.125, respectively. Compared with the traditional converter, the proposed one can avoid the extreme duty cycle while achieving a high voltage conversion ratio. What is more, the higher the voltage conversion ratio, the closer the duty cycle is to 0.5. When the duty cycle approaches 0.5, the time used to maintain the ON and OFF state for all power semiconductors is nearly equal in each period, which is beneficial to avoid the narrow pulse of PWM voltage waveforms while the high voltage conversion ratio is achieved.

Voltage Conversion Ratio in
Step-Down Mode According to Figure 5c, the power switches Q4 and Q5 are ON, so that the voltages of C1 and Chigh are equal. By applying the volt-second balance principle on L, the voltage conversion ratio in CCM can be obtained as By simplifying (7), the following equation can be derived: where 0.5 < dBuck < 1.
Under the same voltage conversion ratio, 0 shows the comparison between the proposed and the traditional two-level bidirectional converters. According to Figure 9, when the voltage conversion ratio is 8 in the step-up mode, the duty cycles of the proposed and the traditional converters are 0.4375 and 0.875, respectively; in step-down mode, when the voltage conversion ratio is 0.125, the duty cycles of the proposed and the traditional converters are 0.5625 and 0.125, respectively. Compared with the traditional converter, the proposed one can avoid the extreme duty cycle while achieving a high voltage conversion ratio. What is more, the higher the voltage conversion ratio, the closer the duty cycle is to 0.5. When the duty cycle approaches 0.5, the time used to maintain the ON and OFF state for all power semiconductors is nearly equal in each period, which is beneficial to avoid the narrow pulse of PWM voltage waveforms while the high voltage conversion ratio is achieved. Step-down mode. Step-down mode. The average inductor current can be derived from the ampere-second balance of the capacitors C 1 and C high in CCM.
where I C1a and I C1b are the average currents across C 1 in state 10 and 00, respectively. It follows from (10) that the average inductor current I L can be obtained as follows: In the state 10, the inductor current increases linearly, and (12) can be obtained as where f is the switching frequency and ∆i L is the inductor current ripple. It follows from (11) and (12) that the current ripple ratio r Boost of the inductor can be obtained as where R high is the equivalent load of the high-voltage side.

The Average Inductor Current and Inductor Current Ripple in
Step-Down Mode The average inductor current I L can be obtained as follows: In the state 100, the inductor current decreases linearly, and (15) can be obtained as It follows from (14) and (15) that the current ripple ratio r Buck of the inductor can be obtained as follows: where R low is the equivalent load of the low-voltage side. The inductor current ripple ratios of a traditional two-level bidirectional converter are: where d Boost and d Buck are the duty cycles of that converter in step-up and step-down mode, respectively. r Boost and r Buck are the current ripple ratios of that converter in step-up and step-down mode, respectively. Supposing that the output power, inductor, and switching frequency of the proposed converter and the traditional two-level converter are equal, it can be obtained that It can be concluded from (18) that the inductor current ripple ratio in the proposed converter is lower than that in the traditional two-level converter. On the other hand, if the inductor current ripple ratios are equal, the inductor of the proposed converter is only half that of the traditional one, which means that the proposed converter has outstanding dynamic response.

Good Dynamic Performance
The proposed converter can work in both the step-up and step-down modes. In order to save paper space, only the dynamic performance in step-down mode is analyzed. Before analyzing the dynamic performance, a small-signal model of step-down mode is needed.
When the proposed converter operates in the range 0.5 < d Buck < 1, the main power switches Q 3 , Q 4 , and Q 5 have three effective switching states: S 3 S 4 S 5 = [111, 100, 011]. u high , u low , and d Buck are the input, the output, and the control variables, respectively. i L , u C1 , and u Clow are the state variables. r is the equivalent series resistance for C 1 .
When S 3 S 4 S 5 = 111, the operating time of the proposed converter is (2d Buck − 1) × T. The state space average model in this operating time is When S 3 S 4 S 5 = 100, the operating time of the proposed converter is (1 − d Buck ) × T. The state space average model in this operating time is When S 3 S 4 S 5 = 011, the operating time of the proposed converter is (1 − d Buck ) × T. The state space average model in this operating time is Energies Combining (19) and (20) with (21), the average model of the proposed converter is The state, the input, the output, and the control variables can be described by using the small-signal disturbance variables as: where I L , U C1 , U Clow , U low , U high , and D Buck are steady state components, andî L ,û C1 ,û Clow ,û low , andd Buck are their corresponding small-signal disturbance variables.
As a result, the small-signal model of the proposed converter is Using the parameters shown in Table 1, when the output voltage is 25 V, the control-to-output transfer function can be expressed as .52 × 10 7 s + 1.5 × 10 13 s 3 + 3.32 × 10 5 s 2 + 2.55 × 10 8 s + 7.52 × 10 12 .
Assume that the proposed converter and the traditional two-level converter have the same output power, inductor current ripple ratio, and switching frequency. Then, the inductor of the traditional two-level converter is double that of the proposed converter. The control-to-output transfer function of the traditional two-level converter in step-down mode can be expressed as The Bode diagram of the duty cycle to output voltage open-loop transfer function is shown in Figure 10. According to Figure 10, the crossover frequency of the proposed converter is higher than that of the traditional two-level converter due to smaller inductance.
The Bode diagram of the duty cycle to output voltage open-loop transfer function is shown in Figure 10. According to Figure 10, the crossover frequency of the proposed converter is higher than that of the traditional two-level converter due to smaller inductance. The switching frequency of the traditional two-level converter can be chosen to be five times the crossover frequency. At this point, the equivalent switching frequency of the proposed converter is twice that of the switching frequency. The side-band effect has been eliminated due to interleave The switching frequency of the traditional two-level converter can be chosen to be five times the crossover frequency. At this point, the equivalent switching frequency of the proposed converter is twice that of the switching frequency. The side-band effect has been eliminated due to interleave control. Therefore, the crossover frequency of the proposed converter can be increased to two-fifths of f. It means that the proposed converter can push to a higher control bandwidth, which leads to better dynamic performance.
In step-up mode, small inductance and a higher equivalent switching frequency lead to better dynamic performance too.
The control-to-output transfer function derived above is helpful to design the voltage controller shown in Figure 8. The voltage controller is a PI (proportional integral) regulator and it can be expressed as Using the control-to-output transfer function, k p and k i can be deduced. Due to the use of the capacitor-clamped H-type structure, the proposed converter has the following advantages:

•
Avoiding the narrow pulse of PWM voltage waveforms when a high voltage conversion ratio is achieved: It costs a little time to turn a power semiconductor on and off, thus the ideal narrow pulse of the PWM voltage waveform is difficult to realize. The higher the voltage conversion ratio of the proposed converter is, the closer the duty cycle is to 0.5. When the duty cycle approaches 0.5, the time used to maintain the ON and OFF state for all power semiconductors is nearly equal in each period, which is beneficial to avoid the narrow pulse of PWM voltage waveforms while a high voltage conversion ratio is achieved.

•
Reducing inductor current ripple: The inductor L is charged and discharged twice during each switching period, as 0 and 0 show. With a small duty cycle in step-up mode, the charging time of the inductor is short. The charging time of the inductor in step-down mode is short too. Then, the inductor current ripple will decrease. • Good dynamic performance: Due to using small inductance and a higher equivalent switching frequency, the proposed converter has a better dynamic performance.

Voltage and Current Stress on the Power Switches
According to the current flow path of the proposed converter in step-up mode, as shown in 0 (or the current-flow path of the step-down mode, as shown in Figure 5), using the KVL (Kirchhoff's voltage law), the voltage stress on Q 1 -Q 5 in the step-up and the step-down modes can be obtained as The voltage stress on Q 1 -Q 5 in the step-up and step-down modes is the same.
Similarly, according to current-flow path in step-up mode, as shown in Figure 3 (or the current-flow path in step-down mode, as shown in Figure 5), and the KCL (Kirchhoff's current law), the current stress (namely average currents when the switch is ON) on Q 1 -Q 5 in the step-up and the step-down modes can be obtained as (29) The current stress on Q 1 -Q 5 in the step-up and step-down modes is also identical.

Experimental Result and Analyses
In order to verify the feasibility of the theoretical analysis, an experimental prototype with the parameters shown in Table 1 has been developed.

Experimental Results in the Step-Up Mode
The PWM voltages of power semiconductors and the inductor current waveforms are shown in Figures 11 and 12. The PWM voltage of each power semiconductor is about 200 V, approximately equal to the high-voltage side U high , which validates the analysis in Section 3. According to Figures 11 and 12, the voltage gain M Boost of the proposed converter is 8 and the duty cycle d Boost is about 0.44. The ON state time of the power switches Q 1 -Q 2 is about 0.44 T and the ON state time of the power switches Q 3 -Q 5 is about 0.56 T. At that high voltage gain, both the ON and OFF state times of those power switches are close to 0.5 T, which is effective for avoiding the narrow pulse of the PWM voltage waveforms. Due to using the synchronous rectification, the turn on and turn off of the controlled MOSFETs Q 3 , Q 4 , and Q 5 realize the ZVS (zero voltage switching), e.g., the gate signal S 4 and the voltage stress of Q 4 as shown in Figure 13. According to Figure 11, the inductor L is charged and discharged twice during each switching period. Therefore, the equivalent switching frequency of the proposed converter is double that of the real switching frequency f. This feature is beneficial to improve the dynamic performance and reduce the inductor current ripple of this converter.
waveforms. Due to using the synchronous rectification, the turn on and turn off of the controlled MOSFETs Q3, Q4, and Q5 realize the ZVS (zero voltage switching), e.g., the gate signal S4 and the voltage stress of Q4 as shown in Figure 13. According to Figure 11, the inductor L is charged and discharged twice during each switching period. Therefore, the equivalent switching frequency of the proposed converter is double that of the real switching frequency f. This feature is beneficial to improve the dynamic performance and reduce the inductor current ripple of this converter.  waveforms. Due to using the synchronous rectification, the turn on and turn off of the controlled MOSFETs Q3, Q4, and Q5 realize the ZVS (zero voltage switching), e.g., the gate signal S4 and the voltage stress of Q4 as shown in Figure 13. According to Figure 11, the inductor L is charged and discharged twice during each switching period. Therefore, the equivalent switching frequency of the proposed converter is double that of the real switching frequency f. This feature is beneficial to improve the dynamic performance and reduce the inductor current ripple of this converter.
Charging and discharging twice T t (10µs /div) Figure 11. PWM voltage of power semiconductor Q1 and inductor current iL.  The voltage across clamp capacitor C1 is approximately 200 V, being well-consistent with Uhigh as shown in Figure 14. Therefore, in the switching state 01, the clamp capacitor C1 can maintain the forward bias of the anti-parallel diode of Q5. The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is beneficial to avoid narrow pulses of the PWM voltage waveform at high voltage gain. The voltage across clamp capacitor C 1 is approximately 200 V, being well-consistent with U high as shown in Figure 14. Therefore, in the switching state 01, the clamp capacitor C 1 can maintain the forward bias of the anti-parallel diode of Q 5 . The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is beneficial to avoid narrow pulses of the PWM voltage waveform at high voltage gain.
The voltage across clamp capacitor C1 is approximately 200 V, being well-consistent with Uhigh as shown in Figure 14. Therefore, in the switching state 01, the clamp capacitor C1 can maintain the forward bias of the anti-parallel diode of Q5. The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is beneficial to avoid narrow pulses of the PWM voltage waveform at high voltage gain. In the step-up mode, Ulow and Uhigh are the input and output voltage, respectively. The output voltage can stay around the reference value of 200 V. The output/input voltage waveforms shown in Figure 15 can be obtained when changing the input voltage dynamically. According to Figure 15, when the input voltage varies continuously from 25 V to 60 V, the output voltage can stay around 200 V. The conclusion can be obtained from Figure 15 that the proposed converter can obtain a wide voltage conversion ratio from 3.3 to 8 in step-up mode. In the step-up mode, U low and U high are the input and output voltage, respectively. The output voltage can stay around the reference value of 200 V. The output/input voltage waveforms shown in Figure 15 can be obtained when changing the input voltage dynamically. According to Figure 15, when the input voltage varies continuously from 25 V to 60 V, the output voltage can stay around 200 V. The conclusion can be obtained from Figure 15 that the proposed converter can obtain a wide voltage conversion ratio from 3.3 to 8 in step-up mode.
The voltage across clamp capacitor C1 is approximately 200 V, being well-consistent with Uhigh as shown in Figure 14. Therefore, in the switching state 01, the clamp capacitor C1 can maintain the forward bias of the anti-parallel diode of Q5. The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is beneficial to avoid narrow pulses of the PWM voltage waveform at high voltage gain.  At that high voltage conversion ratio, both the ON and OFF state times of those power switches are close to 0.5 T, which is effective for avoiding the narrow pulse of the PWM voltage waveforms. In addition, the slave power semiconductors Q 1 and Q 2 also acted in the synchronous rectification operation, which turned on and turned off with ZVS, e.g., the gate signal S 1 and the voltage stress of Q 1 , as shown in Figure 18. According to Figure 16, the inductor L is also charged and discharged twice during each switching period. The dynamic performance of the proposed converter in step-down mode is also improved.

Experimental Results in the Step-Down Mode
According to Figure 19, the voltage across clamp capacitor C 1 is approximately 200 V, being wellconsistent with U high . Therefore, in the switching state 011, the clamp capacitor C 1 can maintain the power switch Q 5 ON. The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is also beneficial to avoid narrow pulses of the PWM voltage waveform at a high voltage conversion ratio, just like in step-up mode.
that high voltage conversion ratio, both the ON and OFF state times of those power switches are close to 0.5 T, which is effective for avoiding the narrow pulse of the PWM voltage waveforms. In addition, the slave power semiconductors Q1 and Q2 also acted in the synchronous rectification operation, which turned on and turned off with ZVS, e.g., the gate signal S1 and the voltage stress of Q1, as shown in Figure 18. According to Figure 16, the inductor L is also charged and discharged twice during each switching period. The dynamic performance of the proposed converter in step-down mode is also improved.
According to Figure 19, the voltage across clamp capacitor C1 is approximately 200 V, being wellconsistent with Uhigh. Therefore, in the switching state 011, the clamp capacitor C1 can maintain the power switch Q5 ON. The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is also beneficial to avoid narrow pulses of the PWM voltage waveform at a high voltage conversion ratio, just like in step-up mode.  to 0.5 T, which is effective for avoiding the narrow pulse of the PWM voltage waveforms. In addition, the slave power semiconductors Q1 and Q2 also acted in the synchronous rectification operation, which turned on and turned off with ZVS, e.g., the gate signal S1 and the voltage stress of Q1, as shown in Figure 18. According to Figure 16, the inductor L is also charged and discharged twice during each switching period. The dynamic performance of the proposed converter in step-down mode is also improved. According to Figure 19, the voltage across clamp capacitor C1 is approximately 200 V, being wellconsistent with Uhigh. Therefore, in the switching state 011, the clamp capacitor C1 can maintain the power switch Q5 ON. The feature that all power semiconductors turn on and off only once during each switching period can be achieved. This is also beneficial to avoid narrow pulses of the PWM voltage waveform at a high voltage conversion ratio, just like in step-up mode.

Bidirectional Power Flow Experiment
In order to verify the performance of the proposed converter in a HESS, the related experiments are carried out using the HESS shown in Figure 1. The output voltages of the SC and battery are about 42 V and 50 V, respectively, and the DC load power varies with a step change between 400 W and 650 W. The proposed converter is used as the power interface between the SC and the DC bus.
With the DC load being suddenly increased and decreased, changes in the output currents are shown in Figure 21, where i bat and i sc denote the output currents of the battery and the SC, respectively. When the DC load required power changes from 400 W to 650 W suddenly, the SC compensates for the required power immediately by increasing the current i sc from 0 to 6 A in 20 ms approximately, which protects the battery by avoiding a sudden change in current and prolongs its life. Gradually, the task of supplying the power shortage is transferred from the SC to the battery. The i sc falls to 0 from 6 A along with the i bat rising from 8 A to 13 A. Similarly, when the DC load required power changes from 650 W to 400 W suddenly, the current i sc varies from 0 to −6 A in 20 ms approximately. As a result, the current from the battery decreases from 13 A to 8 A gradually, and the current of the SC returns to 0 from −6 A. When the DC load required power suddenly increases or decreases, the SC can respond quickly to compensate for the power gap between the battery and the DC load. In this situation, the service life of the battery is extended because of the slow changes in its output current. It can be concluded from Figure 21 that the proposed converter can cooperate well in the HESS whether the load is suddenly changed or not.
compensates for the required power immediately by increasing the current isc from 0 to 6 A in 20 ms approximately, which protects the battery by avoiding a sudden change in current and prolongs its life. Gradually, the task of supplying the power shortage is transferred from the SC to the battery. The isc falls to 0 from 6 A along with the ibat rising from 8 A to 13 A. Similarly, when the DC load required power changes from 650 W to 400 W suddenly, the current isc varies from 0 to −6 A in 20 ms approximately. As a result, the current from the battery decreases from 13 A to 8 A gradually, and the current of the SC returns to 0 from −6 A. When the DC load required power suddenly increases or decreases, the SC can respond quickly to compensate for the power gap between the battery and the DC load. In this situation, the service life of the battery is extended because of the slow changes in its output current. It can be concluded from Figure 21 that the proposed converter can cooperate well in the HESS whether the load is suddenly changed or not. The efficiencies of the proposed converter in the step-up and step-down modes are shown in Figure 22. In step-up mode, Uhigh is 200 V and Ulow varies from 25 V to 60 V continuously; in stepdown mode, Ulow is 25 V and Uhigh varies from 80 V to 200 V continuously. According to Figure 22, the efficiency varies from 91.52% to 94.80% in step-up mode, which is slightly lower than that in the step-down mode (varies from 92.01% to 95.30%). With the constant load power in step-up mode, the efficiency decreases accompanied by the input voltage declining due to the increasing losses caused by the growing input current. In the step-down mode, the efficiency decreases with the increase of high side voltages. Due to the increase in the high side voltages, the voltage stresses of the power semiconductors increase. Therefore, the turn on/off losses of the power semiconductors will increase. The efficiencies of the proposed converter in the step-up and step-down modes are shown in Figure 22. In step-up mode, U high is 200 V and U low varies from 25 V to 60 V continuously; in step-down mode, U low is 25 V and U high varies from 80 V to 200 V continuously. According to Figure 22, the efficiency varies from 91.52% to 94.80% in step-up mode, which is slightly lower than that in the step-down mode (varies from 92.01% to 95.30%). With the constant load power in step-up mode, the efficiency decreases accompanied by the input voltage declining due to the increasing losses caused by the growing input current. In the step-down mode, the efficiency decreases with the increase of high side voltages. Due to the increase in the high side voltages, the voltage stresses of the power semiconductors increase. Therefore, the turn on/off losses of the power semiconductors will increase. Step up Step down Step-down mode.

Conclusions
A new common grounded H-type bidirectional converter was proposed in this paper. It has the advantages of a wide voltage conversion ratio and a good dynamic response in both step-down and step-up operation modes. In addition, only one inductor is used in this converter, and the inductor is charged and discharged twice during each switching period, which results in a low inductor current ripple and a small size for this converter. Due to the use of a capacitor-clamped H-type structure, the proposed converter can avoid the narrow pulse of the PWM voltage waveforms while achieving a high voltage conversion ratio. Besides, the efficiency of the converter is improved because the slave active power switches turn on and turn off with zero voltage. In order to prove the feasibility, the proposed converter was implemented in the laboratory with the proper voltage conversion ratio (3.3-8 in step-up mode and 1/8-1/3 in step-down mode). A theoretical analysis and experimental results proved Step-down mode.

Conclusions
A new common grounded H-type bidirectional converter was proposed in this paper. It has the advantages of a wide voltage conversion ratio and a good dynamic response in both step-down and step-up operation modes. In addition, only one inductor is used in this converter, and the inductor is charged and discharged twice during each switching period, which results in a low inductor current ripple and a small size for this converter. Due to the use of a capacitor-clamped H-type structure, the proposed converter can avoid the narrow pulse of the PWM voltage waveforms while achieving a high voltage conversion ratio. Besides, the efficiency of the converter is improved because the slave active power switches turn on and turn off with zero voltage. In order to prove the feasibility, the proposed converter was implemented in the laboratory with the proper voltage conversion ratio (3.3-8 in step-up mode and 1/8-1/3 in step-down mode). A theoretical analysis and experimental results proved that the proposed converter is suitable for connecting a low-voltage SC to a high-voltage DC bus.