Coordination Control Method Suitable for Practical Engineering Applications for Distributed Power Flow Controller (DPFC)

: To control multiple series units of distributed power ﬂow controller (DPFC), a hierarchical control method is proposed. This coordination control system consists of a coordination controller and multiple series unit controllers. According to the demand of power ﬂow ordered by a dispatch center, the corresponding series-compensated voltage is calculated by a high-level controller and transferred to each series unit controller. Comparing the targeted compensated voltage with actual injected voltage, the modulation signal of the converter will be modiﬁed to change the power ﬂow accurately. The DPFC system model is built in Power Systems Computer Aided Design/ Electromagnetic Transients including DC (PSCAD/EMTDC). The simulation result indicates that the proposed hierarchical control method is effective and can be considered as an option for practical engineering applications in the future. ADC: analog-to-digital converter. SPWM: sinusoidal pulse-width modulation (PWM).


Introduction
The mechanically controlled AC power transmission systems, including the use of high-power electronics, advanced control centers, and communication links, were proposed in 1986 by N.G. Hingorani from American Electric Power Research Institute (EPRI) [1][2][3]. For a simple flexible AC transmission system (FACTS) parallel device or a simple FACTS series device, only the reactive power can be exchanged if the energy storage unit is not disposed on the DC capacitor side within the FACTS device. That is, its effect is equivalent to a tunable inductor or an adjustable capacitor. As a consequence, it is limited and not flexible enough for regulating the power flow of the transmission line.
The conception of a unified power-flow controller (UPFC) was proposed in 1991 by Dr. L. Gyugyi [4,5] and has been extensively studied to date [6][7][8][9][10][11]. The UPFC can be regarded as the combination of shunt and series FACTS linked by a common DC. Generally, the shunt device is a static synchronous compensator (STATCOM), while the series device is an example of a static synchronous series compensator (SSSC). Bidirectional active power can flow between the parallel and series units via the DC-bus capacitor to realize 'four quadric' power-flow regulation. Additionally, the active power flow and reactive power flow of the transmission line can be controlled independently, which matches its "universal" mind for control. However, the parallel and series units of UPFC are installed centrally; as a consequence, many land resources are required for the installation. The series side is integrated into one unit, which causes a large fold line change in the voltage distribution of the transmission line. Besides this, the requirement for the insulation is high due to the direct electrical connection of the parallel and series units. The aforementioned factors have led research workers to rethink UPFC from the aspects of project cost, ease of operation and maintenance.
A parallel FACTS device and many distributed series FACTS devices constitute a DPFC. The structure of a DPFC is shown in Figure 1. In the following, the parallel FACTS device is called a parallel unit while the series FACTS devices are called series units. The parallel unit is located at the sending end of the transmission line, and series units are distributed along the transmission line. As shown in Figure 1, T1 and T2 are delta-wye grounded transformers The delta side of the transformer is blocked for the third harmonic current while the wye grounded side is allowed for flowing 3rd harmonic current; thus, the energy channel of third harmonic active power is formed, which makes the active power exchange between the parallel unit and series units of the DPFC possible.
The parallel unit of the DPFC is composed of two back-to-back voltage source converters (VSCs). VSC1 is a three-phase converter which is responsible for maintaining the bus voltage and keeping the DC capacitor voltage stable. VSC2 is a single-phase converter, which is used to generate a constant third harmonic current. Thus, the parallel unit of the DPFC plays the role of absorbing the active power from the bus, and then converting it to the third harmonic active power. The third harmonic active power is injected into the transmission line and taken in by the DPFC series units as active power support. After that, the base-frequency active power is generated by the power exchange control in the series units.
In Figure 1  As shown in Figure 1, T1 and T2 are delta-wye grounded transformers The delta side of the transformer is blocked for the third harmonic current while the wye grounded side is allowed for flowing 3rd harmonic current; thus, the energy channel of third harmonic active power is formed, which makes the active power exchange between the parallel unit and series units of the DPFC possible.
The parallel unit of the DPFC is composed of two back-to-back voltage source converters (VSCs). VSC1 is a three-phase converter which is responsible for maintaining the bus voltage and keeping the DC capacitor voltage stable. VSC2 is a single-phase converter, which is used to generate a constant third harmonic current. Thus, the parallel unit of the DPFC plays the role of absorbing the active power from the bus, and then converting it to the third harmonic active power. The third harmonic active power is injected into the transmission line and taken in by the DPFC series units as active power support. After that, the base-frequency active power is generated by the power exchange control in the series units.
In Figure 1, • V 1 and • V 2 represent the voltage at the sending-end and receiving-end of the transmission line, respectively.
• I 3 is the equivalent third harmonic current. P 1 , Q 1 , P 2 , and Q 2 indicate the power flow at the sending-end and receiving-end of the transmission line, respectively.
Each DPFC series unit generates a compensated voltage   • V 2 . X Σ = X T1 + X line + X T2 denotes the total impedance of the AC transmission power system, where X T1 and X T2 represent the impedance of the transformer T1 and T2, respectively. Thus, the natural power flow of the transmission line is expressed as With DPFC series units, the power flow becomes • V 1 and • V 2 can be regarded as constant during a certain period of time in the actual power system operation, and so the increment of active and reactive power flow at the receiving-end can be written as follows: Based on the above equations, it is obvious that the power flow of the transmission line can be controlled efficiently by changing the magnitude value and phase angle of the series-compensated voltage slightly and flexibly.

Coordination Control System of a DPFC
The proposed coordination control system of a DPFC consists of an upper-level controller, a parallel unit controller and multiple series unit controllers. The schematic diagram of this control system is depicted in Figure 3.
In Figure 3, E dcsh_ref is the reference value of the DC capacitor voltage in the parallel unit while I 3_ref indicates the referenced third harmonic frequency. The control method for the parallel unit can be found in [20][21][22]; thus, the control scheme of the coordination control method for the series unit is mainly discussed in this research work. be found in [20][21][22]; thus, the control scheme of the coordination control method for the series unit is mainly discussed in this research work. Figure 3. The structure of the coordination control system of a DPFC.

The Computation of Reference Compensated Voltage
According to the demand of power flow set P and set Q ordered by the dispatch center, and the states of transmission line • Setting the number of DPFC series units to be n, the total base-frequency impedance between the sending-end and receiving-end of the power transmission system is 0 Z , the short circuit reactance of each series unit is Tse X , and the initial current phasor of transmission line is

The Computation of Reference Compensated Voltage
According to the demand of power flow P set and Q set ordered by the dispatch center, and the states of transmission line • Setting the number of DPFC series units to be n, the total base-frequency impedance between the sending-end and receiving-end of the power transmission system is Z 0 , the short circuit reactance of each series unit is X Tse , and the initial current phasor of transmission line is • Corresponding to the target power flow, I set and α represent the RMS value of • The corresponding series-compensated voltage generated by each DPFC series unit is V se_ref can be regarded as an equivalent series impedance Z set injected by each series unit. Then, another expression of the transmission line is According to the obvious assumption and analysis, the series-compensated voltage is • At the initial stable state t = t 0 , the phase angle that

The Control Scheme of DPFC Series Units
The structure of the DPFC series unit is shown in Figure 4.
denotes the conjugate complex of the targeted current line set Supposing that the voltage phasors at the sending-end and receiving-end of the transmission system are unchanged during one control cycle, then we have • The corresponding series-compensated voltage generated by each DPFC series unit is From the view of the total system, the effect of can be regarded as an equivalent series impedance set Z injected by each series unit. Then, another expression of the transmission line is According to the obvious assumption and analysis, the series-compensated voltage is • At the initial stable state t = t0, the phase angle that 1

The Control Scheme of DPFC Series Units
The structure of the DPFC series unit is shown in Figure 4. The DPFC series unit has the task of maintaining the DC capacitor voltage and responding to the reference signal effectively. The control scheme for the DPFC series unit including the single-phase locked loop (SPLL), DC capacitor voltage control and power flow control loop is depicted in Figure 5. Based on the comparison of the actual value with the reference value of the DC capacitor voltage in the DPFC series unit, the DC-voltage control loop will generate the modulation signal mod 3 v to maintain the DC capacitor voltage. Consequently, the output of the AC/DC converter equals the mutual control effects of mod 1 v and mod 3 v .

The Single-Phase Locked Loop (SPLL)
The adopted phase locked loop method is based on the literature [30]. However, the literature [30] directly integrates the angular frequency to obtain the phase-locked output, which easily leads to the saturation of the integral link. Therefore, the above method is improved in this paper, which can effectively prevent the integral saturation phenomenon.
The single-phase locked loop here is designed to track the frequency and phase of the base- Based on the comparison of the actual value with the reference value of the DC capacitor voltage in the DPFC series unit, the DC-voltage control loop will generate the modulation signal v mod3 to maintain the DC capacitor voltage. Consequently, the output of the AC/DC converter equals the mutual control effects of v mod1 and v mod3 .

The Single-Phase Locked Loop (SPLL)
The adopted phase locked loop method is based on the literature [30]. However, the literature [30] directly integrates the angular frequency to obtain the phase-locked output, which easily leads to the saturation of the integral link. Therefore, the above method is improved in this paper, which can effectively prevent the integral saturation phenomenon.
The single-phase locked loop here is designed to track the frequency and phase of the base-frequency current • I 1 and third harmonic current The measured value of the line current phase is obtained by current transformer (CT). As shown in Figure 6, the third harmonic current and base-frequency current • I 1 are separated by the filter, and then their phases are locked by the single-phase locked loop (SPLL) in the DPFC series unit. The outputs of SPLL for the base-frequency current and SPLL for third harmonic current are expressed as follows: Considering that DPFC series units have the advantage of capturing the real-time phase of the transmission line current, the waveform of the real-time phase of the terminal voltage can be reproduced during a control period, which is very practical for engineering applications.

The DC Capacitor Voltage Control
The DC capacitor voltage control loop is shown in Figure 6. By comparing the actual DC capacitor voltage dc E with the reference DC capacitor voltage , the PI controller will generate the magnitude value of the modulation signal mod 3 v . To simulate the dynamic characteristics of the converter, a first-order inertial loop is introduced for DC capacitor voltage control. To avoid causing dcsh_ref E Figure 6. The scheme of the DPFC series unit controller.

The Reproduced Real-Time Phase for Reference Series-Compensated Voltage
The time when the program of the phase locked loop of the line current is started is marked as t = 0. Recording a certain zero-crossing point of the fundamental frequency current phasor of the transmission line as t 1 , at this time, the phase of the line current is measured as ϕ i , and then the phase The real-time phase of • V 2 can be attained by Then, the real-time phase of the reference series-compensated voltage • V se_ref can be denoted as Considering that DPFC series units have the advantage of capturing the real-time phase of the transmission line current, the waveform of the real-time phase of the terminal voltage can be reproduced during a control period, which is very practical for engineering applications.

The DC Capacitor Voltage Control
The DC capacitor voltage control loop is shown in Figure 6. By comparing the actual DC capacitor voltage E dc with the reference DC capacitor voltage E dcsh_ref , the PI controller will generate the magnitude value of the modulation signal v mod3 . To simulate the dynamic characteristics of the converter, a first-order inertial loop is introduced for DC capacitor voltage control. To avoid causing extra voltage changes or power loss, the series unit is required to exchange only the active power of the third harmonic with the transmission line. Hence, the modulation signal v mod3 should be the same or inverse to the phase of the third harmonic current of the transmission line.
Thus, the DC-voltage control loop generates the modulation signal v mod3 for the third harmonic frequency voltage. The third harmonic active power generated by the parallel unit can change according to the demand for active power of the DC side to maintain the voltage of the DC capacitor in series units.
where k se represents the ratio of STT, m se is the fundamental frequency voltage modulation ratio, and E dc is the DC capacitor voltage. In fact, the phase of the control reference voltage signal of the series unit port will be shifted after passing through the inductor-capacitor (LC) filter. In addition, due to the active power loss, the amplitude of the series fundamental frequency voltage actually injected into the transmission line is smaller than the reference value. This will lead to deviations in the flow control. Therefore, it is necessary to correct the fundamental frequency compensation voltage modulation signal by taking the measurement of the mean value correction and the phase compensation.
The target and actual value of the compensated voltage are sent to the comparison module after being conversed and processed in the ADC unit. Then, the PI controller generates the compensated phase and magnitude correction factor to modify the modulation signal v mod1 . The modulating signal for compensated base-frequency voltage is modified as follows: where k Me is the magnitude modified factor and e represents the correction for the phase. m se_ref denotes the modulation ratio of the fundamental frequency voltage. According to the above analysis, integrating the four control modules together, the detailed scheme for the DPFC series unit can be depicted in Figure 6, where ω f f represents the rated angular frequency for fundamental-frequency components, and ω f f 3 represents the rated angular frequency for third harmonic components. Fcn1, Fcn2, Fcn3, Fcn5and Fcn7 are PI controllers. Fcn4, Fcn6 and Fcn8 are first-order inertia blocks. G, G 1 and G 2 represent the gain of the first-order inertia blocks.

Simulation of the DPFC Control System
The model of the transmission system including DPFCs is shown in Figure 7. It is built by the software tool PSCAD/EMTDC 4.2.1. The parallel unit is equivalent to the third harmonic current source and the series units of DPFC are built as detailed models. Thus, the DC-voltage control loop generates the modulation signal for the third harmonic frequency voltage. The third harmonic active power generated by the parallel unit can change according to the demand for active power of the DC side to maintain the voltage of the DC capacitor in series units.

The Power Flow Control
SPWM (sinusoidal PWM) control is adopted by the series unit. The relationship between the RMS value (root-mean-square) of the inverter output voltage and the DC capacitor voltage is se se se dc 2 = 2 V k mE (19) where se k represents the ratio of STT, se m is the fundamental frequency voltage modulation ratio, and dc E is the DC capacitor voltage.
In fact, the phase of the control reference voltage signal of the series unit port will be shifted after passing through the inductor-capacitor (LC) filter. In addition, due to the active power loss, the amplitude of the series fundamental frequency voltage actually injected into the transmission line is smaller than the reference value. This will lead to deviations in the flow control. Therefore, it is necessary to correct the fundamental frequency compensation voltage modulation signal by taking the measurement of the mean value correction and the phase compensation.
The target and actual value of the compensated voltage are sent to the comparison module after being conversed and processed in the ADC unit. Then, the PI controller generates the compensated phase and magnitude correction factor to modify the modulation signal mod 1 v . The modulating signal for compensated base-frequency voltage is modified as follows: where e M k is the magnitude modified factor and e represents the correction for the phase. se_ref m denotes the modulation ratio of the fundamental frequency voltage. According to the above analysis, integrating the four control modules together, the detailed scheme for the DPFC series unit can be depicted in Figure 6, where ff ω represents the rated angular frequency for fundamental-frequency components, and ff3 ω represents the rated angular frequency for third harmonic components. Fcn1, Fcn2, Fcn3, Fcn5and Fcn7 are PI controllers. Fcn4, Fcn6 and Fcn8 are first-order inertia blocks. G, G1 and G2 represent the gain of the first-order inertia blocks.

Simulation of the DPFC Control System
The model of the transmission system including DPFCs is shown in Figure 7. It is built by the software tool PSCAD/EMTDC 4.2.1. The parallel unit is equivalent to the third harmonic current source and the series units of DPFC are built as detailed models.  The device parameters of the DPFC are listed in Table 1.  The corresponding parameters for the control loops of DPFC series unit are shown in Table 2.  The simulation results of the DPFC coordination control system are depicted in Figure 8. Figure 8a shows the power flow at the receiving-end of the transmission system by employing the proposed control method. At time t = 3.5 s, P r and Q r are stable at 799.83 W and −100.66 Var, respectively. At time t = 6.0 s, P r and Q r are at a new stable state at 999.978 W and −98.25 Var, respectively. Considering the setting value given in Table 2, the power flow control is effective. Figure 8a also shows the power flow at the receiving end of the transmission system by using the state of art (SOA). At time t = 3.5 s, SOAP r and SOAQ r are stable at 800.14 W and −98.11 Var, respectively. At time t = 6.0 s, SOAP r and SOAQ r are at a new stable state 1000.42 W and −99.998 Var, respectively. Considering the setting value given in Table 2, the power flow control is effective.
Comparing the proposed method with the SOA according to the simulation results of the independent active power flow control, it is indicated that both are effective and the control effects are similar. The simulation results of the DPFC coordination control system are depicted in Figure 8.   Table 2, the power flow control is effective. Figure 8a also shows the power flow at the receiving end of the transmission system by using the state of art (SOA). At time t = 3.5 s, SOAPr and SOAQr are stable at 800.14 W and −98.11 Var, respectively. At time t = 6.0 s, SOAPr and SOAQr are at a new stable state 1000.42 W and −99.998 Var, respectively. Considering the setting value given in Table 2, the power flow control is effective.
Comparing the proposed method with the SOA according to the simulation results of the independent active power flow control, it is indicated that both are effective and the control effects are similar. Figure 8b displays the exchange of the third harmonic active power flow Pse3 and base-frequency active power flow Pse1 for each series unit. It is worth noting that Pse3 ≠ Pse1 for the reason that active power loss of VSC at the third harmonic and base frequency are not equal. Combining this power exchange process with the DC capacitor voltage in Figure 8c, it is verified that the third harmonic frequency active power is used for building and maintaining the voltage of the DC capacitor. Figure 8c indicates the DC capacitor voltage dc E of VSC. dc E grows dramatically and then remains stable at the reference value 20 V, which verifies the validity of DC-voltage control. Figure 8d represents the magnitudes of the base-frequency voltage at the primary side and secondary side of STT. Et1 is the primary-side voltage while Ese1 is the secondary-side voltage. At t  Figure 8b displays the exchange of the third harmonic active power flow P se3 and base-frequency active power flow P se1 for each series unit. It is worth noting that P se3 = P se1 for the reason that active power loss of VSC at the third harmonic and base frequency are not equal. Combining this power exchange process with the DC capacitor voltage in Figure 8c, it is verified that the third harmonic frequency active power is used for building and maintaining the voltage of the DC capacitor. Figure 8c indicates the DC capacitor voltage E dc of VSC. E dc grows dramatically and then remains stable at the reference value 20 V, which verifies the validity of DC-voltage control. Figure 8d represents the magnitudes of the base-frequency voltage at the primary side and secondary side of STT. E t1 is the primary-side voltage while E se1 is the secondary-side voltage. At t = 3.5 s, E t1 = 3.606 V and E se1 = 0.626 V. At t = 6.0 s, E t1 = 8.643 V and E se1 = 1.607 V. The ratio of STT is 20:100 (secondary side to primary side); however, the ratio between the actual voltage E se1 and E t1 is not strictly equal to 1:5. Therefore, a modification for the modulation signal v mod1 is needed. The target power flows are changed to P set3 = 800 W and Q set3 = −100 Var from t = 2.5 to 7.0 s while these are P set4 = 800 W and Q set4 = −50 Var from t = 7.0 to 10.0 s. The simulation results are shown in Figure 9.
is 20:100 (secondary side to primary side); however, the ratio between the actual voltage Ese1 and Et1 is not strictly equal to 1:5. Therefore, a modification for the modulation signal mod 1 v is needed. Figure 8e,f display the SPLL results of the line current by FFT (fast Fourier transform) component extraction. Both the phases of base-frequency and the third harmonic line current can be locked quickly and accurately. Figure 8g,h indicate the magnitude and phase angle of the base-frequency series-compensated voltage for each DPFC series unit. At t = 3.5 s, the actual values are Thus, the control of the base-frequency series-compensated voltage is effective.

Test Case 2
The target power flows are changed to Pset3 = 800 W and Qset3 = −100 Var from t = 2.5 to 7.0 s while these are Pset4 = 800 W and Qset4 = −50 Var from t = 7.0 to 10.0 s. The simulation results are shown in Figure 9. Therefore, it is verified that both the proposed method and SOA method are effective for the independent reactive power flow control. Additionally, the effects of these two methods are similar. Figure 9b displays the exchange of the third harmonic active power flow Pse3 with basefrequency active power flow Pse1 for each series unit. It is worth to noting that the power exchange process is consistent with the tendency of the DC capacitor voltage in Figure 9c; hence, it is indicated that the third harmonic frequency active power is used for building and maintaining the voltage of the DC capacitor. Figure 9c indicates the DC capacitor voltage E of VSC. E can still stay stable at 20 V when  Figure 9a shows the power flow at the receiving end of the transmission system by employing the proposed control method. At time t = 3.5 s, P r and Q r are stable at 802.59 W and −101.81 Var, respectively. At time t = 8.0 s, P r and Q r are at a new stable state of 802.86 W and −50.43 Var, respectively. Considering the given setting value, the power flow control is effective. Figure 9a also indicates the power flow at the receiving-end of the transmission system by using the state of art (SOA). At time t = 3.5 s, SOAP r and SOAQ r are stable at 800.14 W and −98.11 Var, respectively. At time t = 8.0 s, SOAP r and SOAQ r are at a new stable state of 800.01 W and −49.997 Var, respectively. Considering the given setting value, the power flow control is effective.
Therefore, it is verified that both the proposed method and SOA method are effective for the independent reactive power flow control. Additionally, the effects of these two methods are similar. Figure 9b displays the exchange of the third harmonic active power flow P se3 with base-frequency active power flow P se1 for each series unit. It is worth to noting that the power exchange process is consistent with the tendency of the DC capacitor voltage in Figure 9c; hence, it is indicated that the third harmonic frequency active power is used for building and maintaining the voltage of the DC capacitor. Figure 9c indicates the DC capacitor voltage E dc of VSC. E dc can still stay stable at 20 V when the target power flow changes, which verifies the validity of the DC capacitor voltage control. Figure 9d represents the magnitudes of the base-frequency voltage at the primary side and secondary side of STT. E t1 is the primary-side voltage while E se1 is the secondary-side voltage. At t = 3.5 s, E t1 = 3.691 V and E se1 = 0.641 V. At t = 8.0 s, E t1 = 3.545 V and E se1 = 0.612 V. The ratio of STT is 20:100 (secondary side: primary side); however, the ratio between the actual voltage E se1 and E t1 is not strictly equal to 1:5. Therefore, a correction for the modulation signal v mod1 is necessary. Figure 9e,f display the SPLL results of the line current extracted by FFT. It is verified that both the phases of the base-frequency and third harmonic line current can be locked quickly with high precision.

Comparison of the Proposed Method with the State-of-the-Art
Comparing the proposed method with the SOA in [28] based on the simulation results of power flow control in Figures 8a and 9a in Section 4.1, it is indicated that the control effect of the proposed and existing method are similar in independent active and reactive power flow control.
It should be mentioned that the starting time of the simulation in PSCAD/EMTDC for the phasors of terminal voltage and line current are the same; thus, both the initial phases of the terminal voltage and line current are measurable. In the actual operation system, however, there is no way to acquire the initial phase angle of the terminal voltage except for the phase difference between two phasors.
The SOA takes the real-time phase of the terminal voltage as the input angle of the inverse Park's transformation and generates corresponding reference values of the series-compensated voltage. Thus, the real-time phase of the terminal voltage must be provided for power flow control in multiple series units by high-speed communication link, which is not practical for the actual transmission system.
Using the proposed real-time phase reproducer of the terminal voltage, only the initial difference between the terminal voltage and line current is needed by leveraging the real-time phase of line current locally at the lower control scheme. Hence, the proposed method is much more suitable for practical engineering applications due to the limitations of communication speed, which is not considered in the existing method.

Conclusions
A coordination control method for DPFC series units has been proposed and verified in this paper. The waveform of the real-time phase of the terminal voltage can be reproduced correctly during a control period within the DPFC series units, and so a high-speed communication link is not required for the real-time power flow control. Hence, it is much more practical for engineering applications. To control the series-compensated voltage exactly, measures to modify the magnitude and angle of the modulation signal through PI control loops have been taken. The control parameters of each series unit are the same to avoid the interaction's inverse impact on multiple series unit. Simulation results from PSCAD/EMTDC have indicated that the proposed power flow control method is effective. By comparing the proposed method with the SOA in simulation and considering the speed limitations of the communication link in an actual transmission system, it can be concluded that the proposed method is more suitable for practical engineering applications with an equivalent control effect to the SOA. In future research work, experimental testing will be carried out to verify the proposed method further.

Conflicts of Interest:
The authors declare no conflict of interest.