Capacitors Voltage Switching Ripple in Three-Phase Three-Level Neutral Point Clamped Inverters with Self-Balancing Carrier-Based Modulation

This paper provides a comprehensive analysis of the capacitors voltage switching ripple for three-phase three-level neutral point clamped (NPC) inverter topologies. The voltage ripple amplitudes of the two dc-link capacitors are theoretically estimated as a function of both amplitude and phase angle of output current and the inverter modulation index. In particular, peak-to-peak distribution and maximum amplitudes of the capacitor voltage switching ripple over the fundamental period are obtained. A comparison is made considering different carrier-based pulse-width modulations in the case of almost all sinusoidal load currents, representing either grid connection or passive load with a negligible current ripple. Based on the voltage switching ripple requirements of capacitors, a simple and effective original equation for a preliminary sizing of the capacitors has been proposed. Numerical simulations and experimental tests have been carried out in order to verify the analytical developments.


Introduction
In industrial applications, the most used switching inverter is the two-level converter.Due to mass production, it is a relatively cheap and reliable configuration.Furthermore, as the number of semiconductor devices is low, they can be simply controlled by different types of pulse-width modulation (PWM) techniques.However, the main drawback of the two-level converter is the high harmonic content of the output voltage, which makes the use of bulky output filter necessary, increasing the cost of the system and the losses.The harmonic content can be reduced simply by increasing the PWM switching frequency, which leads to an increase of the switching losses.The use of power filters and high switching frequency has to be balanced to achieve reasonable converter costs with acceptable efficiency.
During the last decades, the drawbacks of the two-level converter motivated researchers to develop new converter topologies.A very promising inverter family, called multilevel inverters (MLIs), offer better quality output voltage waveforms with a reduced harmonic content comparing to the conventional two-level inverter topologies, increase the overall voltage and power rating of the converter, and generally mitigate the electromagnetic interferences.
The penetration of multilevel inverters has been steadily increasing due to their widespread usage in manufacturing, transport, energy, high-power drives and other industry applications.Several MLI topologies have been introduced and extensively studied in the literature.Most currently used multilevel topologies can be grouped: cascaded H-bridge (CHB), neutral point clamped (NPC), and flying capacitors (FC).Multilevel inverters were initiated by the invention of the so-called NPC inverter in 1981 by Nabae et al. [1].The NPC inverter uses a single DC bus subdivided into a number of voltage levels by a series string of capacitors.The voltages across the individual switches are clamped by diodes at the voltage level of only one capacitor of the series DC-link string.The major difficulty associated with control of the diode-clamped inverter is the balancing of the capacitor voltages [2,3].To achieve that, many modulation techniques have been developed [4][5][6][7][8].In particular, carrier-based modulation and space vector modulation (SVM) strategies, similar to those employed for conventional two-level three-phase inverters, can be readily modified and extended to fulfill the multilevel NPC requirements.
An essential part of MLI design is the selection of DC-link capacitors.The capacitors are a sensitive element of the inverter and a common source of failures.So far, regarding two-level converter systems, some papers have investigated the minimum DC-link capacitance and proposed methods for its size reduction [9,10].Recently, based on the DC-link voltage analysis and considering both low-and/or high-frequency DC voltage components, simple and effective guidelines for designing the DC-link capacitor have been presented in [11] for single-phase H-bridge inverter, and in [12] for three-phase three-level flying capacitor inverter.Methods used to derive expressions for RMS value and harmonic spectrum of the capacitor current in two-level inverters, are extended to the three-level inverters in [13].An analytical expression for calculating RMS current through the DC-link capacitor in a three-level NPC inverter is given in [14].The analysis of the DC-link capacitor current in three-level NPC and CHB inverters and a new numerical approach for calculating the RMS value of the capacitor current is proposed in [15].
Evaluation of the low-frequency neutral-point voltage oscillations in the three-level NPC inverter using space vector modulation (SVM) techniques has been analyzed in [16].A novel modulation strategy for the NPC inverter is proposed in [17] to overcome one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point.The proposed modulation strategy can completely remove this oscillation for all the operating conditions and for any kind of loads, even unbalanced and nonlinear loads.
Nowadays, NPC inverters are the most widely used three-level inverter topologies in the industrial applications, considering both the conventional and the T-type configurations (Figure 1).In order to choose the most suitable topology and hereby increase power efficiency, the comparison between of conventional NPC and T-type inverters has been investigated and reported in the literature [18], also considering the loss evaluation.An efficiency comparison of both over-mentioned topologies is presented in [19] and the result shows that the T-type inverter is generally more efficient at lower switching frequencies.
Energies 2018, 11, x FOR PEER REVIEW 3 of 19 input current.Section 4 presents the analysis of the capacitor voltage switching ripple.Section 5 defines the guidelines for a preliminary design of the DC-link capacitors.In Section 6 simulation and experimental verifications have been reported, and Section 7 presents the conclusion.

System Configuration
The circuit scheme of a three-level three-phase neutral point clamped inverter (NPC) is shown in Figure 1, for both conventional and T-type configurations.It consists of a DC voltage source (Vs) with series RL impedance, representing either a simplified model of a real DC source or a DC filter (series reactor).Each leg of the inverter is composed of four power switches (for leg A: SA (1) to SA (4) , the same for legs B and C).Two capacitors C1 and C2 are connected to the neutral point of the inverter and serve as a voltage divider.For proper operation of the NPC inverter, the neutral point must be kept at one half of DC-link voltage by using a proper modulation strategy able to achieve voltage balancing between the capacitors.

Modulation Principles
In case of balanced modulation and within the linear modulation range, the output voltages normalized by Vdc and averaged over the switching period (Tsw = 1/fsw) correspond to the modulating signals [20]: (1) The analysis of inverter DC-link input current and voltage is essential for sizing and designing the DC-link capacitor since it directly impacts the price, the lifetime and the failure rate of a converter system.A DC-link capacitor has to deal with the harmonics of the inverter input current and to avoid the high DC-link voltage ripple appearance.In general, the low-frequency voltage ripple component is more important for the required capacitance design since it has a higher value comparing to the switching frequency voltage ripple component.Although correctly sizing the DC-link capacitances is important to control the magnitude of the low-frequency voltage ripple, it is not the only thing that must be considered.
The calculation of low-frequency input current and input voltage ripples on DC-link capacitors have been analyzed and presented in the literature by other authors [15,16].The evaluation of voltage switching ripple for the NPC converters has not been reported yet.The analysis of the voltage switching ripple in DC-link capacitors of three-level three-phase NPC inverters, applicable to both conventional and T-type configurations (Figure 1), is presented in this paper, with reference to different carrier-based PWM techniques.The peak-to-peak capacitor voltage switching ripple amplitudes are analytically determined as a function of modulation index and output phase angle.Based on the limitation on the peak-to-peak capacitor voltage switching ripple amplitudes, simple and practical expressions for sizing the capacitors have been proposed.
The paper is organized as follows.Section 2 introduces the system configuration and the modulation principles.Section 3 presents the analysis of low-frequency and switching frequency input current.Section 4 presents the analysis of the capacitor voltage switching ripple.Section 5 defines the guidelines for a preliminary design of the DC-link capacitors.In Section 6 simulation and experimental verifications have been reported, and Section 7 presents the conclusion.

System Configuration
The circuit scheme of a three-level three-phase neutral point clamped inverter (NPC) is shown in Figure 1, for both conventional and T-type configurations.It consists of a DC voltage source (V s ) with series RL impedance, representing either a simplified model of a real DC source or a DC filter (series reactor).Each leg of the inverter is composed of four power switches (for leg A: S A (1) to S A (4) , the same for legs B and C).Two capacitors C 1 and C 2 are connected to the neutral point of the inverter and serve as a voltage divider.For proper operation of the NPC inverter, the neutral point must be kept at one half of DC-link voltage by using a proper modulation strategy able to achieve voltage balancing between the capacitors.

Modulation Principles
In case of balanced modulation and within the linear modulation range, the output voltages normalized by V dc and averaged over the switching period (T sw = 1/f sw ) correspond to the modulating signals [20]: where ϑ = ωt, ω is the fundamental angular frequency (ω = 2πf ), f is the fundamental frequency, m is the inverter modulation index, u * i are the normalized reference output voltages of each phase (i = A, B or C) and C m represents the injected common mode signal.
The voltages across the two capacitors C 1 and C 2 can be spontaneously regulated to half of the DC-link voltage by the use of proper modulation technique with self-balancing capability.i can be written (averaging is denoted by overline): With reference to the modulation (1) and considering phase A, the averaged switching functions of the upper and the lower switches, Equation (2), become: Due to the modulation symmetry among the three phases, the switching functions for the phases B and C are readily obtained considering the phase displacement of the normalized output voltages given in Equation (1).
In case of sinusoidal PWM (SPWM), the injected common-mode signal is zero: However, in case of centered PWM (CPWM), the injected common-mode signal is: In this last case, C m can be rewritten as: A straightforward method to implement carrier-based optimized centered PWM (OCPWM) for three-phase three-level inverters has been proposed in [20].The procedure is based on applying the traditional min/max centering separately to pivot voltages and residual two-level voltages.Pivot voltages are determined by a simple polarity combination of reference voltages.The resulting common-mode voltage that has to be injected in reference voltages is determined in few simple steps as described in the following equations: Figure 2 shows the three carrier-based modulations considered in this paper., S i , S i

Input Current Components
With reference to Figure 1 In case of balanced load and neglecting the output current ripple, the corresponding three-phase output currents can be written as: where Iac is the output current amplitude and ϕ is the power phase angle.
The averaged component (over the switching period) of each leg input current can be determined by multiplying the switching function of upper or lower switch of each phase by the corresponding output current.In the case of leg A it leads to: By introducing Equations ( 3) and (11) in Equation ( 12), the averaged currents of the upper and lower switch of the leg A become: The total input currents + i and − i can be calculated as the sum of the three leg currents as: Due to the three-phase symmetry of modulation and output currents within the fundamental period T, both input currents have a periodicity of T/3.As a consequence, the analysis can be restricted to an angle range of 2π/3, and all the input harmonics are multiple of 3. i.e., apart from the DC component, the lowest harmonic order component is the 3rd.

Input Current Components
With reference to Figure 1, the instantaneous input currents i + (t) and i -(t) are composed of the averaged value over the switching period, i + and i − , and the switching frequency component, ∆i + and ∆i − .Similarly, i + and i − consist of DC component over the fundamental period, I dc , and the alternating low-frequency component, i + and i − , leading to: In case of balanced load and neglecting the output current ripple, the corresponding three-phase output currents can be written as: where I ac is the output current amplitude and ϕ is the power phase angle.The averaged component (over the switching period) of each leg input current can be determined by multiplying the switching function of upper or lower switch of each phase by the corresponding output current.In the case of leg A it leads to: A i a (12) By introducing Equations ( 3) and (11) in Equation ( 12), the averaged currents of the upper and lower switch of the leg A become: The total input currents i + and i − can be calculated as the sum of the three leg currents as: A i a + S Due to the three-phase symmetry of modulation and output currents within the fundamental period T, both input currents have a periodicity of T/3.As a consequence, the analysis can be restricted to an angle range of 2π/3, and all the input harmonics are multiple of 3. i.e., apart from the DC component, the lowest harmonic order component is the 3rd.
With reference to the phase angle range 2π/3 ≤ ϑ ≤ 4π/3, two sub-ranges π/3 can be identified.Considering Equations ( 2), ( 11) and ( 14), the input currents i + and i − can be expressed as: A i a + S Introducing Equations ( 1), (2), and (11) in Equations ( 15) and ( 16), and setting C m = 0 as in case of SPWM, leads to: Similarly, replacing Equation ( 6) in Equation ( 1) in case of CPWM, input currents i + and i − can be expressed as Although the above analytical calculations are based on SPWM and CPWM, the analysis could be readily extended to other PWM techniques, such as OCPWM, leading to more complex expressions not presented in this paper.
Consequently, the low-frequency input current components are readily determined in case of SPWM as: Energies 2018, 11, 3244 7 of 20 In the case of CPWM, the low-frequency input currents are expressed as:

Input Voltage Components
Based on the analysis of the inverter input current ripple components, the instantaneous voltages v 1 and v 2 across DC-link capacitors can be written as: where V 1 and V 2 are the DC components averaged over the fundamental period, v 1 and v 2 are the alternating low-frequency ripple components, and ∆v 1 and ∆v 2 are the switching frequency ripple components of the voltages across capacitors C 1 and C 2 , respectively.Being the low-frequency ripple components widely studied in literature, the analysis is focused on the switching ripple component.

Peak-to-Peak Voltage Switching Ripple Evaluation
In order to calculate the voltage switching ripple of DC-link capacitors, the amount of the switching frequency component of currents ∆i 1 and ∆i 2 circulating through the DC-link capacitor C 1 and C 2 should be determined.Assuming that the DC source impedance at the switching frequency is much higher than the capacitor's reactance, the whole current component ∆i + and ∆i -are circulating through the capacitors C 1 and C 2 , i.e., ∆i 1 = ∆i + and ∆i 2 = ∆i − .In this case, the corresponding DC voltage variations (peak-to-peak) over the sub-periods [0-∆t 1 ] and [0-∆t 2 ] can be expressed as being ∆t 1 and ∆t 2 specific switching time intervals.The instantaneous input current is considered constant within each considered time interval.Due to the periodicity of the input currents i + and i -, the evaluation of peak-to-peak voltage ripple is limited to the phase angle range 2π/3 ≤ ϑ ≤ 4π/3.Analyzing the voltage ripple, two cases have been identified: the first case considering zero phase angle (ϕ = 0 • ) and the second considering ϕ = 60 • .The peak-to-peak voltage switching ripple of capacitors has been analytically calculated as: In case of ϕ = 0 • : Energies 2018, 11, 3244 8 of 20 In case of ϕ = 60 • : being S (1) i and S (4) i the switching function for the upper and lower switches of phase i (being i = A, B or C), given by Equation ( 2).The total averaged input currents i + and i − can be calculated by Equations ( 17) and ( 18) in case of sinusoidal PWM, and by Equations ( 19) and ( 20) in case of centered PWM.In case of optimized centered PWM the input currents can be calculated introducing Equations ( 2), ( 7) and (11) in Equations ( 15) and ( 16), leading to more complex developments.Equations ( 28)-(31) suggest normalization for ∆V 1 and ∆V 2 , as follow: being ∆U 1 and ∆U 2 the normalized peak-to-peak voltage switching ripple amplitude of capacitors.
Figure 3 shows the distribution of the normalized peak-to-peak voltage switching ripple calculated based on Equations (28), ( 29 Figure 3 presents the normalized peak-to-peak voltage ripple amplitude across the upper capacitor since the normalized peak-to-peak voltage ripple amplitude across the lower capacitor has exactly the same profile with a phase shift corresponding to 60° (1/2 of the considered period).
According to Figure 3, it can be seen a wide excursion of the normalized peak-to-peak voltage ripple amplitude, generally ranging between 0 (min) and 0.25 (max).Despite there are evident differences in the voltage switching ripple envelope profile among the three modulation strategies, it cannot be identified a modulation clearly better than the others from this point of view.This consideration is also supported by the diagrams presented in Figure 4, representing the maximum   According to Figure 3, it can be seen a wide excursion of the normalized peak-to-peak voltage ripple amplitude, generally ranging between 0 (min) and 0.25 (max).Despite there are evident differences in the voltage switching ripple envelope profile among the three modulation strategies, it cannot be identified a modulation clearly better than the others from this point of view.This consideration is also supported by the diagrams presented in Figure 4, representing the maximum of the normalized peak-to-peak ripple amplitude, calculated numerically, over the whole modulation index range, for ϕ = 0 • , 30 • , 60 • , and 90 • , considering SPWM, CPWM, and OCPWM.Again, these three modulation techniques give similar and comparable results also with reference to the maximum of the peak-to-peak voltage switching ripple.For all the cases, the absolute maximum of normalized peak-to-peak voltage ripple amplitude can be assumed as 0.25.Figure 3 presents the normalized peak-to-peak voltage ripple amplitude across the upper capacitor since the normalized peak-to-peak voltage ripple amplitude across the lower capacitor has exactly the same profile with a phase shift corresponding to 60° (1/2 of the considered period).
According to Figure 3, it can be seen a wide excursion of the normalized peak-to-peak voltage ripple amplitude, generally ranging between 0 (min) and 0.25 (max).Despite there are evident differences in the voltage switching ripple envelope profile among the three modulation strategies, it cannot be identified a modulation clearly better than the others from this point of view.This consideration is also supported by the diagrams presented in Figure 4, representing the maximum of the normalized peak-to-peak ripple amplitude, calculated numerically, over the whole modulation index range, for ϕ = 0°, 30°, 60°, and 90°, considering SPWM, CPWM, and OCPWM.Again, these three modulation techniques give similar and comparable results also with reference to the maximum of the peak-to-peak voltage switching ripple.For all the cases, the absolute maximum of normalized peak-to-peak voltage ripple amplitude can be assumed as 0.25.

Dc-link Preliminary Capacitor Design
Based on the analysis of capacitor voltage ripple components, simple and effective guidelines for a preliminary design of the capacitors C 1 and C 2 are proposed in this section.In particular, the capacitances can be calculated taking into account requirements or restrictions referred to the switching frequency and/or low-frequency voltage ripple components.
Despite the design of DC-link capacitors in the three-phase three-level inverter has been widely addressed in literature considering always the low-frequency voltage ripple, a guideline for the design of the DC-link capacitors for this multilevel inverter configuration based on the switching voltage ripple has not been developed yet.
In general, the capacitor voltage switching ripple amplitude could have additional specific restrictions to limit switching noise, electromagnetic interferences, and voltage stress on the DC-link.
In this paper, the selection of the DC-link capacitors C 1 and C 2 can be performed on the basis of the maximum amplitude of the peak-to-peak voltage switching ripple at the switching frequency (that is in the order of kHz).
According to Figure 4, it can be noted that the maximum amplitude of the peak-to-peak ripple is determined as: In this case, the capacitances can be readily calculated on the basis of Equations ( 32) and (33): Energies 2018, 11, 3244 10 of 20

Results
In order to verify proposed theoretical developments valid for both the considered NPC multilevel inverter configurations (Figure 1), numerical simulations and corresponding experimental tests are carried out.Inverter is controlled by carrier-based multilevel PWM (Figure 2) with reference to the three considered modulation techniques (SPWM, CPWM, and OCPWM).The switching frequency is set 2.5 kHz to better emphasize the switching ripple components, and two different output phase angles (0 and 60 • ) are considered, as for the specific analytical developments.The main circuit parameters are summarized in Table 1 for both simulations and experiments.

Simulation Results
Simulation results are carried out by implementing the power circuit scheme and the PWM techniques by Matlab/Simulink, considering SPWM, CPWM, and OCPWM.
The first simulation tests (Figures 5 and 6) are concerning the input inverter currents.In this case, unity sinusoidal output current (I ac = 1A) are considered to easily verify the analytical developments presented in Section 3, with specific reference to the considered output phase angles ϕ = 0 • and ϕ = 60 in case of m = 0.4 and for two cases of output phase angles ϕ = 0° (Figure 5) and ϕ = 60° (Figure 6).The bottom traces in Figures 5 and 6 show the total input current, with emphasis to instantaneous value + i (blue trace) and its averaged value over the switching period + i (red trace).The low-frequency current component (green trace) is determined analytically in both cases of SPWM and CPWM by Equations ( 22) and (24), respectively, and is calculated by replacing Equations ( 2), (7), and (11) in Equation ( 15), in the case of OCPWM.
The numerical results generally show a perfect matching with the theoretical values.The small delay between averaged and theoretical currents (Tsw/2) is due to the averaging process itself.The top traces in Figures 5 and 6 show the simulation results comparing the instantaneous input current of leg A i + A (blue trace) with its averaged value over the switching period i + A (red trace), and the corresponding low-frequency current component calculated by Equation ( 13) (green trace) in case of m = 0.4 and for two cases of output phase angles ϕ = 0 • (Figure 5) and ϕ = 60 • (Figure 6).The bottom traces in Figures 5 and 6 show the total input current, with emphasis to instantaneous value i + (blue trace) and its averaged value over the switching period i + (red trace).The low-frequency current component (green trace) is determined analytically in both cases of SPWM and CPWM by Equations ( 22) and ( 24), respectively, and is calculated by replacing Equations ( 2), (7), and (11) in Equation ( 15), in the case of OCPWM.
The numerical results generally show a perfect matching with the theoretical values.The small delay between averaged and theoretical currents (T sw /2) is due to the averaging process itself.
The second group of simulation tests is concerning the switching voltage ripple across the two DC-link capacitors.In this case, the load circuit model is corresponding to the real experimental setup, made with the purpose to easily adapt the output phase angles to the considered cases (ϕ = 0 and ϕ = 60 • ), according to Figure 7.The corresponding circuit parameters are given in Table 2.The second group of simulation tests is concerning the switching voltage ripple across the two DC-link capacitors.In this case, the load circuit model is corresponding to the real experimental setup, made with the purpose to easily adapt the output phase angles to the considered cases (ϕ = 0 and ϕ = 60°), according to Figure 7.The corresponding circuit parameters are given in Table 2.
The voltage switching ripple is determined by filtering away the low-frequency components form the instantaneous capacitor voltages.

Load
The voltage switching ripple is determined by filtering away the low-frequency components form the instantaneous capacitor voltages.
Figure 8 presents the instantaneous voltage switching ripple across the capacitors (blue traces) in case of sinusoidal PWM together with the theoretical envelopes ±ΔV1/2 (upper capacitor) and ±ΔV2/2 (lower capacitor), analytically evaluated by ( 28) and (29) (red traces) for two cases of modulation index m = 0.3 (top) and 0.5 (bottom), considering the output phase angle ϕ = 0.The same quantities are presented in Figure 9 with reference to output phase angle ϕ = 60°.In this case, envelopes ±ΔV1/2 and ±ΔV2/2 are analytically evaluated by (30) and (31).As mentioned in Section 4, the analytical developments could be readily extended to other more sophisticated modulation strategies, such as optimized centered PWM, but leading to more complex and less meaningful expressions.For this reason, the envelopes of voltage switching ripple have not explicitly obtained in case of OCPWM, just numerically derived introducing Equations ( 2), ( 7), ( 11), (15), and ( 16) in the basic Equations ( 28)-(31).Similarly, to previous cases, Figures 12 and 13 present the instantaneous voltage switching ripple across the capacitors (blue traces) in case of optimized centered PWM together with the envelopes ±∆V 1 /2 (upper capacitor) and ±∆V 2 /2 (lower capacitor) (red traces) for two cases of modulation index m = 0.3 (top) and 0.5 (bottom), considering the output phase angles ϕ= 0 (Figure 12) and ϕ = 60 • (Figure 13).As mentioned in Section 4, the analytical developments could be readily extended to other more sophisticated modulation strategies, such as optimized centered PWM, but leading to more complex and less meaningful expressions.For this reason, the envelopes of voltage switching ripple have not explicitly obtained in case of OCPWM, just numerically derived introducing Equations ( 2), ( 7), ( 11), (15), and ( 16) in the basic Equations ( 28)-(31).Similarly, to previous cases, Figures 12 and 13 present the instantaneous voltage switching ripple across the capacitors (blue traces) in case of optimized centered PWM together with the envelopes ±ΔV1/2 (upper capacitor) and ±ΔV2/2 (lower capacitor) (red traces) for two cases of modulation index m = 0.3 (top) and 0.5 (bottom), considering the output phase angles ϕ= 0 (Figure 12) and ϕ = 60° (Figure 13).

Experimental Results
A picture view of the whole experimental setup is shown in Figure 14.It consists of a three-phase T-type NPC inverter implemented by 12 discrete Silicon Carbide (SiC) power MOSFETs (CREE C2M0080120D) rated for 1200 V and 36 A. The three considered PWM techniques and the calculations to analytically determine the envelopes of voltage switching ripple across the two dc-link capacitors are implemented by a TMS320F28335 floating point DSP control board.Code Composer Studio (CCS) is adopted for programming the DSP board, with the possibility of real-time adjustment of modulation parameters by computer interface.The main circuit parameters are given in Tables 1  and 2, i.e., the same used for the second group of simulations.

Experimental Results
A picture view of the whole experimental setup is shown in Figure 14.It consists of a three-phase T-type NPC inverter implemented by 12 discrete Silicon Carbide (SiC) power MOSFETs (CREE C2M0080120D) rated for 1200 V and 36 A. The three considered PWM techniques and the calculations to analytically determine the envelopes of voltage switching ripple across the two dc-link capacitors are implemented by a TMS320F28335 floating point DSP control board.Code Composer Studio (CCS) is adopted for programming the DSP board, with the possibility of real-time adjustment of modulation parameters by computer interface.The main circuit parameters are given in Tables 1 and 2, i.e., the same used for the second group of simulations.
Experimental results are shown by Yokogawa DLM 2024 oscilloscope screenshots.Experimental results are shown by Yokogawa DLM 2024 oscilloscope screenshots.Figure 15 presents an example of load voltage and current (blue and red traces, respectively) obtained by the laboratory setup in case of sinusoidal PWM and unity power factor (m = 0.5).

Experimental Results
A picture view of the whole experimental setup is shown in Figure 14.It consists of a three-phase T-type NPC inverter implemented by 12 discrete Silicon Carbide (SiC) power MOSFETs (CREE C2M0080120D) rated for 1200 V and 36 A. The three considered PWM techniques and the calculations to analytically determine the envelopes of voltage switching ripple across the two dc-link capacitors are implemented by a TMS320F28335 floating point DSP control board.Code Composer Studio (CCS) is adopted for programming the DSP board, with the possibility of real-time adjustment of modulation parameters by computer interface.The main circuit parameters are given in Tables 1 and 2, i.e., the same used for the second group of simulations.
Experimental results are shown by Yokogawa DLM 2024 oscilloscope screenshots.Figure 15 presents an example of load voltage and current (blue and red traces, respectively) obtained by the laboratory setup in case of sinusoidal PWM and unity power factor (m = 0.5).The capacitor voltage switching ripple has been obtained experimentally by simply using the "ac coupling" built-in function of the oscilloscope together with the built-in low-pass filter, on the basis of the instantaneous capacitor voltage, according to Equation (26).Simulation and experimental results have a good matching for all the considered cases, as proved by comparing Figures 8 and 9 with Figure 16 in case of SPWM, and by comparing Figures 10 and 11 with Figure 17 in case of CPWM.Note that the same scale is adopted in corresponding simulation and experimental diagrams to facilitate the comparison.The capacitor voltage switching ripple has been obtained experimentally by simply using the "ac coupling" built-in function of the oscilloscope together with the built-in low-pass filter, on the basis of the instantaneous capacitor voltage, according to Equation (26).Simulation and experimental results have a good matching for all the considered cases, as proved by comparing Figures 8 and 9 with Figure 16 in case of SPWM, and by comparing Figures 10 and 11 with Figure 17 in case of CPWM.Note that the same scale is adopted in corresponding simulation and experimental diagrams to facilitate the comparison.

Conclusions
This paper deals with input current analysis and determination of capacitors voltage switching ripple in three-phase three-level neutral point clamped inverters.Reference is made to the basic modulation strategies, namely sinusoidal PWM, centered PWM, and optimized centered PWM, but the proposed method be easily extended to other modulation techniques.The switching frequency current and voltage ripple components have been analytically determined for the two dc-link capacitors.In particular, the peak-to-peak voltage ripple amplitudes have been calculated as a function of the inverter modulation index and the output current amplitude.Simple and effective guidelines for a preliminary design the dc-link capacitors of the NPC configuration have been also introduced.Developments have been carried out in case of general output power factor, representing either grid connections, motor, or passive loads.
The mathematical developments have been verified, both numerically and experimentally, for different values of modulation indices and specifically for two output phase angles  = 0 (corresponding to most of the grid-connected applications) and  = 60°.A very satisfactory matching between analytical, numerical, and experimental results has been achieved, proving the validity of the proposed approach.The capacitor voltage switching ripple has been obtained experimentally by simply using the "ac coupling" built-in function of the oscilloscope together with the built-in low-pass filter, on the basis of the instantaneous capacitor voltage, according to Equation (26).
Simulation and experimental results have a good matching for all the considered cases, as proved by comparing Figures 8 and 9 with Figure 16 in case of SPWM and by comparing Figures 10 and 11 with Figure 17 in case of CPWM.Note that the same scale is adopted in corresponding simulation and experimental di agrams to facilitate the comparison.

Conclusions
This paper deals with input current analysis and determination of capacitors voltage switching ripple in three-phase three-level neutral point clamped inverters.Reference is made to the basic modulation strategies, namely sinusoidal PWM, centered PWM, and optimized centered PWM, but the proposed method be easily extended to other modulation techniques.The switching frequency current and voltage ripple components have been analytically determined for the two dc-link capacitors.In particular, the peak-to-peak voltage ripple amplitudes have been calculated as a function of the inverter modulation index and the output current amplitude.Simple and effective guidelines for a preliminary design the dc-link capacitors of the NPC configuration have been also introduced.Developments have been carried out in case of general output power factor, representing either grid connections, motor, or passive loads.
The mathematical developments have been verified, both numerically and experimentally, for different values of modulation indices and specifically for two output phase angles ϕ = 0 (corresponding to most of the grid-connected applications) and ϕ = 60 • .A very satisfactory matching between analytical, numerical, and experimental results has been achieved, proving the validity of the proposed approach.

Vdc v1 v2 Figure 1 .
Figure 1. Circuit schemes of the three-phase three-level neutral point clamped (NPC) inverter: conventional type (left side) and T-type (right side).

Figure 1 .
Figure 1. Circuit schemes of the three-phase three-level neutral point clamped (NPC) inverter: conventional type (left side) and T-type (right side).
following averaged switching functions for the upper and lower switches S

Figure 3
Figure3presents the normalized peak-to-peak voltage ripple amplitude across the upper capacitor since the normalized peak-to-peak voltage ripple amplitude across the lower capacitor has exactly the same profile with a phase shift corresponding to 60 • (1/2 of the considered period).

Figure 4 .
Figure 4. Maximum peak-to-peak value of the normalized voltage switching ripple vs. modulation index m in case of (a) sinusoidal pulse-width modulation (SPWM), (b) centered PWM (CPWM) and (c) optimized centered PWM (OCPWM) for different output phase angles.

Figure 4 .
Figure 4. Maximum peak-to-peak value of the normalized voltage switching ripple vs. modulation index m in case of (a) sinusoidal pulse-width modulation (SPWM), (b) centered PWM (CPWM) and (c) optimized centered PWM (OCPWM) for different output phase angles.

Figure 5 .Figure 6 .
Figure 5.One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4, Iac = 1A and ϕ = 0°.

Figure 5 .
Figure 5.One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4,I ac = 1A and ϕ = 0 • .

Figure 5 .Figure 6 .
Figure 5.One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4, Iac = 1A and ϕ = 0°.

Figure 6 .
Figure 6.One leg dc-link current (top) and total input current (bottom): instantaneous value (blue trace), its averaged value over the switching period (red), and calculated value (green) in case of SPWM, CPWM and OCPWM (from right to left) for m = 0.4,I ac = 1A and ϕ = 60 • .Energies 2018, 11, x FOR PEER REVIEW 12 of 19

Figure 14 .
Figure 14.Picture view of the experimental setup.

Figures 16 and 17
Figures 16 and 17present the results with reference to sinusoidal PWM and centered PWM techniques, respectively.Two values of modulation index: m = 0.3 and 0.5 (from top to bottom) and two values of the output phase angles ϕ = 0 and ϕ = 60° are considered (left and right column, respectively).In all screenshots, upper traces present the capacitor voltage and its averaged counterpart (blue and green traces, respectively) and the bottom traces present the measured capacitor voltage switching ripple and the calculated peak-to-peak envelopes provided by the DSP board and displayed using DAC block with a proper voltage scaling (red and green traces, respectively).

Figure 14 .
Figure 14.Picture view of the experimental setup.

Figure 14 .
Figure 14.Picture view of the experimental setup.

Figures 16 and 17
Figures 16 and 17 present the results with reference to sinusoidal PWM and centered PWM techniques, respectively.Two values of modulation index: m = 0.3 and 0.5 (from top to bottom) and two values of the output phase angles  = 0 and = 60° are considered (left and right column, respectively).In all screenshots, upper traces present the capacitor voltage and its averaged counterpart (blue and green traces, respectively) and the bottom traces present the measured capacitor voltage switching ripple and the calculated peak-to-peak envelopes provided by the DSP board and displayed using DAC block with a proper voltage scaling (red and green traces, respectively).

Figures 16
Figures 16 and 17 present the results with reference to sinusoidal PWM and centered PWM techniques, respectively.Two values of modulation index: m = 0.3 and 0.5 (from top to bottom) and two values of the output phase angles ϕ = 0 and ϕ = 60 • are considered (left and right column,

Figure 16 .Figure 16 .
Figure 16.Experimental results for ϕ = 0° (left) and ϕ = 60° (right).Upper half: capacitor voltage and its averaged value.Lower half: calculated peak-to-peak envelope and measured capacitor voltage switching ripple with different modulation indexes: m = 0.3 and 0.5 (from top to bottom) in case of SPWM.

Figure 16 .Figure 17 .
Figure 16.Experimental results for ϕ = 0° (left) and ϕ = 60° (right).Upper half: capacitor voltage and its averaged value.Lower half: calculated peak-to-peak envelope and measured capacitor voltage switching ripple with different modulation indexes: m = 0.3 and 0.5 (from top to bottom) in case of SPWM.

Figure 17 .
Figure 17.Experimental results for = 0° (left) and  = 60° (right).Upper half: capacitor voltage and its averaged value.Lower half: calculated peak-to-peak envelope and measured capacitor voltage switching ripple with different modulation indexes: m = 0.3 and 0.5 (from top to bottom) in case of CPWM.

Figure 17 .
Figure 17.Experimental results for ϕ = 0 • (left) and ϕ = 60 • (right).Upper half: capacitor voltage and its averaged value.Lower half: calculated peak-to-peak envelope and measured capacitor voltage switching ripple with different modulation indexes: m = 0.3 and 0.5 (from top to bottom) in case of CPWM.
, the instantaneous input currents i + (t) and i -(t) are composed of the averaged value over the switching period, + i and − i , and the switching frequency component,