Damping Optimum-Based Design of Control Strategy Suitable for Battery / Ultracapacitor Electric Vehicles

This contribution outlines the design of electric vehicle direct-current (DC) bus control system supplied by a battery/ultracapacitor hybrid energy storage system, and its coordination with the fully electrified vehicle driveline control system. The control strategy features an upper-level DC bus voltage feedback controller and a direct load compensator for stiff tracking of variable (speed-dependent) voltage target. The inner control level, comprising dedicated battery and ultracapacitor current controllers, is commanded by an intermediate-level control scheme which dynamically distributes the upper-level current command between the ultracapacitor and the battery energy storage systems. The feedback control system is designed and analytical expressions for feedback controller parameters are obtained by using the damping optimum criterion. The proposed methodology is verified by means of simulations and experimentally for different realistic operating regimes, including electric vehicle DC bus load step change, hybrid energy storage system charging/discharging, and electric vehicle driveline subject to New European Driving Cycle (NEDC), Urban Driving Dynamometer Schedule (UDDS), New York Certification Cycle (NYCC) and California Unified Cycle (LA92), as well as for abrupt acceleration/deceleration regimes.


Introduction
According to reference [1], road transport significantly contributes to the already alarmingly high levels of CO 2 in the atmosphere, which are the main cause of the greenhouse effect [2].Since this sector is also highly sensitive to the availability of oil [3], it has gradually moved towards greater inclusion of electric vehicles (EVs) into the transportation sector due to their favorable fuel economy and low CO 2 footprint during exploitation [1,3].Moreover, electrical vehicle technology has also been recognized as one of the key factors in the development of intelligent transportation system (ITS) [4], and its integration within the smart grid framework [5].
However, one of the main limitations of currently deployed EVs is that, generally speaking, their batteries can be optimized either for high-power operation or high energy capacity [6][7][8], wherein batteries characterized by high-power operating capabilities would be able to support abrupt loads such as those encountered during vehicle acceleration and regenerative braking regimes, whereas batteries characterized by high energy density can facilitate higher EVs autonomy and larger all-electric driving range [9][10][11].Additionally, when batteries are subject to frequent high-power abrupt loading regimes, their useful operating life tends to significantly decrease, as opposed to those operating under steady loads [12][13][14].Under the aforementioned highly dynamic driving conditions, battery thermal stress may become a serious issue, which mandates battery temperature monitoring based on vehicle power-train energy consumption and appropriate battery thermal model [15].Different battery pack cooling strategies may be employed to prolong the battery useful life and discharge capability (see e.g., [16] and references therein).Both references [15] and [16] emphasize the need for precise overall battery system modeling for thermal monitoring and management.
One way of dealing with the aforementioned battery limitations would be to oversize the EV high-power battery pack [7], but this would in turn increase the EV weight and production costs and would also result in lower efficiency of the electric power-train [14].A practical alternative to battery over-sizing would be augmentation of the high-energy-density battery with an ultracapacitor-based energy storage system (ESS) [17].Being characterized by exceptional power densities and cycling abilities (durability) compared to batteries, ultracapacitors represent a viable auxiliary energy storage solution for peak shaving of aforementioned EV pulsed loads [18,19].Furthermore, a study presented in [20] has suggested that battery hybridization with ultracapacitors within EVs might result in approximately 75% battery cycle life extension through peak load shaving by means of ultracapacitors and associated reduction of battery thermal burden.Moreover, the benefits of employing battery/ultracapacitor hybrid energy storage (HESS) have been confirmed in [21], wherein the cost of temperature-related battery degradation strongly favors the use of ultracapacitors, which would facilitate profitable HESS operation over the anticipated 10-year period of exploitation.Of course, proper sizing of the individual battery and ultracapacitor energy storages within the HESS is needed with respect to the anticipated operating conditions of the EVs [22].
The aforementioned energy storage hybridization concept has shown clear benefits in the transportation sector [23] and has resulted in numerous successful EV applications [9,10,[24][25][26].A parallel battery/ultracapacitor HESS topology with independent load control of individual energy storages should be well suited for energy management control tasks [6,7,11,26,27].In such an arrangement, both the battery and the ultracapacitor system are equipped with high-performance current-controlled power converters [28], providing bidirectional energy management within the EVs through the common direct-current (DC) bus (see Figure 1).This may be a challenging control problem because the supervisory control strategy should simultaneously keep the DC bus voltage within narrow bounds [9,25], while also distributing the DC bus load between the battery and ultracapacitor ESS to facilitate smooth EV power-train operation for a wide range of operating regimes [29,30].In particular, the power converter coordination (load distribution) in EV applications should be aimed at ultracapacitor taking on the excessive (pulsed) power demand [31] and acting as a transient power load buffer.This may be facilitated through conditioning of the power demanded from the ultracapacitor power converter with respect to the battery by using a rule-based [32] or a proportional load distribution strategy [31].Naturally, due to low energy density of ultracapacitor ESS, ultracapacitor system voltage should also be monitored and controlled to avoid overcharging or operation at low state of charge [28].
Energies 2018, 11, x FOR PEER REVIEW 2 of 27 high-power abrupt loading regimes, their useful operating life tends to significantly decrease, as opposed to those operating under steady loads [12][13][14].Under the aforementioned highly dynamic driving conditions, battery thermal stress may become a serious issue, which mandates battery temperature monitoring based on vehicle power-train energy consumption and appropriate battery thermal model [15].Different battery pack cooling strategies may be employed to prolong the battery useful life and discharge capability (see e.g., [16] and references therein).Both references [15] and [16] emphasize the need for precise overall battery system modeling for thermal monitoring and management.
One way of dealing with the aforementioned battery limitations would be to oversize the EV high-power battery pack [7], but this would in turn increase the EV weight and production costs and would also result in lower efficiency of the electric power-train [14].A practical alternative to battery over-sizing would be augmentation of the high-energy-density battery with an ultracapacitor-based energy storage system (ESS) [17].Being characterized by exceptional power densities and cycling abilities (durability) compared to batteries, ultracapacitors represent a viable auxiliary energy storage solution for peak shaving of aforementioned EV pulsed loads [18,19].Furthermore, a study presented in [20] has suggested that battery hybridization with ultracapacitors within EVs might result in approximately 75% battery cycle life extension through peak load shaving by means of ultracapacitors and associated reduction of battery thermal burden.Moreover, the benefits of employing battery/ultracapacitor hybrid energy storage (HESS) have been confirmed in [21], wherein the cost of temperature-related battery degradation strongly favors the use of ultracapacitors, which would facilitate profitable HESS operation over the anticipated 10-year period of exploitation.Of course, proper sizing of the individual battery and ultracapacitor energy storages within the HESS is needed with respect to the anticipated operating conditions of the EVs [22].
The aforementioned energy storage hybridization concept has shown clear benefits in the transportation sector [23] and has resulted in numerous successful EV applications [9,10,[24][25][26].A parallel battery/ultracapacitor HESS topology with independent load control of individual energy storages should be well suited for energy management control tasks [6,7,11,26,27].In such an arrangement, both the battery and the ultracapacitor system are equipped with high-performance current-controlled power converters [28], providing bidirectional energy management within the EVs through the common direct-current (DC) bus (see Figure 1).This may be a challenging control problem because the supervisory control strategy should simultaneously keep the DC bus voltage within narrow bounds [9,25], while also distributing the DC bus load between the battery and ultracapacitor ESS to facilitate smooth EV power-train operation for a wide range of operating regimes [29,30].In particular, the power converter coordination (load distribution) in EV applications should be aimed at ultracapacitor taking on the excessive (pulsed) power demand [31] and acting as a transient power load buffer.This may be facilitated through conditioning of the power demanded from the ultracapacitor power converter with respect to the battery by using a rule-based [32] or a proportional load distribution strategy [31].Naturally, due to low energy density of ultracapacitor ESS, ultracapacitor system voltage should also be monitored and controlled to avoid overcharging or operation at low state of charge [28].Simultaneous load sharing and DC bus voltage control typically requires an additional control level.In the case of off-line optimization studies of battery/ultracapacitor HESS, a dynamic programming-based off-line control law may achieve a global optimum in terms of minimum battery degradation over time [21].This approach, however, cannot be used in real-time applications due to its non-causality (i.e., the requirement to know the driving cycle beforehand), and its intense computational burden.Other optimization-based approaches, such as those based on pseudo-spectral method [33] have also been investigated, wherein the battery cycle life and energy capacity retention optimization problem is solved by using nonlinear programming (NLP).For on-line applications, the aforementioned load allocation problem may be addressed within the framework of robust state control in the form of linear quadratic regulator (LQR) [9] with the EV power-train load treated as a system uncertainty.Successful application of a model predictive controller (MPC) for the energy management task has been demonstrated for the case of fully deterministic process model [34], and stochastic process model representation within MPC framework [12].The predictive control approach has also been used to minimize the battery and ultracapacitor losses, while simultaneously maintaining the ultracapacitor state of charge within prescribed bounds [35].Artificial intelligence control methods, such as those based on artificial neural networks (ANNs) [36] and fuzzy logic [37] have also been successful in achieving favorable battery performance indices in terms of battery life extension and capacity preservation within EVs based on HESS.However, these control approaches may be characterized by a rather high level of design complexity and intricate implementation requiring sophisticated control hardware [9,34], which may not be suitable for industry applications.Moreover, in the aforementioned cases of MPC and LQR controllers, the power converter response dynamics and limits are dealt with implicitly through cost function weighting, which might entail some closed-loop performance trade-offs related to weighting factors choices.Therefore, it would be favorable from the standpoint of practical control system design to provide a simple and robust power sharing strategy which would prioritize the power demand to avoid abrupt battery loading issues [38].
Having this in mind, the engineering practice suggests that the prospective control strategy should be characterized by: (1) Top-down cascade control system structure, to facilitate direct saturation of current demands via power converter references [39]; (2) Bottom-up control system design wherein the current control systems for the battery and ultracapacitor ESS are designed and tested first, which is then followed by the comprehensive design of the superimposed feedback control levels [40]; (3) A direct or indirect load compensator should augment the feedback controllers to deal with potentially abrupt loads at the EV DC bus side [41,42]; (4) Variable DC bus voltage target, which is characteristic for hybrid-EVs [43,44] and those with fully electrified power-trains [45], and may also be beneficial to useful life extension of capacitors within the inverter DC bus [46]; (5) Use of control system design methodology which could facilitate straightforward tuning of the closed-loop control system response dynamics; (6) Simplicity of code implementation that would enable use on robust microcontroller platforms suitable for automotive applications.
Having this in mind, the hypothesis of this work is that favorable performance of DC bus control system in terms of load suppression can be achieved by using a DC bus cascade control system structure and feed-forward load compensating action (see e.g., [39]), both for the case of constant and variable (EV-operating regime-dependent) DC bus voltage target.The proposed solution is based on the well-established proportional-integral (PI) feedback controller of DC bus voltage augmented with direct load compensator, which command suitable current demands to the hybrid battery/ultracapacitor HESS via a dynamic load distribution scheme.A damping optimum-based methodology [47] is used for feedback control system design, whereas direct zero-pole canceling approach is used for load compensator tuning.The proposed design approach has been verified through simulations and experimentally for different realistic EV power-train operating scenarios.These included a DC bus load step disturbance, EV driveline subject to urban-type driving cycles, such as the New European Driving Cycle (NEDC), Urban Driving Dynamometer Schedule (UDDS), New York Certification Cycle (NYCC) and California Unified Cycle (also known as LA92 cycle) [48] and abrupt EV acceleration and deceleration commands.
The paper is organized in six sections.Section 2 presents the DC bus system and vehicle driveline load model, whereas Section 3 outlines the control system design.Simulation results are included in Section 4, while Section 5 presents the result of experimental verification on a down-scaled DC bus laboratory setup.Discussion of obtained results and final remarks are given in Section 6.

EV Power-Train Model
This section presents the models of EV power-train and the DC bus topology based on parallel-connected battery and ultracapacitor ESS.

Fully Electric Power-Train Topology
The power-train topology of the EVs analyzed herein is shown in Figure 1.The hypothetical vehicle is equipped with the battery and ultracapacitor ESSs parallel-connected via individual two-quadrant DC/DC power converters [32] to the common DC bus, which also supplies the power converter (inverter) of the alternating current (AC) servo motor which provides wheel traction through the fixed-ratio transmission (gearbox).Even though the electric drive-train should also include a hydraulic braking system, a power dissipation resistor for additional electro-dynamic braking capability, and different electrical auxiliaries, these are omitted from the "idealized" EV power-train representation in Figure 1 to simplify the subsequent analysis.Nevertheless, these systems could be taken into account through an additional load component in the DC bus load current i L .

Traction Motor Control System
An AC permanent-magnet synchronous motor (PMSM) is considered for vehicle traction in this work, primarily due to its advantages over the AC induction motor in terms of higher power density, better overall efficiency, and generally smaller rotor inertia [49].The natural PMSM machine description in the so-called stationary (stator-side) reference frame is described by a highly nonlinear dynamic model, which is not convenient from the standpoint of control system design.The PMSM control system is realized within the framework of field-oriented (or vector) control, which enables decoupled field flux and torque control at the rotor [39].For that purpose, the PMSM machine stator-side variables (e.g., phase currents) are transformed into the so-called rotating d-q coordinate frame, where the d-axis relates to the rotor permanent-magnet field flux direction and the q-axis is perpendicular to it.In this way, the PMSM machine model resembles the model of the DC machine which is more convenient for analysis and control system design [39].The resulting so-called field (d) and torque (q) currents i d and i q are obtained from the motor phase sinusoidal currents i 1 , i 2 and i 3 by using the well-known Park transform [50]: where θ = ωt is the rotor "electrical" angular position, and ω is the rotor "electrical" speed.
Figure 2 shows the block diagram representation of the PMSM current control system in the d-q reference frame.The PMSM servo-machine model comprises the simplified representation of the motor inverter, denoted by a first-order lag term with time constant T di corresponding to the small lag of the inverter voltage response.The traction motor model comprises the first-order armature (stator winding) lag model in both the field (d) and torque (q) axis, characterized by armature inductance L a and resistance R a , which determine the respective motor current components based on input voltages u d and u q and the motor electromotive force u emf = Φ r ω = pΦ r ω m (ω m is the rotor angular speed, Φ r is the rotor field flux, and p is the number of motor pole pairs).The model also includes the so-called cross-axis coupling terms ∆u d = ωL a i q and ∆u q = ωL a i d which are the result of the aforementioned Park transform.Dual fast PI controllers are used to control the aforementioned currents i d and i q , and their design is presented in the next section.However, to obtain effective suppression of cross-axis coupling terms ∆u d and ∆u q , feed-forward d-q-axis cross-axis compensation terms are also included within the control system in Figure 2.These additive control terms are based on the available motor speed ω m and current signals (see Figure 2).Finally, the current control system in Figure 2 may also include the compensation of counter electromotive force (EMF) (pΦ r ω m term in Figure 2).The aforementioned PMSM machine parameters which can be used in subsequent simulation analysis can be obtained from the catalogue data for a suitably sized PMSM motor (see Section 4), whereas the current PI controller parameters are obtained as the result of control system design procedure described in Section 3.4 and are listed in Section 4.
The voltage command signals u dR and u qR , provided by respective current controllers are then transformed back to the stator-side coordinate frame quantities (i.e., phase voltage references u 1R , u 2R and u 3R ) through the inverse Park transform: Operation below the rated speed is considered herein, so current i d is kept at zero under closed-loop current control (i dR = 0), and the PMSM overall field flux Ψ = Φ r + L a i d corresponds to the rated rotor flux Φ r .In that case the relationship between torque current reference i qR and the motor torque target τ R simplifies to (see i qR reference path in Figure 2): with k T = 1.5pΦ r being the motor torque constant.
Energies 2018, 11, x FOR PEER REVIEW 5 of 27 input voltages ud and uq and the motor electromotive force uemf = Φrω = pΦrωm (ωm is the rotor angular speed, Φr is the rotor field flux, and p is the number of motor pole pairs).The model also includes the so-called cross-axis coupling terms Δud = ωLaiq and Δuq = ωLaid which are the result of the aforementioned Park transform.Dual fast PI controllers are used to control the aforementioned currents id and iq, and their design is presented in the next section.However, to obtain effective suppression of cross-axis coupling terms Δud and Δuq, feed-forward d-q-axis cross-axis compensation terms are also included within the control system in Figure 2.These additive control terms are based on the available motor speed ωm and current signals (see Figure 2).Finally, the current control system in Figure 2 may also include the compensation of counter electromotive force (EMF) (pΦrωm term in Figure 2).The aforementioned PMSM machine parameters which can be used in subsequent simulation analysis can be obtained from the catalogue data for a suitably sized PMSM motor (see Section 4), whereas the current PI controller parameters are obtained as the result of control system design procedure described in Section 3.4 and are listed in Section 4.
The voltage command signals udR and uqR, provided by respective current controllers are then transformed back to the stator-side coordinate frame quantities (i.e., phase voltage references u1R, u2R and u3R) through the inverse Park transform: Operation below the rated speed is considered herein, so current id is kept at zero under closed-loop current control (idR = 0), and the PMSM overall field flux Ψ = Φr + Laid corresponds to the rated rotor flux Φr.In that case the relationship between torque current reference iqR and the motor torque target τR simplifies to (see iqR reference path in Figure 2):

Dynamic Model of DC Bus
The DC bus system in Figure 1 is described by the following integral-type process model: where Cdc represents the capacitance of the DC bus, udc is the voltage across the DC bus, iL represents the EV power-train-related load current, and icb and icu are input currents of battery and ultracapacitor ESS, i.e., input currents of their respective DC/DC power converters.

Dynamic Model of DC Bus
The DC bus system in Figure 1 is described by the following integral-type process model: Energies 2018, 11, 2854 6 of 26 where C dc represents the capacitance of the DC bus, u dc is the voltage across the DC bus, i L represents the EV power-train-related load current, and i cb and i cu are input currents of battery and ultracapacitor ESS, i.e., input currents of their respective DC/DC power converters.
If battery and ultracapacitor-side current measurements i b and i u (see Figure 1) are available, DC bus-side currents i cb and i cu could be estimated based on the following relationships between the average values of battery and ultracapacitor currents i b and i u and the corresponding DC/DC power converter instantaneous input currents i cb and i cu are valid (Figure 3, see also [51,52]): where d b and d u are battery and ultracapacitor DC/DC converter pulse-width-modulated (PWM) output voltage duty cycles, respectively, which are readily available from the current controller-based voltage reference commanded to power converter [40].Since the voltage PWM switching frequency is relatively high, the above averaged currents may be used instead of their instantaneous values within the DC bus model (4).In this way, the subsequent design of the DC bus control system can be greatly simplified [41].
Energies 2018, 11, x FOR PEER REVIEW 6 of 27 If battery and ultracapacitor-side current measurements ib and iu (see Figure 1) are available, DC bus-side currents icb and icu could be estimated based on the following relationships between the average values of battery and ultracapacitor currents ib and iu and the corresponding DC/DC power converter instantaneous input currents icb and icu are valid (Figure 3, see also [51,52]): where db and du are battery and ultracapacitor DC/DC converter pulse-width-modulated (PWM) output voltage duty cycles, respectively, which are readily available from the current controller-based voltage reference commanded to power converter [40].Since the voltage PWM switching frequency is relatively high, the above averaged currents may be used instead of their instantaneous values within the DC bus model (4).In this way, the subsequent design of the DC bus control system can be greatly simplified [41].The following expression is valid for the averaged DC bus load iL due to the operation of three-phase motor inverter [46]: where Iph is the amplitude of the phase current fundamental component, Uph is the amplitude of inverter phase voltage fundamental component, and cosϕ is the traction motor power factor.The principal components of the PMSM stator reference frame currents are given as follows: These can be transformed to the d-q coordinate frame according to (1), yielding the following relationships between id and iq and the inverter reactive and active current: Finally, by using the d-q frame voltage references udR and uqR obtained from respective current controllers (Figure 2), the amplitude Uph of the inverter phase voltage can be directly calculated in the following manner [42]: The following expression is valid for the averaged DC bus load i L due to the operation of three-phase motor inverter [46]: where I ph is the amplitude of the phase current fundamental component, U ph is the amplitude of inverter phase voltage fundamental component, and cosϕ is the traction motor power factor.The principal components of the PMSM stator reference frame currents are given as follows: These can be transformed to the d-q coordinate frame according to (1), yielding the following relationships between i d and i q and the inverter reactive and active current: Finally, by using the d-q frame voltage references u dR and u qR obtained from respective current controllers (Figure 2), the amplitude U ph of the inverter phase voltage can be directly calculated in the following manner [42]: Hence, the DC bus load i L according to Equation ( 6) can be directly estimated based on Equations ( 8) and ( 9), and direct load compensation can be easily facilitated.

ESS Models
As illustrated by the principal schematic in Figure 1, the battery ESS can be described by the quasi-static Thevenin process model [7]: where u b is the battery terminal voltage, i b is the battery current, R b is the battery equivalent series resistance, Q b is the battery charge capacity, and E b and ξ are battery electromotive force and state of charge, respectively.Similarly, ultracapacitor ESS in Figure 1 is modeled as a simple series connection of the equivalent series resistance R u and ultracapacitor capacitance C u [7]: where u u and i u are the ultracapacitor terminal voltage and input current, respectively.

Control System Design
Based on the previously described models of individual EV power-train subsystems, a suitable energy management control strategy is designed in this section.

Damping Optimum Criterion
Damping optimum criterion [47] is a practical pole-placement-like method of design of linear continuous-time closed-loop systems and is used herein for the tuning of feedback control loops.The tuning procedure is based on the following closed-loop characteristic polynomial: where T e represents the so-called closed-loop equivalent time constant, and D 2 , D 3 , . . ., D n represent the damping optimum characteristic ratios of the nth order closed-loop system.In the so-called "optimal" case, characterized by D i = 0.5 (i = 2, . . ., n), the closed-loop system has a quasi-aperiodic step response characterized by an overshoot of approximately 6% (resembling a second-order system with damping ratio ζ = 0.71) and the approximate rise time (1.8-2.1)T e .The aforementioned closed-loop damping ratio value 0.71 is considered an "optimal" choice in practical applications because it provides relatively fast step reference response with small (negligible) overshoot without any weakly damped oscillations in the control loop state variables during the response settling stage.The closed-loop damping adjustment corresponds to the adjustment of the individual characteristic ratios D i , wherein the most dominant characteristic ratio D 2 determines the damping of the dominant closed-loop dynamics.In particular, by increasing the characteristic ratio D 2 above the optimal value 0.5 (while keeping the less-dominant characteristic ratios at optimal values D i = 0.5, i = 3, . . ., n), the closed-loop response becomes faster and more oscillatory.On the other hand, by decreasing D 2 below 0.5, the closed-loop system damping level is increased, and the closed-loop system is characterized by slower response without overshoot, i.e., the so-called aperiodic dynamics are obtained (see e.g., discussions in [47,53]).Finally, by choosing a larger value of equivalent closed-loop time constant T e , the control system generally tends to be more robust and its sensitivity to noise is greatly improved (i.e., bandwidth Ω BW is proportional to 1/T e ).However, this results in control system response slowdown and poorer disturbance rejection performance.

Low-Level Control of ESSs
Block diagram models of current control loops for the battery and ultracapacitor ESS are shown in Figure 4a,b, respectively.The battery and ultracapacitor energy storages are characterized by their respective equivalent electrical-circuit models given by Equations ( 10) and (11) in the case of battery, and Equation ( 12) in the case of ultracapacitor.Individual ESS current control is based on the PI controller in its modified form characterized by the proportional gain being in the local feedback path, while the integral term acts upon the current control error.In this way, controller zeros do not occur in the closed-loop transfer function model between the reference and the controlled variable (see discussion in [53]).
Since charge accumulation processes are typically slow, the battery electromotive force and ultracapacitor charge-related voltage variations are rather non-emphasized compared to voltage variations due to voltage drop across the series resistance, especially during transients.Thus, the dominant current transient dynamics may be expressed by a simple equivalent first-order transfer function model [40]: where L c is the inductance of the embedded inductor within the DC/DC power converter and R tot is the total series resistance of the respective ESS in Figure 4 (R tot = R c + R b in the case of battery and R tot = R c + R u for the case of ultracapacitor).

Low-Level Control of ESSs
Block diagram models of current control loops for the battery and ultracapacitor ESS are shown in Figure 4a,b, respectively.The battery and ultracapacitor energy storages are characterized by their respective equivalent electrical-circuit models given by Equations ( 10) and (11) in the case of battery, and Equation ( 12) in the case of ultracapacitor.Individual ESS current control is based on the PI controller in its modified form characterized by the proportional gain being in the local feedback path, while the integral term acts upon the current control error.In this way, controller zeros do not occur in the closed-loop transfer function model between the reference and the controlled variable (see discussion in [53]).
Since charge accumulation processes are typically slow, the battery electromotive force and ultracapacitor charge-related voltage variations are rather non-emphasized compared to voltage variations due to voltage drop across the series resistance, especially during transients.Thus, the dominant current transient dynamics may be expressed by a simple equivalent first-order transfer function model [40]: where Lc is the inductance of the embedded inductor within the DC/DC power converter and Rtot is the total series resistance of the respective ESS in Figure 4 (Rtot = Rc + Rb in the case of battery and Rtot = Rc + Ru for the case of ultracapacitor).Based on block diagram representations of battery and ultracapacitor ESS current control loops, the damping optimum-based control system design is carried out.To simplify the design procedure, the small delay due to power converter and current sensor (filter) lags are lumped into a single equivalent lag action: (15) wherein the equivalent parasitic lag constant T∑i = Tl + Tfi may also include the sampling delay if a discrete-time (digital) controller is considered.
Based on Equation ( 15) and current vs. voltage model ( 14) under the assumption of slow charge accumulation-related phenomena, the current measurement vs. reference value transfer function model im(s)/iR(s) of both closed-loop current control systems in Figure 4 is given by: Based on block diagram representations of battery and ultracapacitor ESS current control loops, the damping optimum-based control system design is carried out.To simplify the design procedure, the small delay due to power converter and current sensor (filter) lags are lumped into a single equivalent lag action: wherein the equivalent parasitic lag constant T ∑i = T l + T fi may also include the sampling delay if a discrete-time (digital) controller is considered.
Based on Equation ( 15) and current vs. voltage model ( 14) under the assumption of slow charge accumulation-related phenomena, the current measurement vs. reference value transfer function model i m (s)/i R (s) of both closed-loop current control systems in Figure 4 is given by: The damping optimum tuning procedure for the current control system is carried out by equating the coefficients of the denominator of the transfer function model (16) with the coefficients of the damping optimum characteristic polynomial defined by Equation ( 13) for the case of third-order nominal model (n = 3).After some manipulation and rearranging, the following analytical relationships are obtained, which relate the PI controller parameters with the process parameters and damping optimum tuning parameters (i.e., characteristic ratios) [40][41][42]: Clearly, this tuning approach enables independent tuning of the response speed (equivalent time constant T ei ) and closed-loop damping (dominant characteristic ratio D 2i ).
Unlike the battery, the ultracapacitor is characterized by rather low energy density (charge capacity).Hence, it may relatively quickly become discharged if frequent discharging demands are commanded to ultracapacitor ESS.Therefore, a supplementary controller of ultracapacitor state of charge is also needed [40,41].For the sake of simplicity, it can be realized as ultracapacitor terminal voltage PI controller, as shown in Figure 5.The damping optimum tuning procedure for the current control system is carried out by equating the coefficients of the denominator of the transfer function model (16) with the coefficients of the damping optimum characteristic polynomial defined by Equation ( 13) for the case of third-order nominal model (n = 3).After some manipulation and rearranging, the following analytical relationships are obtained, which relate the PI controller parameters with the process parameters and damping optimum tuning parameters (i.e., characteristic ratios) [40][41][42]: Clearly, this tuning approach enables independent tuning of the response speed (equivalent time constant Tei) and closed-loop damping (dominant characteristic ratio D2i).
Unlike the battery, the ultracapacitor is characterized by rather low energy density (charge capacity).Hence, it may relatively quickly become discharged if frequent discharging demands are commanded to ultracapacitor ESS.Therefore, a supplementary controller of ultracapacitor state of charge is also needed [40,41].For the sake of simplicity, it can be realized as ultracapacitor terminal voltage PI controller, as shown in Figure 5. Again, to simplify the design procedure, the rather small time constants of the inner current control loop (Teu) and voltage measurement (Tfv) are lumped into a single equivalent time constant T∑u = Teu + Tfv, which results in the following form of the closed-loop system characteristic polynomial: The previously described damping optimum design yields the following analytical expressions for the controller parameters (i.e., time constant Tca and gain Kca): with the equivalent time constant Tea in above expressions obtained through solving of the following cubic equation: Again, to simplify the design procedure, the rather small time constants of the inner current control loop (T eu ) and voltage measurement (T fv ) are lumped into a single equivalent time constant T ∑u = T eu + T fv , which results in the following form of the closed-loop system characteristic polynomial: The previously described damping optimum design yields the following analytical expressions for the controller parameters (i.e., time constant T ca and gain K ca ): Energies 2018, 11, 2854 10 of 26 with the equivalent time constant T ea in above expressions obtained through solving of the following cubic equation: whose solution also needs to satisfy the following feasibility condition to obtain non-negative values of controller parameters: Please note that the auxiliary state of charge control loop response dynamics need to be much slower than the command from the superimposed control level (see next subsection), so that any interference with the control action i uR from the upper-level DC bus control strategy (also shown in Figure 5) may be effectively avoided.

Design of DC Bus Voltage Control System
Figure 6 shows the DC bus control system arrangement, comprising the upper-level DC voltage feedback controller and feed-forward load compensator which command the inner current control loops of the battery and ultracapacitor ESS through the dynamic load distribution scheme.
The DC bus voltage reference u dcR is calculated based on PMSM inverter phase voltage amplitude estimate according to Equation ( 9), subject to the following constraint related to the upper bound of the phase voltage modulation index M max = 1.155 to avoid traction motor phase voltage over-modulation issues [46]: This is done in Figure 6 by simply augmenting the theoretical DC voltage result u dc = 2U ph /M max according to (25) through a voltage scaling factor κ u > 1.Note also that the DC bus voltage reference u dcR needs to be limited to prevent: (1) DC bus under-voltages and (2) rather inefficient boost operation of the DC/DC power converter at high DC bus voltages (see [54]).
Energies 2018, 11, x FOR PEER REVIEW 10 of 27 whose solution also needs to satisfy the following feasibility condition to obtain non-negative values of controller parameters: Please note that the auxiliary state of charge control loop response dynamics need to be much slower than the command from the superimposed control level (see next subsection), so that any interference with the control action iuR from the upper-level DC bus control strategy (also shown in Figure 5) may be effectively avoided.

Design of DC Bus Voltage Control System
Figure 6 shows the DC bus control system arrangement, comprising the upper-level DC voltage feedback controller and feed-forward load compensator which command the inner current control loops of the battery and ultracapacitor ESS through the dynamic load distribution scheme.
The DC bus voltage reference udcR is calculated based on PMSM inverter phase voltage amplitude estimate according to Equation ( 9), subject to the following constraint related to the upper bound of the phase voltage modulation index Mmax = 1.155 to avoid traction motor phase voltage over-modulation issues [46]: This is done in Figure 6 by simply augmenting the theoretical DC voltage result udc = 2Uph/Mmax according to (25) through a voltage scaling factor κu > 1.Note also that the DC bus voltage reference udcR needs to be limited to prevent: (1) DC bus under-voltages and (2) rather inefficient boost operation of the DC/DC power converter at high DC bus voltages (see [54]).According to Figure 6, the current reference from the upper-level DC bus PI feedback controller and load compensator should be dynamically distributed between the battery and ultracapacitor ESS to facilitate effective load disturbance suppression of the closed-loop system.Since batteries are typically intended for steady and slowly changing loads [55], the battery ESS current controller should be tuned for slow response (i.e., tuned with large equivalent time constant Teb).On the other hand, ultracapacitor ESS, being able to provide peak shaving capability, should be equipped with fast-current controller (i.e., characterized by small equivalent lag Teu).Indeed, within the load distribution strategy in Figure 6 the "slow" battery ESS receives the upper-level command directly, and any abrupt power demand that the battery ESS cannot immediately provide due to its bandwidth limitations is forwarded to the ultracapacitor ESS whose current reference is calculated as icuR = icbR − icb.Note that these current commands (icbR and icuR) need to be referred to the battery-side and ultracapacitor-side currents through scaling with respect to individual DC/DC power converter duty cycles as explained in Section 2.3 and elaborated in detail in [41].According to Figure 6, the current reference from the upper-level DC bus PI feedback controller and load compensator should be dynamically distributed between the battery and ultracapacitor ESS to facilitate effective load disturbance suppression of the closed-loop system.Since batteries are typically intended for steady and slowly changing loads [55], the battery ESS current controller should be tuned for slow response (i.e., tuned with large equivalent time constant T eb ).On the other hand, ultracapacitor ESS, being able to provide peak shaving capability, should be equipped with fast-current controller (i.e., characterized by small equivalent lag T eu ).Indeed, within the load distribution strategy in Figure 6 the "slow" battery ESS receives the upper-level command directly, and any abrupt power demand that the battery ESS cannot immediately provide due to its bandwidth limitations is forwarded to the ultracapacitor ESS whose current reference is calculated as i cuR = i cbR − i cb .Note that these current commands (i cbR and i cuR ) need to be referred to the battery-side and ultracapacitor-side currents through scaling with respect to individual DC/DC power converter duty cycles as explained in Section 2.3 and elaborated in detail in [41].
The dynamic model of the current reference distribution scheme in Figure 6 is given by the following transfer function: If the ultracapacitor ESS is characterized by much faster response (T eu << T eb ), the above relationship can be simplified as follows [41]: i.e., the transient dynamics of current supplied to the DC bus are only due to the fast ultracapacitor ESS action characterized by a small lag T eu .For voltage feedback control system design, this relatively small lag may be augmented with the small lag T ∑ corresponding to voltage measurement and sampling effect in the case of digital controller.Based on the above analysis, the DC bus feedback control system transfer function model reads as follows: which yields the following expressions for PI controller parameters: The feed-forward compensator design is aimed at canceling out the dominant lag in the path of the current reference, which yields the result for the compensator lead time constant [42]: while the filtering time constant T f is tuned to achieve a good trade-off between direct compensator response speed and noise attenuation: with the scaling factor α = 0.2 chosen herein.

Traction Motor Current/Torque Control
It is assumed that traction motor electromotive force u emf = pΦ r ω m is compensated for and that the compensation of voltage cross-coupling terms ∆u d = L a i q pω m and ∆u q = L a i d pω m is also included (see Figure 2).In that case the feedback controller design should be the same for both axes of the rotating d-q coordinate frame, because of their symmetrical structures.Typically, in the case of current control loop design the armature time constant T a = L a /R a is canceled out by the current PI controller zero (see [39]): In that case the closed-loop transfer functions of d-q current control systems read as follows: The damping optimum-based design (with n = 2 in Equation ( 13)), results in the following expressions for the current controller proportional gains K cd and K cq and the current control loop equivalent time constant T ei :

Results of Simulation Analysis
The presented control system design has been verified first by means of comprehensive simulation analysis for different scenarios.These included a DC bus load step disturbance and related ESS charging and discharging operation, EV driveline subject to urban-type driving cycles such as NEDC, UDDS, NYCC and California Unified Cycle (also known as LA92 cycle), and abrupt EV acceleration and deceleration commands.The overall EVs simulation model and all sub-models and control systems are implemented within MATLAB/Simulink software environment by using standard blocks and libraries.

Simulation Model Parameterization
The simulation model comprising the hybrid battery/ultracapacitor energy storage equipped with the previously designed DC bus control system and the traction motor drive within the hypothetical EVs is parameterized based on realistic power-train component data obtained from [43,[56][57][58][59].
In addition, for the case of simulation verification based on standard certification driving cycles and abrupt acceleration and deceleration scenarios, it is assumed that vehicle deceleration is predominantly due to traction machine inverter regenerative braking operation.For these scenarios, the traction motor torque reference can be obtained by using a vehicle inertia model extended with rolling resistance and air drag terms, and whose speed is controlled by means of a virtual driver model [60] implemented in the form of a PI controller, as illustrated in Figure 7.The virtual driver PI controller parameters are also determined according to damping optimum, with the assumption that power-train load due to air drag is treated as a slow external disturbance within the vehicle model: where J eq is the equivalent inertia referred to the PMSM traction machine output shaft, i g is the transmission gearbox ratio, r w is the wheel radius, and characteristic ratios D 2dr = D 3dr = 0.5 are chosen to obtain fast and well-damped closed-loop response.
The resulting parameters of the process models and respective controllers are listed in Table 1, whereas Table 2 lists the parameters of the hypothetic EVs and the virtual driver, the parameters of a suitable traction motor (PMSM) characterized by the rated power of 72 kW (see [58]), and the parameters of the corresponding traction motor current/torque control system.Moreover, the battery and ultracapacitor ESS can be sized based on analyzing the catalogue data from [56,57].The resulting analysis has shown that the prospective battery with rated capacity of 32 kWh would be characterized by the mass of 320 kg, and the length of 1.4 m, and would measure 0.73 m in width and 0.22 m in height, thus yielding the total volume of 0.22 m 3 .Similar analysis has yielded the dimensions of ultracapacitor ESS to be 1.29 m in length, 0.62 m in width and 0.22 m in height, thus yielding the overall ultracapacitor ESS volume of 0.22 m 3 , and weight of about 180 kg.

Verification of HESS and DC Bus Control System
The comparative simulation responses of the low-level current control loops within ultracapacitor and battery ESS are shown in Figure 8 for the stepwise discharging command with current reference step magnitude of −10 A. The ultracapacitor current control system is tuned for a fast and well-damped step response according to the damping optimum procedure, resulting in the closed-loop equivalent time constant T eu = 15 ms (Table 1), which yields the response settling time of about 30 ms with less than 6% step response overshoot (Figure 8a).The response speed (bandwidth) of the ultracapacitor current control loop can be arbitrarily slowed down by means of increasing the closed-loop equivalent time constant T eu according to Equation (17). Figure 8a further shows that decreasing the most dominant characteristic ratio D 2i below the optimal value (0.5) results in T eu increase, as well as in increased damping of the closed-loop system.In the case of battery ESS (Figure 8b), two distinctive PI controller tuning cases have been considered with respect to the closed-loop equivalent time constant T eb choices (Figure 8b).Namely, the battery ESS control system can be tuned for rather fast response characterized by favorable response damping (T eb = 20 ms in Figure 8b).However, a more conservative tuning aimed at slower closed response should be preferred because the battery ESS is intended for slowly varying loads.The comparative simulation responses obtained for the "slower" PI controller tuning (with T eb = 200 ms) in Figure 8b, indeed show a ten-fold longer closed-loop transient settling time with respect to "fast" controller tuning.

Verification of HESS and DC Bus Control System
The comparative simulation responses of the low-level current control loops within ultracapacitor and battery ESS are shown in Figure 8 for the stepwise discharging command with current reference step magnitude of −10 A. The ultracapacitor current control system is tuned for a fast and well-damped step response according to the damping optimum procedure, resulting in the closed-loop equivalent time constant Teu = 15 ms (Table 1), which yields the response settling time of about 30 ms with less than 6% step response overshoot (Figure 8a).The response speed (bandwidth) of the ultracapacitor current control loop can be arbitrarily slowed down by means of increasing the closed-loop equivalent time constant Teu according to Equation (17). Figure 8a further shows that decreasing the most dominant characteristic ratio D2i below the optimal value (0.5) results in Teu increase, as well as in increased damping of the closed-loop system.In the case of battery ESS (Figure 8b), two distinctive PI controller tuning cases have been considered with respect to the closed-loop equivalent time constant Teb choices (Figure 8b).Namely, the battery ESS control system can be tuned for rather fast response characterized by favorable response damping (Teb = 20 ms in Figure 8b).However, a more conservative tuning aimed at slower closed response should be preferred because the battery ESS is intended for slowly varying loads.The comparative simulation responses obtained for the "slower" PI controller tuning (with Teb = 200 ms) in Figure 8b, indeed show a ten-fold longer closed-loop transient settling time with respect to "fast" controller tuning.Figure 9 shows the comparative simulation responses of the DC bus control system subject to load current step with the magnitude of 50 A, effectively emulating a sudden 18 kW driveline acceleration command (25% of the traction motor rated power).When PI feedback controller alone is used (Figure 9a), the DC bus voltage is characterized by well-damped dynamic behavior.However, the stepwise disturbance response is characterized by a relatively large voltage drop of 8.9% with respect to the selected DC bus voltage target udcR = 360 V, with the voltage response settling to the target value within 140 ms due to non-negligible lag the feedback loop characterized by the equivalent time constant Tedc = 80 ms (top trace in Figure 9a).The HESS responses (bottom plot in Figure 9a) confirm that the ultracapacitor ESS reacts notably faster compared to the battery ESS within the proposed dynamic load distribution scheme.When the PI controller is augmented by the direct feed-forward compensator (Figure 9b), the DC bus voltage drop after the stepwise load is reduced to 1.7% of the DC bus voltage target due to the fast reaction of the feed-forward compensator, which directly forwards a rather fast-current command to the intermediate-level load distribution scheme.As a result, the load suppression potential of the control system featuring the ultracapacitor ESS equipped with fast-current controller is better used, as opposed to the when only the PI feedback controller is used (see Figure 9a,b).Figure 9 shows the comparative simulation responses of the DC bus control system subject to load current step with the magnitude of 50 A, effectively emulating a sudden 18 kW driveline acceleration command (25% of the traction motor rated power).When PI feedback controller alone is used (Figure 9a), the DC bus voltage is characterized by well-damped dynamic behavior.However, the stepwise disturbance response is characterized by a relatively large voltage drop of 8.9% with respect to the selected DC bus voltage target u dcR = 360 V, with the voltage response settling to the target value within 140 ms due to non-negligible lag the feedback loop characterized by the equivalent time constant T edc = 80 ms (top trace in Figure 9a).The HESS responses (bottom plot in Figure 9a) confirm that the ultracapacitor ESS reacts notably faster compared to the battery ESS within the proposed dynamic load distribution scheme.When the PI controller is augmented by the direct feed-forward compensator (Figure 9b), the DC bus voltage drop after the stepwise load is reduced to 1.7% of the DC bus voltage target due to the fast reaction of the feed-forward compensator, which directly forwards a rather fast-current command to the intermediate-level load distribution scheme.As a result, the load suppression potential of the control system featuring the ultracapacitor ESS equipped with fast-current controller is better used, as opposed to the when only the PI feedback controller is used (see Figure 9a,b).
Figure 10 illustrates the DC bus system behavior for the case when the ultracapacitor ESS is being charged from the common DC bus under the auxiliary ultracapacitor voltage controller, which commands appropriate current command to the ultracapacitor ESS current control system.Since the auxiliary controller output is limited to avoid excessive DC bus loads for the purpose of ultracapacitor ESS voltage control, the ultracapacitor ESS represents a near-constant DC load throughout most of the charging transient, which results in a linear rise of the ultracapacitor terminal voltage towards the target value u uR = 300 V (top plot Figure 10a).The DC bus voltage response is characterized by an initial voltage drop (bottom plot in Figure 10a) corresponding to the ultracapacitor ESS load being demanded by the auxiliary controller (top plot in Figure 10b).As indicated by the battery ESS response (bottom plot in Figure 10b), the required ultracapacitor charging current is provided by the battery ESS, which points out to effective load distribution performed by the intermediate-level control scheme in Figure 6.
Energies 2018, 11, x FOR PEER REVIEW 15 of 27 Figure 10 illustrates the DC bus system behavior for the case when the ultracapacitor ESS is being charged from the common DC bus under the auxiliary ultracapacitor voltage controller, which commands appropriate current command to the ultracapacitor ESS current control system.Since the auxiliary controller output is limited to avoid excessive DC bus loads for the purpose of ultracapacitor ESS voltage control, the ultracapacitor ESS represents a near-constant DC load throughout most of the charging transient, which results in a linear rise of the ultracapacitor terminal voltage towards the target value uuR = 300 V (top plot Figure 10a).The DC bus voltage response is characterized by an initial voltage drop (bottom plot in Figure 10a) corresponding to the ultracapacitor ESS load being demanded by the auxiliary controller (top plot in Figure 10b).As indicated by the battery ESS response (bottom plot in Figure 10b), the required ultracapacitor charging current is provided by the battery ESS, which points out to effective load distribution performed by the intermediate-level control scheme in Figure 6.

Driving Cycle-Based Analysis
Figure 11 shows the simulation results of the vehicle model equipped with the virtual driver for the chosen certification driving cycles, i.e., NEDC, UDDS, LA92 and NYCC (see e.g., [15,48]).The driving cycle data are obtained from the US Environmental Protection Agency (EPA) website [48] and have been downloaded as vehicle speed over time traces in ASCII format, and used within the MATLAB/Simulink simulation environment.Since NEDC cycle comprises an interval of urban-like driving (frequent vehicle starting and stopping), followed by a highway-like driving and final rapid deceleration, vehicle driveline is characterized by notable driveline torque τd and vehicle speed v Figure 10 illustrates the DC bus system behavior for the case when the ultracapacitor ESS is being charged from the common DC bus under the auxiliary ultracapacitor voltage controller, which commands appropriate current command to the ultracapacitor ESS current control system.Since the auxiliary controller output is limited to avoid excessive DC bus loads for the purpose of ultracapacitor ESS voltage control, the ultracapacitor ESS represents a near-constant DC load throughout most of the charging transient, which results in a linear rise of the ultracapacitor terminal voltage towards the target value uuR = 300 V (top plot Figure 10a).The DC bus voltage response is characterized by an initial voltage drop (bottom plot in Figure 10a) corresponding to the ultracapacitor ESS load being demanded by the auxiliary controller (top plot in Figure 10b).As indicated by the battery ESS response (bottom plot in Figure 10b), the required ultracapacitor charging current is provided by the battery ESS, which points out to effective load distribution performed by the intermediate-level control scheme in Figure 6.

Driving Cycle-Based Analysis
Figure 11 shows the simulation results of the vehicle model equipped with the virtual driver for the chosen certification driving cycles, i.e., NEDC, UDDS, LA92 and NYCC (see e.g., [15,48]).The driving cycle data are obtained from the US Environmental Protection Agency (EPA) website [48] and have been downloaded as vehicle speed over time traces in ASCII format, and used within the MATLAB/Simulink simulation environment.Since NEDC cycle comprises an interval of urban-like driving (frequent vehicle starting and stopping), followed by a highway-like driving and final rapid deceleration, vehicle driveline is characterized by notable driveline torque τd and vehicle speed v

Driving Cycle-Based
Figure 11 shows the simulation results of the vehicle model equipped with the virtual driver for the chosen certification driving cycles, i.e., NEDC, UDDS, LA92 and NYCC (see e.g., [15,48]).The driving cycle data are obtained from the US Environmental Protection Agency (EPA) website [48] and have been downloaded as vehicle speed over time traces in ASCII format, and used within the MATLAB/Simulink simulation environment.Since NEDC cycle comprises an interval of urban-like driving (frequent vehicle starting and stopping), followed by a highway-like driving and final rapid deceleration, vehicle driveline is characterized by notable driveline torque τ d and vehicle speed v variations.The aforementioned torque variations are even more emphasized for the UDDS cycle (see Figure 11a).Similar result is obtained for the cases of LA92 and NYCC driving cycles, wherein the former combines high-speed and low-speed driving with rather abrupt and frequent vehicle acceleration and deceleration, while the latter is characterized by frequent starting and stopping, albeit at lower vehicle speeds characteristic to congested traffic conditions (Figure 11b).The traction motor phase voltage U ph and active current component I ph •cos(φ) traces shown in Figure 11  variations.The aforementioned torque variations are even more emphasized for the UDDS cycle (see Figure 11a).Similar result is obtained for the cases of LA92 and NYCC driving cycles, wherein the former combines high-speed and low-speed driving with rather abrupt and frequent vehicle acceleration and deceleration, while the latter is characterized by frequent starting and stopping, albeit at lower vehicle speeds characteristic to congested traffic conditions (Figure 11b).Figure 12 shows the corresponding load current iL and DC voltage profiles udc for the individual cases of vehicle driveline and traction motor inverter responses in Figure 11.The comparative DC bus voltage responses in Figure 12 indicate that NEDC driving cycle is characterized by a notable DC bus voltage target increase above the lower threshold Umin = 328 V in the final, highway-like driving interval (top plot in Figure 12a).Namely, this increased DC bus voltage is needed to cover for increased traction motor voltage demand corresponding to high motor (and vehicle) speeds characterized by high motor back-EMF values.Similar requirement with respect to DC bus voltage reference is also observed in the case of LA92 cycle when the vehicle speed increases above the 80 km/h (check traces in Figures 11b and 12c).The UDDS and NYCC driving cycles, being characterized by vehicle speeds below 80 km/h, do not mandate DC bus voltage increase above the lower threshold Umin, as indicated by traces in Figure 12b,d.Moreover, all driving cycles are characterized by notably smaller DC bus voltage tracking errors when direct feed-forward compensator is used, as opposed to the case when PI feedback controller has not been augmented by the feed-forward load compensating action.This is also illustrated by DC bus load current tracking error Δic = − (iL + ic) traces in bottom plots in Figure 12a,d, wherein a notable reduction of load current tracking error magnitudes is observed when direct feed-forward compensator is used.12 indicate that NEDC driving cycle is characterized by a notable DC bus voltage target increase above the lower threshold U min = 328 V in the final, highway-like driving interval (top plot in Figure 12a).Namely, this increased DC bus voltage is needed to cover for increased traction motor voltage demand corresponding to high motor (and vehicle) speeds characterized by high motor back-EMF values.Similar requirement with respect to DC bus voltage reference is also observed in the case of LA92 cycle when the vehicle speed increases above the 80 km/h (check traces in Figures 11b and 12c).The UDDS and NYCC driving cycles, being characterized by vehicle speeds below 80 km/h, do not mandate DC bus voltage increase above the lower threshold U min , as indicated by traces in Figure 12b,d.Moreover, all driving cycles are characterized by notably smaller DC bus voltage tracking errors when direct feed-forward compensator is used, as opposed to the case when PI feedback controller has not been augmented by the feed-forward load compensating action.This is also illustrated by DC bus load current tracking error ∆i c = − (i L + i c ) traces in bottom plots in Figure 12a,d, wherein a notable reduction of load current tracking error magnitudes is observed when direct feed-forward compensator is used.The above conclusions are further strengthened by the comparative DC bus voltage tracking error and load tracking error indices, shown in Figure 13.In particular, when PI controller is used alone, the more dynamic UDDS and LA92 driving cycles are characterized by somewhat larger DC bus voltage tracking errors compared to the case of NEDC, and especially with respect to relatively low-speed NYCC driving cycle (see Figure 13a,b).As expected, introduction of feed-forward load compensator results in notable decrease of DC voltage target tracking error, especially in the case of the highly dynamic UDDS driving cycle.The LA92 driving cycle, on the other hand, is characterized by the least emphasized reduction of maximum voltage tracking error, which is due to two rather dynamic (high-bandwidth) DC bus voltage and load profiles (t between 6.5 s and 8.2 s and t between 14.5 s and 15.7 s in Figure 12c), which relates to higher magnitudes of the maximum DC bus and load current tracking indices in Figure 13a,c.Nevertheless, it may be concluded that in general the feed-forward load compensator, being able to directly react to readily available traction motor torque command (see feed-forward path Figure 6), should be capable of timely commanding precise current demand to the common DC bus, thus improving the anticipated load current tracking ability of the overall control system (as shown in Figures 12 and 13), and to effectively suppress the majority of DC bus voltage excursions in a systematic manner.The above conclusions are further strengthened by the comparative DC bus voltage tracking error and load tracking error indices, shown in Figure 13.In particular, when PI controller is used alone, the more dynamic UDDS and LA92 driving cycles are characterized by somewhat larger DC bus voltage tracking errors compared to the case of NEDC, and especially with respect to relatively low-speed NYCC driving cycle (see Figure 13a,b).As expected, introduction of feed-forward load compensator results in notable decrease of DC voltage target tracking error, especially in the case of the highly dynamic UDDS driving cycle.The LA92 driving cycle, on the other hand, is characterized by the least emphasized reduction of maximum voltage tracking error, which is due to two rather dynamic (high-bandwidth) DC bus voltage and load profiles (t between 6.5 s and 8.2 s and t between 14.5 s and 15.7 s in Figure 12c), which relates to higher magnitudes of the maximum DC bus and load current tracking indices in Figure 13a,c.Nevertheless, it may be concluded that in general the feed-forward load compensator, being able to directly react to readily available traction motor torque command (see feed-forward path Figure 6), should be capable of timely commanding precise current demand to the common DC bus, thus improving the anticipated load current tracking ability of the overall control system (as shown in Figures 12 and 13), and to effectively suppress the majority of DC bus voltage excursions in a systematic manner.

Analysis for EV Constant Acceleration/Deceleration Regime
The proposed DC bus control strategy, with feed-forward load compensator included, has also been tested for the EVs subject to abrupt acceleration and deceleration regimes, and the comparative results are shown in Figure 14.The responses are characterized by abrupt changes of driveline torque followed by quasi-steady-state torque demand during acceleration and deceleration phases (Figure 14a), which apparently represents a kind of a worst-case scenario for the DC bus control strategy.Namely, the aforementioned driveline torque profile results in relatively slow ramp-like profile of DC bus load iL during steady acceleration and deceleration, whereas abrupt DC load changes occur at the vehicle acceleration to deceleration (reversal) point (Figure 14b).Note also that the sudden DC bus voltage drop at reversal from acceleration to deceleration command is needed to facilitate reduced motor phase and DC bus voltage required during transient from driving to regenerative braking.The aforementioned abrupt DC bus load iL transient is, as expected, effectively handled by the ultracapacitor ESS, while the gradual ramp-like DC bus load profiles (during constant acceleration/deceleration) are handled by the battery ESS.

for EV Constant Acceleration/Deceleration Regime
The proposed DC bus control strategy, with feed-forward load compensator included, has also been tested for the EVs subject to abrupt acceleration and deceleration regimes, and the comparative results are shown in Figure 14.The responses are characterized by abrupt changes of driveline torque followed by quasi-steady-state torque demand during acceleration and deceleration phases (Figure 14a), which apparently represents a kind of a worst-case scenario for the DC bus control strategy.Namely, the aforementioned driveline torque profile results in relatively slow ramp-like profile of DC bus load i L during steady acceleration and deceleration, whereas abrupt DC load changes occur at the vehicle acceleration to deceleration (reversal) point (Figure 14b).Note also that the sudden DC bus voltage drop at reversal from acceleration to deceleration command is needed to facilitate reduced motor phase and DC bus voltage required during transient from driving to regenerative braking.The aforementioned abrupt DC bus load i L transient is, as expected, effectively handled by the ultracapacitor ESS, while the gradual ramp-like DC bus load profiles (during constant acceleration/deceleration) are handled by the battery ESS.

Analysis for EV Constant Acceleration/Deceleration Regime
The proposed DC bus control strategy, with feed-forward load compensator included, has also been tested for the EVs subject to abrupt acceleration and deceleration regimes, and the comparative results are shown in Figure 14.The responses are characterized by abrupt changes of driveline torque followed by quasi-steady-state torque demand during acceleration and deceleration phases (Figure 14a), which apparently represents a kind of a worst-case scenario for the DC bus control strategy.Namely, the aforementioned driveline torque profile results in relatively slow ramp-like profile of DC bus load iL during steady acceleration and deceleration, whereas abrupt DC load changes occur at the vehicle acceleration to deceleration (reversal) point (Figure 14b).Note also that the sudden DC bus voltage drop at reversal from acceleration to deceleration command is needed to facilitate reduced motor phase and DC bus voltage required during transient from driving to regenerative braking.The aforementioned abrupt DC bus load iL transient is, as expected, effectively handled by the ultracapacitor ESS, while the gradual ramp-like DC bus load profiles (during constant acceleration/deceleration) are handled by the battery ESS.

Results of Experimental Verification
The core of the DC bus control system has also been verified by means of experiments conducted on the dedicated down-scaled laboratory setup, previously designed and tested in [40,41].Figure 15 shows the principal schematic of the laboratory setup which can be externally supplied from the AC grid, or can work in the isolated (islanded) mode.Setup comprises three two-quadrant (buck-boost) DC/DC power converters connected in parallel to the common DC bus, wherein two of those power converters are used for power flow control of the battery and ultracapacitor module-based ESS, and the third power converter is used to emulate a passive or active DC bus load by supplying power to the dissipation resistor or an another battery.Due to safety concerns, the safety and diagnostics system implemented within the programmable logic controller (PLC) limits the DC voltage to 45 V, while the under-voltage trip is pre-set to 30 V. Battery and ultracapacitor ESS current control, and DC bus voltage control algorithms are implemented within an inexpensive PLC, whereas the DC bus load control, and data collection and supervision of the laboratory setup is implemented within the National Instruments LabView environment by using a CompactRIO acquisition and control system.The parameters of the down-scaled laboratory setup and the corresponding DC bus control system are listed in Table 3.

Results of Experimental Verification
The core of the DC bus control system has also been verified by means of experiments conducted on the dedicated down-scaled laboratory setup, previously designed and tested in [40,41].Figure 15 shows the principal schematic of the laboratory setup which can be externally supplied from the AC grid, or can work in the isolated (islanded) mode.Setup comprises three two-quadrant (buck-boost) DC/DC power converters connected in parallel to the common DC bus, wherein two of those power converters are used for power flow control of the battery and ultracapacitor module-based ESS, and the third power converter is used to emulate a passive or active DC bus load by supplying power to the dissipation resistor or an another battery.Due to safety concerns, the safety and diagnostics system implemented within the programmable logic controller (PLC) limits the DC voltage to 45 V, while the under-voltage trip is pre-set to 30 V. Battery and ultracapacitor ESS current control, and DC bus voltage control algorithms are implemented within an inexpensive PLC, whereas the DC bus load control, and data collection and supervision of the laboratory setup is implemented within the National Instruments LabView environment by using a CompactRIO acquisition and control system.The parameters of the down-scaled laboratory setup and the corresponding DC bus control system are listed in Table 3.The results of experimental verification of the DC bus control system for the case of abrupt (stepwise) DC bus load and load profile corresponding to the NEDC driving cycle are shown in Figure 16a,b, respectively.Due to the aforementioned safety features, the DC bus voltage has been pre-set in both cases in the middle of the usable voltage range (i.e., u dcR = 37.5 V is used).For the same reason, the final part of the NEDC certification cycle, corresponding to the final accelerating of the vehicle towards 120 km/h and subsequent abrupt braking have been omitted from the analysis to avoid tripping the over-voltage and under-voltage protections at the laboratory setup.
rather fast response of the DC bus control system and the inner current control loops of individual ESSs (i.e., battery and ultracapacitor).As expected, the use of DC bus control system comprising both the PI feedback controller and the direct load compensator results in notably smaller DC bus voltage drop and faster DC bus voltage recovery compared to the case when PI feedback controller is used alone.This is further confirmed by the comparative traces obtained for the case of down-scaled DC bus load corresponding to EV driveline subject to highly dynamic NEDC certification cycle.In particular, the feed-forward compensator-based control system load suppression ability, expressed in terms of DC bus voltage reference tracking root mean squared (RMS) error, is over five-fold improved compared to the case when only PI feedback controller is used.As explained earlier, this is primarily due to the better use of load suppression potential of the ultracapacitor ESS featuring a fast current controller under the fast current demand from the direct feed-forward load compensator.

Discussion and Concluding Remarks
This paper has presented the design of EV DC bus control system based on a battery/ultracapacitor HESS, and its coordination with the fully electrified vehicle driveline control system via the readily available traction motor current and voltage variables.The control strategy has included the upper-level DC bus voltage feedback PI controller augmented with a direct load compensator for fast suppression of abrupt DC bus loads, which have commanded appropriate current references to the battery/ultracapacitor HESS via the intermediate-level dynamic load distribution scheme.The feedback control design has been carried out by using the damping optimum criterion.The proposed methodology has been verified by means of simulations for The comparative results in Figure 16a, obtained for stepwise load current change with the step magnitude of 4 A, indeed show that the proposed control system design results in well-damped and rather fast response of the DC bus control system and the inner current control loops of individual ESSs (i.e., battery and ultracapacitor).As expected, the use of DC bus control system comprising both the PI feedback controller and the direct load compensator results in notably smaller DC bus voltage drop and faster DC bus voltage recovery compared to the case when PI feedback controller is used alone.This is further confirmed by the comparative traces obtained for the case of down-scaled DC bus load corresponding to EV driveline subject to highly dynamic NEDC certification cycle.In particular, the feed-forward compensator-based control system load suppression ability, expressed in terms of DC bus voltage reference tracking root mean squared (RMS) error, is over five-fold improved compared to the case when only PI feedback controller is used.As explained earlier, this is primarily due to the better use of load suppression potential of the ultracapacitor ESS featuring a fast current controller under the fast current demand from the direct feed-forward load compensator.

Discussion and Concluding Remarks
This paper has presented the design of EV DC bus control system based on a battery/ultracapacitor HESS, and its coordination with the fully electrified vehicle driveline control system via the readily available traction motor current and voltage variables.The control strategy has included the upper-level DC bus voltage feedback PI controller augmented with a direct load compensator for fast suppression of abrupt DC bus loads, which have commanded appropriate current references to the battery/ultracapacitor HESS via the intermediate-level dynamic load distribution scheme.The feedback control design has been carried out by using the damping optimum criterion.The proposed methodology has been verified by means of simulations for different realistic EV-operating regimes, and experimentally on the down-scaled DC bus laboratory setup.Simulation and experimental results have pointed out to: 1.
Damping optimum tuning approach having been able to ensure well-damped closed-loop behavior of designed feedback systems (i.e., less than 6% step response overshoot).It has also been able to precisely adjust the closed-loop response speed of battery/ultracapacitor HESS inner current control loops via the choice of the closed-loop equivalent time constant.This has enabled rather fast-current reference tracking of the ultracapacitor ESS (30 ms step response settling time has been obtained), while also achieving notably slower battery ESS response (characterized by 400 ms response time) within the DC bus control system.2.
The load suppression ability of the overall DC bus control system having been notably improved by the introduction of the direct load compensator, which has typically resulted in three to five times smaller DC bus voltage excursion after an abrupt DC bus load.In particular, for the realistic scenario of 25% stepwise change of EV driveline load, DC voltage excursion is reduced from 8.9% of the target DC bus voltage value in the case of PI feedback controller to 1.7% in the case when PI controller has been augmented by the load compensator based on DC bus load reconstruction from traction motor variables.

3.
The DC bus voltage target tracking performance having benefited from the inclusion of direct feed-forward load compensator for different certification driving cycles and corresponding DC bus voltage profiles calculated from traction motor variables.Namely, use of direct feed-forward load compensator has resulted in the reduction of the maximum DC bus voltage tracking error from 3.87% to 1.16% of the DC voltage target in the case of NEDC driving cycle, and from 4.93% to just 0.15% in the case of UDDS scenario.Similar reduction has also been observed for NYCC driving scenario (i.e., from 1.37% to just 0.03% has been obtained), whereas LA92 driving cycle has been characterized by the DC bus excursion reduction from 4.27% to 3.15%.Generally speaking, the DC bus voltage average tracking error has been reduced between one and two orders of magnitude for all driving cycles when load compensator has been used.
Future research may be directed towards the extension of the proposed control strategy for multiple energy storages, and related applications in renewable energy systems and EVs.

Figure 1 .
Figure 1.Considered EV power-train with parallel-connected battery and ultracapacitor ESS and vehicle traction AC electrical drive based on permanent-magnet synchronous motor (PMSM).

Figure 1 .
Figure 1.Considered EV power-train with parallel-connected battery and ultracapacitor ESS and vehicle traction AC electrical drive based on permanent-magnet synchronous motor (PMSM).
kT = 1.5pΦr being the motor torque constant.

Figure 2 .
Figure 2. Block diagram of d-q coordinate frame current control system for inverter-fed PMSM traction motor operating below rated speed.

Figure 2 .
Figure 2. Block diagram of d-q coordinate frame current control system for inverter-fed PMSM traction motor operating below rated speed.

Figure 3 .
Figure 3. Illustration of voltage and current relationships at semiconductor switches T1 and T2 and fly-wheeling diodes D1 and D2, and input/output current and voltage relationships of two-quadrant DC/DC power converter for buck operation (a) and boost operation (b).

Figure 3 .
Figure 3. Illustration of voltage and current relationships at semiconductor switches T1 and T2 and fly-wheeling diodes D1 and D2, and input/output current and voltage relationships of two-quadrant DC/DC power converter for buck operation (a) and boost operation (b).

Figure 4 .
Figure 4. Current control loops for battery ESS (a) and ultracapacitor ESS (b), featuring feedback PI controller, simplified power converter model with embedded inductor and simplified ESS models.

Figure 4 .
Figure 4. Current control loops for battery ESS (a) and ultracapacitor ESS (b), featuring feedback PI controller, simplified power converter model with embedded inductor and simplified ESS models.

Figure 5 .
Figure 5. Block diagram of ultracapacitor terminal voltage control system featuring a feedback PI controller commanding an additional current reference to inner ultracapacitor current control loop.

Figure 5 .
Figure 5. Block diagram of ultracapacitor terminal voltage control system featuring a feedback PI controller commanding an additional current reference to inner ultracapacitor current control loop.

Figure 6 .
Figure 6.DC bus control system block diagram representation featuring DC bus voltage target calculation from motor phase voltage demand, DC bus load feed-forward compensator and DC bus voltage feedback PI controller commanding the dynamic load distribution scheme.

Figure 6 .
Figure 6.DC bus control system block diagram representation featuring DC bus voltage target calculation from motor phase voltage demand, DC bus load feed-forward compensator and DC bus voltage feedback PI controller commanding the dynamic load distribution scheme.

Figure 7 .
Figure 7. Vehicle dynamics model comprising equivalent vehicle inertia, rolling resistance and air drag effect referred to the motor side, controlled by a PI controller-based virtual driver.

Figure 8 .
Figure 8. Results of simulation analysis of ultracapacitor ESS (a) and battery ESS (b) current control systems, illustrating the damping optimum tuning procedure and its ability to arbitrarily adjust closed-loop response speed.

Figure 8 .
Figure 8. Results of simulation analysis of ultracapacitor ESS (a) and battery ESS (b) current control systems, illustrating the damping optimum tuning procedure and its ability to arbitrarily adjust closed-loop response speed.

Figure 9 .Figure 10 .
Figure 9. DC bus control voltage and battery/ultracapacitor ESS current simulation results for abrupt load current change when PI controller is used alone (a), and with direct feed-forward load compensator (b).

Figure 9 .
Figure 9. DC bus control voltage and battery/ultracapacitor ESS current simulation results for abrupt load current change when PI controller is used alone (a), and with direct feed-forward load compensator (b).

Figure 9 .Figure 10 .
Figure 9. DC bus control voltage and battery/ultracapacitor ESS current simulation results for abrupt load current change when PI controller is used alone (a), and with direct feed-forward load compensator (b).

Figure 10 .
Figure 10.Simulation responses of ultracapacitor auxiliary voltage control system: ultracapacitor and DC bus voltage traces (a) and battery/ultracapacitor ESS current responses (b).
closely reflect the above vehicle speed and driveline torque profiles.Energies 2018, 11, x FOR PEER REVIEW 16 of 27

Figure 11 .
Figure 11.Simulation responses of vehicle speed, driveline torque, traction motor phase voltage and active current component traces for NEDC and UDDS driving cycles (a) and LA92 and NYCC driving cycles (b).

Figure 11 .
Figure 11.Simulation responses of vehicle speed, driveline torque, traction motor phase voltage and active current component traces for NEDC and UDDS driving cycles (a) and LA92 and NYCC driving cycles (b).

Figure 12
Figure12shows the corresponding load current i L and DC voltage profiles u dc for the individual cases of vehicle driveline and traction motor inverter responses in Figure11.The comparative DC bus voltage responses in Figure12indicate that NEDC driving cycle is characterized by a notable DC bus voltage target increase above the lower threshold U min = 328 V in the final, highway-like driving interval (top plot in Figure12a).Namely, this increased DC bus voltage is needed to cover for increased traction motor voltage demand corresponding to high motor (and vehicle) speeds characterized by high motor back-EMF values.Similar requirement with respect to DC bus voltage reference is also observed in the case of LA92 cycle when the vehicle speed increases above the 80 km/h (check traces in Figures11b and 12c).The UDDS and NYCC driving cycles, being characterized by vehicle speeds below 80 km/h, do not mandate DC bus voltage increase above the lower threshold U min , as indicated by traces in Figure12b,d.Moreover, all driving cycles are characterized by notably smaller DC bus voltage tracking errors when direct feed-forward compensator is used, as opposed to the case when PI feedback controller has not been augmented by the feed-forward load compensating action.This is also illustrated by DC bus load current tracking error ∆i c = − (i L + i c ) traces in bottom plots in Figure12a,d, wherein a notable reduction of load current tracking error magnitudes is observed when direct feed-forward compensator is used.

Figure 12 .
Figure 12.DC bus voltage, load current responses and load current tracking error traces obtained by means of vehicle simulation model for different certification driving cycles: NEDC (a), UDDS (b), LA92 (c) and NYCC (d).

Figure 12 .
Figure 12.DC bus voltage, load current responses and load current tracking error traces obtained by means of vehicle simulation model for different certification driving cycles: NEDC (a), UDDS (b), LA92 (c) and NYCC (d).

Figure 13 .
Figure 13.DC bus voltage maximum error (a) and average error (b), load current maximum tracking error (c) and average tracking error (d) quality indices for NEDC, UDDS, LA92, and NYCC driving cycles.

Figure 14 .
Figure 14.Simulation results for alternating constant acceleration/constant deceleration commands: vehicle speed and driveline torque (a) and DC bus load current and voltage profiles (b).

Figure 13 .
Figure 13.DC bus voltage maximum error (a) and average error (b), load current maximum tracking error (c) and average tracking error (d) quality indices for NEDC, UDDS, LA92, and NYCC driving cycles.

Figure 13 .
Figure 13.DC bus voltage maximum error (a) and average error (b), load current maximum tracking error (c) and average tracking error (d) quality indices for NEDC, UDDS, LA92, and NYCC driving cycles.

Figure 14 .
Figure 14.Simulation results for alternating constant acceleration/constant deceleration commands: vehicle speed and driveline torque (a) and DC bus load current and voltage profiles (b).

Figure 14 .
Figure 14.Simulation results for alternating constant acceleration/constant deceleration commands: vehicle speed and driveline torque (a) and DC bus load current and voltage profiles (b).

Figure 15 .
Figure 15.Principal schematic representation of DC bus control system down-scaled laboratory setup featuring three independently controlled DC/DC power converters, battery and ultracapacitor energy storages and variable load, and PLC-based DC bus control system and NI CompactRIO-based supervisory system.

Figure 15 .
Figure 15.Principal schematic representation of DC bus control system down-scaled laboratory setup featuring three independently controlled DC/DC power converters, battery and ultracapacitor energy storages and variable load, and PLC-based DC bus control system and NI CompactRIO-based supervisory system.

Figure 16 .
Figure 16.Comparative experimental results of DC bus control system without and with direct feed-forward load compensator: stepwise load change (a) and scaled-down NEDC-like load profile (b).

Figure 16 .
Figure 16.Comparative experimental results of DC bus control system without and with direct feed-forward load compensator: stepwise load change (a) and scaled-down NEDC-like load profile (b).

Table 1 .
Parameters of DC bus control system simulation model.
0.1 Ω Ultracapacitor ESS equivalent lag Teu 15 ms Rated voltage of battery Ub 320 V Battery ESS equivalent lag Teb 200 ms Rated charge capacity of battery Qb 100 Ah Voltage reference scaling factor κκu 1.1 Battery internal resistance Rb 0.08 Ω Feed-forward lead time constant Tff 15 ms Ultracapacitor voltage limit Uu,max 375 V DC bus voltage lower limit Umin 328 V Ultracapacitor rated capacitance Cu 21 F DC bus voltage upper limit Umax 690 V Ultracapacitor resistance Ru 45 mΩ DC bus parasitic lag T∑ 5 ms Ultracapacitor ESS current controller (fast) proportional gain Kci 1.78 V/A Ultracapacitor ESS current controller (fast) integral time constant Tci

Table 2 .
EV power-train simulation model parameters.Vehicle dynamics model comprising equivalent vehicle inertia, rolling resistance and air drag effect referred to the motor side, controlled by a PI controller-based virtual driver.

Table 1 .
Parameters of DC bus control system simulation model.
b 100 Ah Voltage reference scaling factor κκ u 1.1 Battery internal resistance R b 0.08 Ω Feed-forward lead time constant T ff 15 ms Ultracapacitor voltage limit U u,max 375 V DC bus voltage lower limit U min 328 V Ultracapacitor rated capacitance C u 21 F DC bus voltage upper limit U max 690 V Ultracapacitor resistance R u 45 mΩ DC bus parasitic lag T ∑ 5 ms Ultracapacitor ESS current controller (fast) proportional gain K ci 1.78 V/A Ultracapacitor ESS current controller (fast) integral time constant T ci 13 ms

Table 2 .
EV power-train simulation model parameters.

Table 3 .
Parameters of DC bus control system for down-scaled laboratory setup.

Table 3 .
Parameters of DC bus control system for down-scaled laboratory setup.
Battery and ultracapacitor ESS DC/DC power converter output voltage u dR , u qR Direct and quadrature axis voltage components u dR , u qR Direct and quadrature axis voltage references from PI current controllers u uR Ultracapacitor ESS voltage reference Motor and wheel inertia, respectively J eq Equivalent inertia at PMSM rotor side k E , k T PMSM electromotive force and torque constants, respectively K ca , T ca Auxiliary ultracapacitor ESS state-of-charge controller gain and integral time constant K cd , K cq PMSM current controller proportional gains K ci , T ci Battery and ultracapacitor ESS current controller gain and integral time constant K dc , T dc DC bus controller proportional gain and integral time constant K dr , T dr Virtual driver proportional gain and integral time constant L a , R a PMSM armature inductance and resistance L c , R c Voltage response delay of DC/DC power converter and motor inverter T e Closed-loop equivalent time constant T ea Equivalent time constant of the auxiliary ultracapacitor state-of-charge control loop T ei Equivalent time constant of the PMSM current control loop T cd , T cq PMSM current controller integral time constants T eb , T eu Equivalent time constants of battery and ultracapacitor current control loops T fi , T fv Current and voltage measurement (filter) time constants T f , T FF Feed-forward load compensator lag time constant and lead time constant T ∑ Parasitic time constant of the voltage control loop T ∑i Parasitic time constant of the current control loop T ∑u Parasitic time constant of the auxiliary state-of-charge control loop U min DC bus voltage lower bound U max DC bus voltage upper bound