Power Decoupling of a Single Phase DC-AC Dual Active Bridge Converter Based on an Integrated Bidirectional Buck / Boost Stage

Jiatu Hong 1,2, Mahinda Vilathgamuwa 2, Jian Yin 1,* , Yitao Liu 1 , Jianchun Peng 1 and Hui Jiang 3 1 College of Mechatronics and Control Engineering, Shenzhen University, Shenzhen 518060, China; jiatu.hong@connect.qut.edu.au (J.H.); liuyt@szu.edu.cn (Y.L.); jcpeng@szu.edu.cn (J.P.) 2 Department of Electrical Engineering and Computer Science, Queensland University of Technology, Brisbane 4001, Australia; mahinda.vilathgamuwa@qut.edu.au 3 College of Optoelectronic Engineering, Shenzhen University, Shenzhen 518060, China; huijiang@szu.edu.cn * Correspondence: jyin@szu.edu.cn; Tel.: +86-755-2690-5532

In single phase DC-AC systems, high power ripple appears at the DC side due to the double-line-frequency characteristics of the transmission power at the AC side.In some situations such as photovoltaic applications, more stable transmission power is required to achieve high accuracy of maximum power point tracking (MPPT).If a large electrolytic capacitor is simply used at the DC side, the power density and the reliability of the converter can be decreased significantly and it is not able to completely eliminate the ripple power.If a battery serves at the DC side, the double-line-frequency charging or discharging current would decrease the lifetime of the battery [12,13].To eliminate the double-line-frequency ripple power at the DC side in single phase power converters, different power decoupling techniques are introduced [14,15].However, most of the proposed active power decoupling topologies require additional power switches which not only decrease the power density and reliability of the converter, but also bring more cost.The concept of the "parasitic" boost-integrated phase-shift full-bridge converter is proposed in [16].Two boost-integrated and unidirectional DC-DC Energies 2018, 11, 2746 2 of 16 topologies, i.e., the symmetric and asymmetric full-bridge converters are presented for specific multi-port applications with one or two integrated boost stages respectively.Compared with the symmetric topology [17], a DC block capacitor in the HF (high frequency) link is indispensable for the asymmetric topology as the average voltage difference between the phase-nodes appears in this case.By adjusting the duty cycles of the legs, bidirectional power flow is realized for the two ports at the primary side of the HF transformer.Similar with the asymmetric topology presented in [16], an active power decoupling method is introduced for CLLC-type resonant DC-AC DAB converter operating in open loop, which is able to effectively realize power decoupling and reduce the capacitance requirement of the converter [18].In this case, the double-line-frequency ripple power is effectively steered into the passive power decoupling capacitor by adjusting the duty cycle of the modulated leg.Based on this, if the duty cycle of the modulated leg can be appropriately controlled, then the double-line-frequency ripple power can be eliminated due to the mentioned bidirectional power transfer characteristic between the passive energy storage capacitor and the DC source.Therefore, a constant charging or discharging current of the battery can be achieved.
This paper presents the power decoupling of a single phase DC-AC dual active bridge converter based on the integrated bidirectional uni-phase buck/boost stage.The double-line-frequency ripple power is effectively eliminated by the proposed control method on the duty cycle of the bridge leg.The mathematical model of the proposed converter is analyzed in Section 2. The analysis of the control strategy for the proposed converter is presented in Section 3. Simulation and experimental results are illustrated in Section 4. Conclusions are given in Section 5.

Mathematical Model of the Converter
The proposed converter is shown in Figure 1.This is a single-stage DC-AC DAB converter with a pseudo intermediate DC link between the synchronous rectifier and the dual active bridges, which is free of the large electrolytic capacitor at the DC link required for the dual-stage DC-AC converter.The AC voltage v g is folded into the voltage v DC1 with a frequency twice that of the AC voltage, which is given by v DC1 = v g = V g sin ω g t where V g is the magnitude of v g and ω g is the angular frequency of v g .
Energies 2018, 11, x FOR PEER REVIEW 2 of 16 density and reliability of the converter, but also bring more cost.The concept of the "parasitic" boostintegrated phase-shift full-bridge converter is proposed in [16].Two boost-integrated and unidirectional DC-DC topologies, i.e., the symmetric and asymmetric full-bridge converters are presented for specific multi-port applications with one or two integrated boost stages respectively.Compared with the symmetric topology [17], a DC block capacitor in the HF (high frequency) link is indispensable for the asymmetric topology as the average voltage difference between the phasenodes appears in this case.By adjusting the duty cycles of the legs, bidirectional power flow is realized for the two ports at the primary side of the HF transformer.Similar with the asymmetric topology presented in [16], an active power decoupling method is introduced for CLLC-type resonant DC-AC DAB converter operating in open loop, which is able to effectively realize power decoupling and reduce the capacitance requirement of the converter [18].In this case, the double-line-frequency ripple power is effectively steered into the passive power decoupling capacitor by adjusting the duty cycle of the modulated leg.Based on this, if the duty cycle of the modulated leg can be appropriately controlled, then the double-line-frequency ripple power can be eliminated due to the mentioned bidirectional power transfer characteristic between the passive energy storage capacitor and the DC source.Therefore, a constant charging or discharging current of the battery can be achieved.This paper presents the power decoupling of a single phase DC-AC dual active bridge converter based on the integrated bidirectional uni-phase buck/boost stage.The double-line-frequency ripple power is effectively eliminated by the proposed control method on the duty cycle of the bridge leg.The mathematical model of the proposed converter is analyzed in Section 2. The analysis of the control strategy for the proposed converter is presented in Section 3. Simulation and experimental results are illustrated in Section 4. Conclusions are given in Section 5.

Mathematical Model of the Converter
The proposed converter is shown in Figure 1.This is a single-stage DC-AC DAB converter with a pseudo intermediate DC link between the synchronous rectifier and the dual active bridges, which is free of the large electrolytic capacitor at the DC link required for the dual-stage DC-AC converter.The AC voltage vg is folded into the voltage vDC1 with a frequency twice that of the AC voltage, which is given by where Vg is the magnitude of vg and ωg is the angular frequency of vg.
The DAB converters are normally controlled by a triple phase shift (TPS) modulation scheme which is shown in Figure 2 [19].
Two legs in the primary side are phase shifted by φ1 and two legs in the secondary side are phase shifted by φ2.The phase shift angle θ between the voltages vAB and vCD is the third element of this TPS modulation scheme, which determines the direction of the power transfer.In this paper, the duty cycles of the switches on leg A can be regulated, while the duty cycles of other switches are fixed at 50%.The DAB converters are normally controlled by a triple phase shift (TPS) modulation scheme which is shown in Figure 2 [19].
Two legs in the primary side are phase shifted by ϕ 1 and two legs in the secondary side are phase shifted by ϕ 2 .The phase shift angle θ between the voltages v AB and v CD is the third element of this TPS modulation scheme, which determines the direction of the power transfer.In this paper, the duty cycles of the switches on leg A can be regulated, while the duty cycles of other switches are fixed at 50%.The Fourier-series method is adopted for the mathematical analysis of the converter in this paper.In this approach, the significant harmonics of the circuit waveforms are all taken into account, and the basic AC-circuit theory is used to analyze the resonant converter.The voltage vAO across the switch Sp2 and the voltage vBO across the switch Sp4 with the duty cycle modulation are given by   From ( 2) and (3), vAB is given by Also, vCD is given similarly by This converter can be simplified by using the circuit model as shown in Figure 3.The nth harmonic component of ir is given by The Fourier-series method is adopted for the mathematical analysis of the converter in this paper.In this approach, the significant harmonics of the circuit waveforms are all taken into account, and the basic AC-circuit theory is used to analyze the resonant converter.The voltage v AO across the switch S p2 and the voltage v BO across the switch S p4 with the duty cycle modulation are given by From ( 2) and (3), v AB is given by Also, v CD is given similarly by This converter can be simplified by using the circuit model as shown in Figure 3.
Energies 2018, 11, x FOR PEER REVIEW 3 of 16 The Fourier-series method is adopted for the mathematical analysis of the converter in this paper.In this approach, the significant harmonics of the circuit waveforms are all taken into account, and the basic AC-circuit theory is used to analyze the resonant converter.The voltage vAO across the switch Sp2 and the voltage vBO across the switch Sp4 with the duty cycle modulation are given by   From ( 2) and (3), vAB is given by Also, vCD is given similarly by This converter can be simplified by using the circuit model as shown in Figure 3.The nth harmonic component of ir is given by The nth harmonic component of i r is given by .
where N is the turns ratio of the HF transformer, .
V ABn and .
V CDn are the phasors of the nth harmonic component of v AB and v CD .
. V ABn and .
V CDn are given by . .
The nth harmonic average power component P an is given by where V ABn and V CDn represent the magnitudes of .
V ABn and .
V CDn , ϕ ABn and ϕ CDn represent the arguments of .V ABn and .
V CDn .The transmission power of the converter is given by By substituting relevant parameters of the converter, the denominator of (10), namely n(n 2 ω 2 s L r C r − 1), increases rapidly with higher harmonics.Its value is 1.27, 58.18, 278.26 and 770.26 for fundamental, third, fifth and seventh harmonics respectively.Thus only the fundamental transmission power of the converter will be considered to calculate the transmission power as shown in ( 11) where the reactance X 1 of the resonant tank at fundamental frequency is given by If D is ideally near 1/2, then (11) can be simplified as From ( 13) it is evident that the phase shift angle θ between the voltages v AB and v CD determines the direction of the power transfer.When v AB leads v CD by the phase shift angle θ, the power transfers from the DC side to the AC side.When v AB lags v CD by θ, then the power transfers from the AC side to the DC side.The bidirectional power transfer feature of the DAB converters is thus realized through the control of the phase shift angle θ.The average power transferred to the AC side is given by Then the magnitude of i g is given by Energies 2018, 11, 2746 5 of 16 According to (13), if ϕ 1 and θ are fixed, then ϕ 2 should be regulated as ϕ 2 = 2ω g t in order to achieve unity power factor at the AC side [20][21][22], which is shown in Figure 4. T g represents the AC voltage period.This modulation method for ϕ 2 ensures the balance between the transmission power of the DAB converter and the AC side power, which realizes a pseudo DC link between the DAB converter and the synchronous rectifier free of the large electrolytic capacitor used in the dual-stage converter.
According to (13), if 1  and  are fixed, then 2  should be regulated as φ 2 = 2ω g t in order to achieve unity power factor at the AC side [20][21][22], which is shown in Figure 4. Tg represents the AC voltage period.This modulation method for φ2 ensures the balance between the transmission power of the DAB converter and the AC side power, which realizes a pseudo DC link between the DAB converter and the synchronous rectifier free of the large electrolytic capacitor used in the dualstage converter.According to (11), assuming θ = π/2, two three-dimensional plots of the transmission power characterization with d max = 0.05 and d max = 0.35 (d max is defined as the maximum deviation magnitude of the duty cycle D) are shown in Figure 5. p is defined as p = P a1 /P N , where P N is given by According to (13), if 1  and  are fixed, then 2  should be regulated as φ 2 = 2ω g t in order to achieve unity power factor at the AC side [20][21][22], which is shown in Figure 4. Tg represents the AC voltage period.This modulation method for φ2 ensures the balance between the transmission power of the DAB converter and the AC side power, which realizes a pseudo DC link between the DAB converter and the synchronous rectifier free of the large electrolytic capacitor used in the dualstage converter.with d max = 0.35 can cause distortion in the AC side current.Therefore, it is reasonable to use the simplified (13) if a small d max value can be obtained.

Control Strategy
The integrated buck/boost stage at the primary side of the HF transformer for power decoupling is shown in Figure 6.C s , L s , two switches of the leg A and the DC bus form a bidirectional Buck/Boost topology inherently, by which the power decoupling is realized.If i s > 0, the topology works in Buck mode.If i s < 0, then the topology works in Boost mode.
Energies 2018, 11, x FOR PEER REVIEW 6 of 16 The transmission power of the DAB converter fluctuates at 100 Hz frequency and the transmission power increases with bigger phase shift angle φ1.As shown in Figure 5, it is obvious that the transmission power of the DAB converter is near the ideal 100 Hz sinusoidal waveform with dmax = 0.05, and is greatly distorted with higher dmax = 0.35.The distorted transmission power with dmax = 0.35 can cause distortion in the AC side current.Therefore, it is reasonable to use the simplified (13) if a small dmax value can be obtained.

Control Strategy
The integrated buck/boost stage at the primary side of the HF transformer for power decoupling is shown in Figure 6.Cs, Ls, two switches of the leg A and the DC bus form a bidirectional Buck/Boost topology inherently, by which the power decoupling is realized.If is > 0, the topology works in Buck mode.If is < 0, then the topology works in Boost mode.Assuming that the AC side voltage and current are in phase, vg and ig are given by Then the AC side power Pg is given by The integrated buck/boost stage at the primary side of the HF transformer for power decoupling.
The two working modes of the integrated buck/boost stage are illustrated in Figure 7. L s works as a part of the low-pass filter in the Buck mode, and works as a Boost inductor in the Boost mode.
The transmission power of the DAB converter fluctuates at 100 Hz frequency and the transmission power increases with bigger phase shift angle φ1.As shown in Figure 5, it is obvious that the transmission power of the DAB converter is near the ideal 100 Hz sinusoidal waveform with dmax = 0.05, and is greatly distorted with higher dmax = 0.35.The distorted transmission power with dmax = 0.35 can cause distortion in the AC side current.Therefore, it is reasonable to use the simplified (13) if a small dmax value can be obtained.

Control Strategy
The integrated buck/boost stage at the primary side of the HF transformer for power decoupling is shown in Figure 6.Cs, Ls, two switches of the leg A and the DC bus form a bidirectional Buck/Boost topology inherently, by which the power decoupling is realized.If is > 0, the topology works in Buck mode.If is < 0, then the topology works in Boost mode.Assuming that the AC side voltage and current are in phase, vg and ig are given by Then the AC side power Pg is given by Assuming that the AC side voltage and current are in phase, v g and i g are given by Then the AC side power P g is given by It is clear that P g consists of two components, i.e., the average part 1 2 V g I g and the oscillating part 1 2 V g I g cos(2ω g t).As the battery serves at the DC side, the DC side power is required to be constant, which equals to the average part of P g .Therefore, the oscillating power should somehow be mitigated through energy storage buffers.The ideal power decoupling performance of the integrated buck/boost stage is shown in Figure 8. P g represents the AC side power, P avg represents the average power of P g , i DC0 represents the DC side current without any control, P c represents the ideal decoupling power transferred into the decoupling capacitor C s , E c represents the ideal storage energy of C s , u s represents the voltage of C s , and i s represents the ideal power steering current.
As u s can be controlled by the duty cycle of the leg A, the ripple power is supposed to be completely eliminated by adjusting the duty cycle properly.The relation between the power decoupling capacitor C s and the duty cycle deviation d is given in [18] as where d max is the maximum deviation magnitude of the modulated duty cycle D.
It is clear that Pg consists of two components, i.e., the average part 1 2 V g I g and the oscillating part 1 2 V g I g cos(2ω g t).As the battery serves at the DC side, the DC side power is required to be constant, which equals to the average part of Pg.Therefore, the oscillating power should somehow be mitigated through energy storage buffers.The ideal power decoupling performance of the integrated buck/boost stage is shown in Figure 8. Pg represents the AC side power, Pavg represents the average power of Pg, iDC0 represents the DC side current without any control, Pc represents the ideal decoupling power transferred into the decoupling capacitor Cs, Ec represents the ideal storage energy of Cs, us represents the voltage of Cs, and is represents the ideal power steering current.
As us can be controlled by the duty cycle of the leg A, the ripple power is supposed to be completely eliminated by adjusting the duty cycle properly.The relation between the power decoupling capacitor Cs and the duty cycle deviation d is given in [18] as where d max is the maximum deviation magnitude of the modulated duty cycle D.The overall control diagram is shown in Figure 9.I avg and i ripple represent the average component and the ripple component of i DC respectively.I avg * and i* represent reference values for I avg and i ripple respectively.The phase shift angle ϕ 2 is as follows: ϕ 2 = 2ω g t (shown in Figure 4) and the phase shift angle θ is fixed as π/2.To obtain a specific value for the charging or discharging current of the battery, ϕ 1 is used to control I avg through a proportional-integral (PI) controller (error value I E as input, ϕ 1 as output), thus the battery charging or discharging current can be regulated based on the value of I avg *.Additionally, i ripple is controlled by the proportional resonant (PR) controller [23] (−i ripple as input, D as output).The non-ideal PR controller transfer function is given by where the K P , K i , ω c and ω 0 represent the proportional term, the resonant term gain, the cut-off frequency and the resonant frequency respectively.According to the internal model principle, if a sinusoidal mathematical model included, the controller can realize zero steady-state error following a sinusoidal reference input signal at the specific frequency [24].The bode diagrams of the non-ideal PR controller are shown in Figure 10, with K P = 1, K i = 10, ω c = 5, 10, 20 rad/s and ω 0 = 200π rad/s.As shown in Figure 10, a high gain at the resonant frequency is obtained.And the bandwidth can be widened with a higher value of ω c and vice versa.A wider bandwidth is helpful when the frequency variation effect occurs.
Energies 2018, 11, x FOR PEER REVIEW 8 of 16 respectively.The phase shift angle φ2 is as follows: φ 2 = 2ω g t (shown in Figure 4) and the phase shift angle θ is fixed as π/2.To obtain a specific value for the charging or discharging current of the battery, φ1 is used to control Iavg through a proportional-integral (PI) controller (error value IE as input, φ1 as output), thus the battery charging or discharging current can be regulated based on the value of Iavg*.Additionally, iripple is controlled by the proportional resonant (PR) controller [23] (−iripple as input, D as output).The non-ideal PR controller transfer function is given by where the K P , K i , ω c and ω 0 represent the proportional term, the resonant term gain, the cutoff frequency and the resonant frequency respectively.According to the internal model principle, if a sinusoidal mathematical model included, the controller can realize zero steady-state error following a sinusoidal reference input signal at the specific frequency [24].The bode diagrams of the non-ideal PR controller are shown in Figure 10, with K P = 1, K i = 10, ω c = 5, 10, 20 rad/s and ω 0 = 200π rad/s.As shown in Figure 10, a high gain at the resonant frequency is obtained.And the bandwidth can be widened with a higher value of ω c and vice versa.A wider bandwidth is helpful when the frequency variation effect occurs.The control loop designed to control Iavg is shown in Figure 11.GLPF represents the transfer function of the low-pass filter (LPF).GPI represents the PI controller.Gc represents the transfer function from φ1 to iDC.Iavg* is set as 0.5 A in the following analysis.respectively.The phase shift angle φ2 is as follows: φ 2 = 2ω g t (shown in Figure 4) and the phase shift angle θ is fixed as π/2.To obtain a specific value for the charging or discharging current of the battery, φ1 is used to control Iavg through a proportional-integral (PI) controller (error value IE as input, φ1 as output), thus the battery charging or discharging current can be regulated based on the value of Iavg*.Additionally, iripple is controlled by the proportional resonant (PR) controller [23] (−iripple as input, D as output).The non-ideal PR controller transfer function is given by

Modulator
where the K P , K i , ω c and ω 0 represent the proportional term, the resonant term gain, the cutoff frequency and the resonant frequency respectively.According to the internal model principle, if a sinusoidal mathematical model included, the controller can realize zero steady-state error following a sinusoidal reference input signal at the specific frequency [24].The bode diagrams of the non-ideal PR controller are shown in Figure 10, with K P = 1, K i = 10, ω c = 5, 10, 20 rad/s and ω 0 = 200π rad/s.As shown in Figure 10, a high gain at the resonant frequency is obtained.And the bandwidth can be widened with a higher value of ω c and vice versa.A wider bandwidth is helpful when the frequency variation effect occurs.The control loop designed to control Iavg is shown in Figure 11.GLPF represents the transfer function of the low-pass filter (LPF).GPI represents the PI controller.Gc represents the transfer function from φ1 to iDC.Iavg* is set as 0.5 A in the following analysis.According to (14), assuming that the PR controller is working appropriately and the DC side power ripple is almost eliminated, then iDC can be given by

Modulator
Gc is given by GLPF is given by where the damping coefficient =0.7,  natural angular frequency ω n = 20π rad/s.GPI is given as The loop gain of the system is given by In the steady state, φ1 is calculated as 1.03 rad/s according to (21) assuming that iDC is ideally controlled as Iavg*.Then the bode diagram of the corrected open-loop transfer function is shown in Figure 12.As shown in this figure, the phase margin is enough to meet the stability requirement of the system.According to (14), assuming that the PR controller is working appropriately and the DC side power ripple is almost eliminated, then i DC can be given by G c is given by G LPF is given by where the damping coefficient ζ = 0.7, natural angular frequency ω n = 20π rad/s.G PI is given as The loop gain of the system is given by In the steady state, ϕ 1 is calculated as 1.03 rad/s according to (21) assuming that i DC is ideally controlled as I avg *.Then the bode diagram of the corrected open-loop transfer function is shown in Figure 12.As shown in this figure, the phase margin is enough to meet the stability requirement of the system.According to (14), assuming that the PR controller is working appropriately and the DC side power ripple is almost eliminated, then iDC can be given by Gc is given by GLPF is given by where the damping coefficient =0.7,  natural angular frequency ω n = 20π rad/s.GPI is given as The loop gain of the system is given by In the steady state, φ1 is calculated as 1.03 rad/s according to (21) assuming that iDC is ideally controlled as Iavg*.Then the bode diagram of the corrected open-loop transfer function is shown in Figure 12.As shown in this figure, the phase margin is enough to meet the stability requirement of the system.

Simulation and Experimental Results
The simulation and experimental results of the proposed DC-AC DAB converter with DC side power decoupling under low power condition are shown in this section.

Simulation Results
The main parameters of the MATLAB Simulink model are given in Table 1.With ϕ 1 = π/2, θ = π/2, the simulation results of the AC side voltage v g and current i g , DC side current i DC without the DC side power decoupling are shown in Figure 13.From Figure 13c, there is a 100 Hz ripple current, or a 100 Hz ripple power at the DC side because of the double-line-frequency power transmission nature at the AC side.It is noted that the unity power factor is achieved at the AC side due to the applied modulation scheme for the phase shift angle ϕ 2 .

Simulation and Experimental Results
The simulation and experimental results of the proposed DC-AC DAB converter with DC side power decoupling under low power condition are shown in this section.

Simulation Results
The main parameters of the MATLAB Simulink model are given in Table 1.With φ1 = π/2, θ = π/2, the simulation results of the AC side voltage vg and current ig, DC side current iDC without the DC side power decoupling are shown in Figure 13.From Figure 13c, there is a 100 Hz ripple current, or a 100 Hz ripple power at the DC side because of the double-line-frequency power transmission nature at the AC side.It is noted that the unity power factor is achieved at the AC side due to the applied modulation scheme for the phase shift angle φ2.With φ1 = π/2, θ = π/2, the simulation results of ig, iDC, the power decoupling capacitor Cs voltage us and current is with the DC side power decoupling are shown in Figure 14.According to (20), the parameters of the PR controller are as follows: K P = 0.3, K i = 3, ω c = 5 rad/s and ω 0 = 200π rad/s.With ϕ 1 = π/2, θ = π/2, the simulation results of i g , i DC , the power decoupling capacitor C s voltage u s and current i s with the DC side power decoupling are shown in Figure 14.According to  (20), the parameters of the PR controller are as follows: K P = 0.3, K i = 3, ω c = 5 rad/s and ω 0 = 200π rad/s.
From Figure 14b, the 100 Hz ripple power at the DC side is almost eliminated, thus a relatively stable DC side current is obtained, which is important when the DC source is a battery.From Figure 14c,d, as the duty cycle of leg A is modulated, the power decoupling capacitor C s voltage u s fluctuates at 100 Hz frequency and balances the 100 Hz ripple power at the DC side.Also, the fluctuation range of u s is relatively small, thus the modulation range of the duty cycle is small, which will not cause a distortion in the transmission power and the AC side current i g as shown in Figure 14a.From Figure 14b, the 100 Hz ripple power at the DC side is almost eliminated, thus a relatively stable DC side current is obtained, which is important when the DC source is a battery.From Figure 14c,d, as the duty cycle of leg A is modulated, the power decoupling capacitor Cs voltage us fluctuates at 100 Hz frequency and balances the 100 Hz ripple power at the DC side.Also, the fluctuation range of us is relatively small, thus the modulation range of the duty cycle is small, which will not cause a distortion in the transmission power and the AC side current ig as shown in Figure 14a.The simulation results of the voltages v AB , v CD , and the transformer primary side current i r are shown in Figure 15.As ϕ 1 is set as π/2, the width of the positive part and the negative part of v AB is π/2, and v AB leads v CD by θ = π/2.The envelope of the transformer secondary voltage v CD under this condition is shown in Figure 16.According to v CD1 given in (1), the magnitude of v CD has a 100 Hz envelope.From Figure 14b, the 100 Hz ripple power at the DC side is almost eliminated, thus a relatively stable DC side current is obtained, which is important when the DC source is a battery.From Figure 14c,d, as the duty cycle of leg A is modulated, the power decoupling capacitor Cs voltage us fluctuates at 100 Hz frequency and balances the 100 Hz ripple power at the DC side.Also, the fluctuation range of us is relatively small, thus the modulation range of the duty cycle is small, which will not cause a distortion in the transmission power and the AC side current ig as shown in Figure 14a.

Experimental Results
The experimental settings are shown in Figure 18.The parameters of the experimental settings are the same as the simulation parameters shown in Table 1.With φ1 = π/2, θ = π/2, the experimental results of the AC side voltage vg and current ig, DC side current iDC without the DC side power decoupling are shown in Figure 19.Similar with the simulation results shown in Figure 13, there appears a 100 Hz ripple current, or a 100 Hz ripple power at the DC side because of the double-linefrequency power transmission nature at the AC side.

Experimental Results
The experimental settings are shown in Figure 18.The parameters of the experimental settings are the same as the simulation parameters shown in Table 1.With φ1 = π/2, θ = π/2, the experimental results of the AC side voltage vg and current ig, DC side current iDC without the DC side power decoupling are shown in Figure 19.Similar with the simulation results shown in Figure 13, there appears a 100 Hz ripple current, or a 100 Hz ripple power at the DC side because of the double-linefrequency power transmission nature at the AC side.

Experimental Results
The experimental settings are shown in Figure 18.The parameters of the experimental settings are the same as the simulation parameters shown in Table 1.With ϕ 1 = π/2, θ = π/2, the experimental results of the AC side voltage v g and current i g , DC side current i DC without the DC side power decoupling are shown in Figure 19.Similar with the simulation results shown in Figure 13, there appears a 100 Hz ripple current, or a 100 Hz ripple power at the DC side because of the double-line-frequency power transmission nature at the AC side.

Experimental Results
The experimental settings are shown in Figure 18.The parameters of the experimental settings are the same as the simulation parameters shown in Table 1.With φ1 = π/2, θ = π/2, the experimental results of the AC side voltage vg and current ig, DC side current iDC without the DC side power decoupling are shown in Figure 19.Similar with the simulation results shown in Figure 13, there appears a 100 Hz ripple current, or a 100 Hz ripple power at the DC side because of the double-linefrequency power transmission nature at the AC side.Comparing Figure 20a with Figure 14a, and Figure 20b with Figure 14b, it is obvious that the experimental results verify the simulation results.The experimental result of iDC is about 0.91 A, which is near the simulation result of iDC.The 100 Hz ripple power at the DC side is almost eliminated compared with Figure 19b, thus a more stable DC side current is obtained.Compared with Figure 14c, the average value of us in Figure 21 is a bit lower than the expected value due to the voltage drop at the DC side in the experimental test.With the duty cycle modulation, the power decoupling capacitor Cs voltage us fluctuates at 100 Hz frequency and thus the 100 Hz ripple power at the DC side is eliminated.
The experimental result of the transformer secondary voltage vCD in this condition is shown in Figure 22.According to vDC1 given in (1), vCD shows a 100 Hz envelope with a magnitude of 18 V (Vg).Comparing Figure 20a with Figure 14a, and Figure 20b with Figure 14b, it is obvious that the experimental results verify the simulation results.The experimental result of iDC is about 0.91 A, which is near the simulation result of iDC.The 100 Hz ripple power at the DC side is almost eliminated compared with Figure 19b, thus a more stable DC side current is obtained.Compared with Figure 14c, the average value of us in Figure 21 is a bit lower than the expected value due to the voltage drop at the DC side in the experimental test.With the duty cycle modulation, the power decoupling capacitor Cs voltage us fluctuates at 100 Hz frequency and thus the 100 Hz ripple power at the DC side is eliminated.
The experimental result of the transformer secondary voltage vCD in this condition is shown in Figure 22.According to vDC1 given in (1), vCD shows a 100 Hz envelope with a magnitude of 18 V (Vg).Comparing Figure 20a with Figure 14a, and Figure 20b with Figure 14b, it is obvious that the experimental results verify the simulation results.The experimental result of iDC is about 0.91 A, which is near the simulation result of iDC.The 100 Hz ripple power at the DC side is almost eliminated compared with Figure 19b, thus a more stable DC side current is obtained.Compared with Figure 14c, the average value of us in Figure 21 is a bit lower than the expected value due to the voltage drop at the DC side in the experimental test.With the duty cycle modulation, the power decoupling capacitor Cs voltage us fluctuates at 100 Hz frequency and thus the 100 Hz ripple power at the DC side is eliminated.
The experimental result of the transformer secondary voltage vCD in this condition is shown in Figure 22.According to vDC1 given in (1), vCD shows a 100 Hz envelope with a magnitude of 18 V (Vg).Comparing Figure 20a with Figure 14a, and Figure 20b with Figure 14b, it is obvious that the experimental results verify the simulation results.The experimental result of i DC is about 0.91 A, which is near the simulation result of i DC.The 100 Hz ripple power at the DC side is almost eliminated compared with Figure 19b, thus a more stable DC side current is obtained.Compared with Figure 14c, the average value of u s in Figure 21 is a bit lower than the expected value due to the voltage drop at the DC side in the experimental test.With the duty cycle modulation, the power decoupling capacitor C s voltage u s fluctuates at 100 Hz frequency and thus the 100 Hz ripple power at the DC side is eliminated.
The experimental result of the transformer secondary voltage v CD in this condition is shown in Figure 22.According to v DC1 given in (1), v CD shows a 100 Hz envelope with a magnitude of 18 V (V g ).

Conclusions
The basic characteristics of the single stage DC-AC DAB converter with an integrated uni-phase buck/boost stage for DC side power decoupling purpose under low power condition is analyzed in detail based on the mathematical analysis, simulations and experiments.Not only the power density and reliability of the converter is enhanced as no additional power switch is added, but also the cost of the converter is decreased.By controlling the duty cycle of the specific leg, the integrated uni-phase buck/boost stage is able to completely eliminate the double-line-frequency ripple power with PR control, which is verified in the simulation and experimental results.In addition, a current loop is added to obtain a specific constant value for the charging or discharging current of the DC source.

Conclusions
The basic characteristics of the single stage DC-AC DAB converter with an integrated uni-phase buck/boost stage for DC side power decoupling purpose under low power condition is analyzed in detail based on the mathematical analysis, simulations and experiments.Not only the power density and reliability of the converter is enhanced as no additional power switch is added, but also the cost of the converter is decreased.By controlling the duty cycle of the specific leg, the integrated uni-phase buck/boost stage is able to completely eliminate the double-line-frequency ripple power with PR control, which is verified in the simulation and experimental results.In addition, a current loop is added to obtain a specific constant value for the charging or discharging current of the DC source.

Conclusions
The basic characteristics of the single stage DC-AC DAB converter with an integrated uni-phase buck/boost stage for DC side power decoupling purpose under low power condition is analyzed in detail based on the mathematical analysis, simulations and experiments.Not only the power density and reliability of the converter is enhanced as no additional power switch is added, but also the cost of the converter is decreased.By controlling the duty cycle of the specific leg, the integrated uni-phase buck/boost stage is able to completely eliminate the double-line-frequency ripple power with PR control, which is verified in the simulation and experimental results.In addition, a current loop is added to obtain a specific constant value for the charging or discharging current of the DC source.

Figure 3 .
Figure 3. Simplified circuit model of the converter.

Figure 3 .
Figure 3. Simplified circuit model of the converter.

Figure 3 .
Figure 3. Simplified circuit model of the converter.

Figure 5 .
Figure 5. Three-dimensional plots of the transmission power characterization with duty cycle modulation (a) d max = 0.05; (b) d max = 0.35.The transmission power of the DAB converter fluctuates at 100 Hz frequency and the transmission power increases with bigger phase shift angle ϕ 1 .As shown in Figure5, it is obvious that the transmission power of the DAB converter is near the ideal 100 Hz sinusoidal waveform with d max = 0.05, and is greatly distorted with higher d max = 0.35.The distorted transmission power

Figure 6 .
Figure 6.The integrated buck/boost stage at the primary side of the HF transformer for power decoupling.

Figure 7 .
Figure 7. Two working modes of the integrated buck/boost stage (a) Buck mode with is > 0; (b) Boost mode with is < 0.

Figure 6 .
Figure 6.The integrated buck/boost stage at the primary side of the HF transformer for power decoupling.

Figure 7 .
Figure 7. Two working modes of the integrated buck/boost stage (a) Buck mode with is > 0; (b) Boost mode with is < 0.

Figure 7 .
Figure 7. Two working modes of the integrated buck/boost stage (a) Buck mode with i s > 0; (b) Boost mode with i s < 0.

Figure 8 .
Figure 8.The ideal power decoupling performance of the integrated buck/boost stage.

Figure 8 .
Figure 8.The ideal power decoupling performance of the integrated buck/boost stage.

Figure 9 .Figure 10 .
Figure 9.The overall control diagram for the proposed DC-AC DAB converter with DC side power decoupling.

Figure 9 .
Figure 9.The overall control diagram for the proposed DC-AC DAB converter with DC side power decoupling.

Figure 9 .Figure 10 .
Figure 9.The overall control diagram for the proposed DC-AC DAB converter with DC side power decoupling.

Figure 10 .Figure 11 .
Figure 10.The bode diagram of the non-ideal PR controller.The control loop designed to control I avg is shown in Figure11.G LPF represents the transfer function of the low-pass filter (LPF).G PI represents the PI controller.G c represents the transfer function from ϕ 1 to i DC.I avg * is set as 0.5 A in the following analysis.

Figure 12 .
Figure 12.The bode diagram of the corrected open-loop transfer function for Iavg control.

Figure 11 .
Figure 11.Control loop for the purpose of I avg control.

Figure 11 .
Figure 11.Control loop for the purpose of Iavg control.

Figure 12 .
Figure 12.The bode diagram of the corrected open-loop transfer function for Iavg control.Figure 12.The bode diagram of the corrected open-loop transfer function for I avg control.

Figure 12 .
Figure 12.The bode diagram of the corrected open-loop transfer function for Iavg control.Figure 12.The bode diagram of the corrected open-loop transfer function for I avg control.

Figure 13 .
Figure 13.With ϕ 1 = π/2, θ = π/2, (a) the AC side voltage v g ; (b) AC side current i g ; and (c) DC side current i DC without the DC side power decoupling.

Figure 14 .Figure 15 .
Figure 14.With φ1 = π/2, θ = π/2, (a) ig; (b) iDC; (c) the power decoupling capacitor Cs voltage us; and (d) the power decoupling capacitor Cs current is.The simulation results of the voltages vAB, vCD, and the transformer primary side current ir are shown in Figure15.As φ1 is set as π/2, the width of the positive part and the negative part of vAB is π/2, and vAB leads vCD by θ = π/2.The envelope of the transformer secondary voltage vCD under this condition is shown in Figure16.According to vCD1 given in (1), the magnitude of vCD has a 100 Hz envelope.

Figure 16 . 16 Figure 16 .Figure 17 .
Figure 16.The envelope of the transformer secondary voltage v CD (ϕ 1 = π/2, θ = π/2).Assuming the battery charging or discharging current is required as I avg * = 1 A, by adding the I avg control loop shown in Figure9, i DC and ϕ 1 are shown in Figure17.It is clear that i DC is controlled at the desired constant value 1 A.

Figure 17 .
Figure 17.(a) i DC and (b) ϕ 1 with the I avg control loop (I avg * = 1 A).

Energies 2018 , 16 Figure 16 .Figure 17 .
Figure 16.The envelope of the transformer secondary voltage vCD (φ1 = π/2, θ = π/2).Assuming the battery charging or discharging current is required as Iavg* = 1 A, by adding the Iavg control loop shown in Figure9, iDC and φ1 are shown in Figure17.It is clear that iDC is controlled at the desired constant value 1 A.

Figure 19 .Figure 19 .
Figure 19.With ϕ 1 = π/2, θ = π/2, experimental results of (a) the AC side voltage v g and current i g ; (b) DC side current i DC without the DC side power decoupling.With ϕ 1 = π/2, θ = π/2, the experimental results of the AC side voltage v g and current i g , DC side current i DC with the DC side power decoupling are shown in Figure 20.The power decoupling capacitor C s voltage u s and current i s are shown in Figure 21.

Figure 21 .
Figure 21.The power decoupling capacitor C s voltage u s and current i s .

Figure 22 .Figure 22 .Figure 23 .
Figure 22.The experimental result of the transformer secondary voltage v CD (ϕ 1 = π/2, θ = π/2).The experimental results of i DC with the PR control plus I avg control loop (I avg * = 1 A) are shown in Figure 23.In this condition, ϕ 1 is controlled as 1.62 rad/s compared with the simulation result of 2.2 rad/s shown in Figure 17b.It is noted that i DC is controlled as I avg * = 1 A.

Figure 23 .
Figure 23.The DC side current i DC with PR control plus I avg control loop (I avg * = 1 A).

Table 1 .
Parameters of the MATLAB Simulink model.

Table 1 .
Parameters of the MATLAB Simulink model.