An Input-Parallel-Output-Series Switched-Capacitor Three-level Boost Converter with a Three-Loop Control Strategy

Abstract: There has been increasing interest for industry applications, such as solar power generation, fuel cell systems, and dc microgrids, in step-up dc-dc converters with reduced number of components, low component stress, small input ripples and high step-up ratios. In this paper, an input-parallel-output-series three-level boost (IPOS-SC-TLB) converter is proposed. In addition to achieving the required performance, the input and output terminals can share the same ground and an automatic current balance function is also achieved in the IPOS-SC-TLB converter. Besides, a capacitor voltage imbalance mechanism was revealed and a three-loop control strategy composed of output voltage loop, input current loop and voltage-balance loop was proposed to address the voltage imbalance issue. Finally both simulation and experiment studies have been conducted to verify the effectiveness of the IPOS-SC-TLB converter and the three-loop control strategy.


Introduction
Multilevel step-up dc-dc converters are widely employed in wind farms [1][2][3][4][5][6], solar power generation systems [7][8][9][10][11], fuel cell systems [12][13][14][15], high-power charging stations for electric cars [16,17], and dc microgrids [18][19][20].In these systems, a multilevel step-up dc-dc converter helps regulate a varying low-level input voltage to a stable high-level voltage, which usually serves as the dc link voltage of a grid-connected inverter.It is desirable to achieve both low voltage stress and low current stress across components to reduce power losses and save cost.Besides, input current ripple is another important issue that should be considered for these systems, especially for fuel cell or battery storage systems.As multilevel conversion techniques have evolved, many multilevel step-up dc-dc converters have been proposed.In terms of non-isolated multilevel step-up dc-dc converters, the three-level boost converter was firstly proposed and then adopted to combine with a three-level diode-clamped inverter to achieve medium voltage and high power [2,6].The corresponding four-level boost converter was subsequently proposed to output higher voltage level and higher power [4].Owing to the interleaved scheme, small input current ripple and low component stress could be easily realized in these multilevel boost converters.However, the input terminal and the output terminal in the two converters do not share the same ground, which can bring in severe EMI problem [7].One flying-capacitor-based three-level boost converter was proposed to address this problem and good effect has been achieved [12].However, all these multilevel boost converters face the same inherent limitation, i.e., the voltage gain is limited to be 1/(1 − d), where d is the duty ratio.Unfortunately, practical considerations limit its output voltage to approximately four times its input voltage.To supply inductors are employed in the PI structure.The SI structure needs (n − 1) capacitors, while one capacitor is necessary in the PI structure.
A comparative analysis between the two techniques are presented in Table 1.On the one hand, (n − 1) voltage levels U0, U1, … Un−1, are achieved due to the (n − 1) split capacitors in the SI structure while only one output voltage level Un−1 is achieved in the PI structure.On the other hand, the total input current flow through (n − 1) split inductors in the PI structure while through only one inductor in the SI structure.As a result, the SI structure has output voltage divider function and voltagebalance control strategy is necessary to realize voltage balance.The PI structure has input current shunt function and current-balance control strategy is necessary to balance all split inductor currents.All the drive circuits of the switches must be isolated in the SI topology, i.e., (n − 1) isolated drive sources are necessary in the SI structure.However, this drawback does not exist in the PI structure because all the switches share the same ground.The conventional three-level boost converter is based on the SI structure in Figure 2a.To distinguish it from other topologies in this paper, the converter in Figure 2a is called SI-TLB.The converter in Figure 2b is named as PIB as it is based on the PI topology.The input terminal and the output terminal of SI-TLB do not share the same ground, which easily results in electromagnetic interference (EMI) problems.Moreover, the voltage stresses across all the components in a PIB converter are high since no multilevel technique is employed.
To avoid these shortcomings mentioned above, flying-capacitor technique has been introduced into SI-TLB and PIB converters to develop new three-level boost converters.The converter called SI-FC-TLB in Figure 2c is derived by employing one flying-capacitor.The input terminal and the output terminal share the same ground and all switches and diodes are clamped at the half of the output voltage by controlling the voltage of the flying-capacitor Cf to be half of the output voltage [21,22].However, it can be seen that SI-TLB and SI-FC-TLB both have a limited voltage gain due to the SI structure.Thus, the converter called PI-FC-TLB in Figure 2d was proposed based on PI structure and one flying-capacitor [21,22].The voltage gain of PI-FC-TLB is as two times as that of SI-TLB and SI-FC-TLB.But the voltage stress across the output diode is high, equal to the output voltage.Also, another converter PI-SFC-TLB based on the PI structure and two symmetrical flying-capacitors in Figure 2e was proposed to reduce the voltage stresses across the output diodes [23].However, the voltage stress across the output capacitor is still equal to the output voltage and many capacitors and diodes are necessary.As analyzed above, flying-capacitor technique introduced into multilevel boost converters based on SI structure could help solve the problem that input and output terminals do not  The conventional three-level boost converter is based on the SI structure in Figure 2a.To distinguish it from other topologies in this paper, the converter in Figure 2a is called SI-TLB.The converter in Figure 2b is named as PIB as it is based on the PI topology.The input terminal and the output terminal of SI-TLB do not share the same ground, which easily results in electromagnetic interference (EMI) problems.Moreover, the voltage stresses across all the components in a PIB converter are high since no multilevel technique is employed.
switched-capacitor network is proposed in [26].For simplification, the converter is name as SC-TLB, which not only has two split capacitors at the output terminal, but also has self-balancing function for capacitor voltages.As a result, there is no need to employ any voltage-balance control strategies to solve the voltage imbalance issue.However, as analyzed in Section 1, there is a big disadvantage that SC-TLB has high input current and high input current ripple since no interleaved structures are employed.As a result, high power losses are inevitable in the SC-TLB converter.There are also two input-parallel-output-series (IPOS) boost converters shown in Figure 2g (called by IPOS-TLB1) and Figure 2h (called by IPOS-TLB2) from references [24,25].Like the ISOS-TLB converter, the input terminal and the output terminal do not share the same ground and the voltage stress across diode D1 is equal to the output voltage in the IPOS-TLB1 converter.Although the topology IPOS-TLB2 is simple, its voltage gain is smaller than the other topologies and the input terminal and the output terminal do not share the same ground, either.
According to the comparative analysis mentioned above, the SI structure is suitable for high input voltage and high output voltage applications while the PI structure is suitable for high input current and high output current applications.As shown in Figure 1, the input terminal, output terminal and all switches share the same ground in the PI topology.The flying-capacitor technique helps enhance the voltage gains of the converters based on the PI structure.Besides, the switched- To avoid these shortcomings mentioned above, flying-capacitor technique has been introduced into SI-TLB and PIB converters to develop new three-level boost converters.The converter called SI-FC-TLB in Figure 2c is derived by employing one flying-capacitor.The input terminal and the output terminal share the same ground and all switches and diodes are clamped at the half of the output voltage by controlling the voltage of the flying-capacitor C f to be half of the output voltage [21,22].
However, it can be seen that SI-TLB and SI-FC-TLB both have a limited voltage gain due to the SI structure.Thus, the converter called PI-FC-TLB in Figure 2d was proposed based on PI structure and one flying-capacitor [21,22].The voltage gain of PI-FC-TLB is as two times as that of SI-TLB and SI-FC-TLB.But the voltage stress across the output diode is high, equal to the output voltage.Also, another converter PI-SFC-TLB based on the PI structure and two symmetrical flying-capacitors in Figure 2e was proposed to reduce the voltage stresses across the output diodes [23].However, the voltage stress across the output capacitor is still equal to the output voltage and many capacitors and diodes are necessary.As analyzed above, flying-capacitor technique introduced into multilevel boost converters based on SI structure could help solve the problem that input and output terminals do not share the same ground while flying-capacitor technique introduced into multilevel boost converters based on PI structure could help enhance voltage gains.However, there is a common disadvantage among SI-FC-TLB, PI-FC-TLB, and PI-SFC-TLB converters that the output terminal is constructed by only one output capacitor, which not only bears a high voltage stress, but also does not help reduce the voltage stress across output diodes and output capacitors.Additionally, the voltage-balance control is not easy to realize as one or more flying-capacitor voltages should be control independently.Even though the output capacitor can be replaced by two split capacitors in series in the output terminal, the two split capacitors could not be self-balanced and could not be controlled by voltage-balance control strategy either.On the other hand, a three-level boost converter based on switched-capacitor network is proposed in [26].For simplification, the converter is name as SC-TLB, which not only has two split capacitors at the output terminal, but also has self-balancing function for capacitor voltages.As a result, there is no need to employ any voltage-balance control strategies to solve the voltage imbalance issue.However, as analyzed in Section 1, there is a big disadvantage that SC-TLB has high input current and high input current ripple since no interleaved structures are employed.As a result, high power losses are inevitable in the SC-TLB converter.
There are also two input-parallel-output-series (IPOS) boost converters shown in Figure 2g (called by IPOS-TLB1) and Figure 2h (called by IPOS-TLB2) from references [24,25].Like the ISOS-TLB converter, the input terminal and the output terminal do not share the same ground and the voltage stress across diode D 1 is equal to the output voltage in the IPOS-TLB1 converter.Although the topology IPOS-TLB2 is simple, its voltage gain is smaller than the other topologies and the input terminal and the output terminal do not share the same ground, either.
According to the comparative analysis mentioned above, the SI structure is suitable for high input voltage and high output voltage applications while the PI structure is suitable for high input current and high output current applications.As shown in Figure 1, the input terminal, output terminal and all switches share the same ground in the PI topology.The flying-capacitor technique helps enhance the voltage gains of the converters based on the PI structure.Besides, the switched-capacitor technique, which could be deemed as an extension of flying-capacitor technique, not only increases the voltage gain, but also brings a self-balancing function for capacitor voltages.On the whole, there are three techniques could be employed in multilevel dc/dc converters, i.e., interleaved technique, flying-capacitor technique, and switched-capacitor technique.Until now, only one or two of the three techniques were employed in a single power converter.
This paper proposes an IPOS-SC-TLB converter in Figure 3 and presents a detailed analysis of the converter.IPOS-SC-TLB combines the parallel-interleaved technique, flying-capacitor technique, and switched-capacitor technique together.In Figure 3, L 1 , L 2 , S 1 , S 2 formulate the PI structure, while L 1 , S 1 , D 1 , C 1 form Boost I and L 2 , S 2 , D 3 , C 2 form Boost II.Besides, C f , D 2 and S 2 , C 1 formulate a switched-capacitor network, which makes the two input terminals in parallel and the output terminals in series for Boost I and Boost II.
of the three techniques were employed in a single power converter.
This paper proposes an IPOS-SC-TLB converter in Figure 3 and presents a detailed analysis of the converter.IPOS-SC-TLB combines the parallel-interleaved technique, flying-capacitor technique, and switched-capacitor technique together.In Figure 3, L1, L2, S1, S2 formulate the PI structure, while L1, S1, D1, C1 form Boost I and L2, S2, D3, C2 form Boost II.Besides, Cf, D2 and S2, C1 formulate a switchedcapacitor network, which makes the two input terminals in parallel and the output terminals in series for Boost I and Boost II.
The proposed IPOS-SC-TLB converter.

Operating Principle
In the IPOS-SC-TLB converter, all the inductors, capacitors, switches, diodes have the same respective parameters, i.e.,

Operating Principle
In the IPOS-SC-TLB converter, all the inductors, capacitors, switches, diodes have the same respective parameters, i.e., Considering the voltage drops of IGBT and diode, and the equivalent series resistor of inductor, the equivalent circuits of the IPOS-SC-TLB converter are presented in Figure 4.In the interleaved scheme, the operating stages of IPOS-SC-TLB could be divided into two modes according to duty cycle: when d is greater than 0.5 and when d is smaller than 0.5.
(1) When the duty cycle d is greater than 0.5, the IPOS-SC-TLB operates at the periodic stages of I, II, I, and III.
Stage I: Both switches S 1 , S 2 are turned on and the diode D 2 is forward biased as the capacitor voltage U C1 is still a little bigger than the capacitor voltage U Cf after the stage III.During Stage I, both the two inductors L 1 , L 2 are charged by the input source U in .Thus, there are: As the two capacitor voltages U C1 , U Cf are charged in parallel, the voltage differences between U C1 and U Cf are small but cannot be ignored.As a result, the current flowing through D 2 caused by the small voltage difference is labelled as I 1 .The current flowing through S 1 is equal to i L1 while the current flowing through S 2 is the sum of i L2 and I 1 .
Stage II: When the switch S 1 is turned on and the switch S 2 is turned off, the diode D 3 is forward.The inductor L 1 is still charged by the input source U in , which also supplies energy to the load together with the inductor L 2 and the flying-capacitor C f .Thus, there are: According to (4) and ( 6), there is: Energies 2018, 11, 2631 7 of 26 During Stage II, the capacitor voltage U Cf decreases while the capacitor voltage U C1 increases.As a result, the voltage difference between U C1 and U Cf becomes bigger and bigger and finally reaches its maximum at the end of Stage II.The current flowing through the switch S 1 is still equal to i L1 while no currents flows through the switch S 2 and the diode D 2 during this stage.
voltage UC1 is still a little bigger than the capacitor voltage UCf after the stage III.During Stage I, both the two inductors L1, L2 are charged by the input source Uin.Thus, there are: As the two capacitor voltages UC1, UCf are charged in parallel, the voltage differences between UC1 and UCf are small but cannot be ignored.As a result, the current flowing through D2 caused by the small voltage difference is labelled as I1.The current flowing through S1 is equal to iL1 while the current flowing through S2 is the sum of iL2 and I1.Stage I: The converter repeats Stage I and the same output results could be achieved like (3) and (4).However, as analyzed in Stage II, the voltage difference between U C1 and U Cf reaches its maximum value, the current flowing through the diode D 2 reaches its maximum value, labelled as I 2 .The current flowing through S 1 turns to be the same as i L1 again while the current flowing through S 2 is the sum of i L2 and I 2 .
Stage III: When the switch S 1 is turned off while the switch S 2 is turned on, the diodes D 1 , D 2 are both forward.The inductor L 2 is charged by the input source U in , which also supplies energy to C 1 and C f together with the inductor L 1 .Thus, there are: During Stage III, the two capacitors C 1 , C f are connected in parallel and thus the voltage difference between them is small, which results in a small current flowing through the diode D 2 .It has been mentioned in the first Stage I, labelled as I 1 .As a consequence, the current flowing through S 1 turns to be zero while the current flowing through S 2 is the sum of i L2 and I 1 .
(2) When the duty cycle d is smaller than 0.5, the IPOS-SC-TLB converter operates at the periodic stages of IV, II, IV, and III.
Stage IV: Both switches S 1 , S 2 are turned off while D 1 and D 3 are on forward biased: As the first Stage IV begins after Stage III, the capacitor voltage U Cf decreases while the capacitor voltage U C1 increases.During this stage, no currents pass through the two switches S 1 , S 2 and the diode D 2 as they are all switched off.
Stage II: The same results could be achieved like ( 5)-( 7) and the voltage difference between U C1 and U Cf continues increasing during this stage.The current flowing through the switch S 1 is still equal to i L1 while no currents flows through the switch S 2 and the diode D 2 during this stage.
Stage IV: The converter enters into another Stage IV, where the voltage difference between U C1 and U Cf continues increasing and reach its maximum value at the end of the stage.And no currents no currents pass through the two switches S 1 , S 2 and the diode D 2 .
Stage III: At the beginning of the stage III, the current flowing through the diode D 2 reaches its maximum value I 2 .But later becomes a smaller value I 1 as the two capacitors C 1 , C f are charged in parallel.Thus, the current flowing through the switch S 1 is zero while the current flowing through the switch S 2 is the sum of i L2 and I 2 and then the sum of i L2 and I 1 during this stage.For any duty cycle d, two equations can be attained based on Voltage-Second Balance Principle during one switching period: During the switching period, the output voltage of the converter is always described by: According to (28), there is: Therefore, the voltage gain G and the capacitor voltages could be derived by: The capacitor voltages are calculated by: Energies 2018, 11, 2631 When the parasitic parameters are ignored, there are:

Component Stress
According to the analysis mentioned above, the key voltage waveforms of the IPOS-SC-TLB converter are presented in Figure 5.The voltage stresses across all switches, diodes and capacitors are half of the output voltage: Energies 2018, 11, x FOR PEER REVIEW 10 of 26  The current waveforms of the IPOS-SC-TLB converter are presented in Figure 6.From Figure 6, whatever the duty cycle d is, the average current across S 1 , S 2 can be obtained as follows: The average currents across D 1 , D 2 , D 3 identical with value equal to the average output current are determined as follows: When the duty cycle d is over 0.5, the operating period of Stage II in Figure 4b can be expressed by (1 − d)T s during one switching period.During Stage II, the capacitor C 2 is charged with the current expressed by:   During the remained operating period dT s , C 2 is discharged with the current expressed by: According to Ampere-Second Balance Principle, there is: We can obtain the average current of inductor L 2 by simplifying (24) as below: When the duty cycle is smaller than 0.5, the same formula as ( 25) can be obtained.It should be noted that the average current of inductor L 2 could be also derived as below.During one whole switching period, the average charging current flowing through C f is the same as the average current flowing through D 2 .So the increased charges of C f during one switching period is I D2 *T s .In addition, when d is over 0.
According to (26), the same formula as ( 25) can be achieved.On the other hand, the average current of L 1 can be easily obtained as below: According to ( 20)-( 27), the average currents across all switches and diodes are:

Switched-Capacitor Network
For two typical boost converters, their input terminals cannot be simply connected in parallel and while their output terminals are connected in series simultaneously.The flying-capacitor C f and the diode D 2 in the proposed IPOS-SC-TLB converter are used to realize the input-parallel output-series topology.Because a switched-capacitor network is constructed and it helps support the output voltage of the Boost I for the Boost II.As shown in Figure 4, the flying-capacitor C f is clamped with the capacitor C 1 during Stage I and Stage III, labelled as the oval areas, i.e., the two capacitor voltages are identical.During Stage II and Stage IV, the flying-capacitor C f serves as the voltage support for the Boost II.So, it could be thought of as that the output capacitor C 2 is charged by the input source because the capacitor voltage U Cf offsets the capacitor voltage U C1 , which are labelled as the rectangular areas.Furthermore, it can be seen from ( 26) that the flying-capacitor C f could automatically balance the average currents of the two inductors L 1 and L 2 .Thus, the IPOS-SC-TLB converter does not need any current-balance circuit or current-balance control strategy that is required in the conventional parallel-interleaved dc/dc converters.

Ripple Analysis
In the switched-capacitor network, the flying-capacitor C f could be served as an energy buffer.According to (26) and ( 27), the increased or decreased charges on C f is U o *T s /R, which could be described by another way of C f *∆u Cf , where ∆u Cf represents the voltage ripple of C f .Finally, the voltage ripple of C f is derived by: Besides, it is easy to attain the voltage ripples of C 1 and C 2 : Additionally, the current ripples of L 1 and L 2 could be obtained by: The input current ripple can be calculated by:

Inrush Current Suppression
In practical application, IGBT and diode usually have some voltage drops and capacitors has equivalent serial resistors.Thus, it is inevitable to see some voltage differences between C 1 and C f , which can be described by: U D and U S are assumed to be the voltage drop of one diode and the voltage drop of one IGBT.Figure 7 shows the equivalent circuit of the switched-capacitor network when S 2 turns on.
It can be seen that the output capacitor C1 is connected with the flying-capacitor Cf in parallel.RC1, RCf means the equivalent serial resistors of C1 and Cf, respectively.The current iD2 flowing through the diode D2 could be calculated by: In (34), the equivalent serial resistors RC1, RCf are usually very small, which are in the range of milliohms.As a result, although ΔU is small, it may bring in very high inrush current iD2 flowing the switched-capacitor network when S2 is turned on and D2 is forward instantaneously.Moreover, this will result in more conduction losses across the switch S2 and the diode D2.
From (10), one way to suppress iD2 is to reduce the voltage difference ΔU is by using wide bandgap semiconductors, such as SiC or GaN components that have smaller voltage drops compared with Si-based components.However, ΔU cannot be reduced to zero and this may still bring in a certain inrush current.Another method is to increase the impedance of the switched-capacitor network.Placing a serial resistor with high resistance could increase the impedance but extra power losses are produced.As shown in Figure 8, this paper proposes to put a small stray inductor Ls together with D2.In this way, the loop impedance is increased by 2πfsLs and then the inrush current iD2 is reduced to: It can be seen that the output capacitor C 1 is connected with the flying-capacitor C f in parallel.R C1 , R Cf means the equivalent serial resistors of C 1 and C f , respectively.The current i D2 flowing through the diode D 2 could be calculated by: In (34), the equivalent serial resistors R C1 , R Cf are usually very small, which are in the range of milliohms.As a result, although ∆U is small, it may bring in very high inrush current i D2 flowing the switched-capacitor network when S 2 is turned on and D 2 is forward instantaneously.Moreover, this will result in more conduction losses across the switch S 2 and the diode D 2 .
From (10), one way to suppress i D2 is to reduce the voltage difference ∆U is by using wide bandgap semiconductors, such as SiC or GaN components that have smaller voltage drops compared with Si-based components.However, ∆U cannot be reduced to zero and this may still bring in a certain inrush current.Another method is to increase the impedance of the switched-capacitor network.Placing a serial resistor with high resistance could increase the impedance but extra power losses are produced.As shown in Figure 8, this paper proposes to put a small stray inductor L s together with D 2 .In this way, the loop impedance is increased by 2πf s L s and then the inrush current i D2 is reduced to:

Comparative Analysis
Comparative analyses of SC-TLB, SI-TLB, SI-FC-TLB, PI-FC-TLB and the proposed IPOS-SC-TLB are presented in Table 2. L, S, D, and C represent the quantities of inductors, switches, diodes and capacitors, respectively.DS means the quantity of driver supplies and G means the voltage gains.Besides, U VPS , U VPD , and U VPC respectively represent the voltage stresses across switches, diodes, capacitors; and I VPS1 , I VPS2 , and I VPD represent the average current across switches S 1 , S 2 and diodes, respectively."Self-balance" means the input inductor currents could be self-balanced and "same ground" means the input terminal and the output terminal share the same ground.In addition, the voltage gain comparison curves are presented in Figure 9.
From (10), one way to suppress iD2 is to reduce the voltage difference ΔU is by using wide bandgap semiconductors, such as SiC or GaN components that have smaller voltage drops compared with Si-based components.However, ΔU cannot be reduced to zero and this may still bring in a certain inrush current.Another method is to increase the impedance of the switched-capacitor network.Placing a serial resistor with high resistance could increase the impedance but extra power losses are produced.As shown in Figure 8, this paper proposes to put a small stray inductor Ls together with D2.In this way, the loop impedance is increased by 2πfsLs and then the inrush current iD2 is reduced to: . IPOS-SC-TLB with a small stray inductor Ls.Among these seven TLB converters, the common performance parameters are the voltage stress across switches and the input current ripple.The TLB converters based on SI structure need two isolated drive power supplies and have a low voltage gain, while those TLB converters based on PI structure need only one power supply and show a higher voltage gain.The SI-FC-TLB and PI-FC-TLB are very similar except for different interleaved structures.From these two converters, it could be seen that the voltage stresses across the output diodes are low in the SI structure while high in the PI structure; and the average current stresses across switches are high in the SI structure while low in the PI structure.The smaller average current stress across switches should be attributed to the PI structure.Among the five converters, the quantity of components are not the most in the proposed IPOS-SC-TLB, and high voltage gain, small voltage stress and small current stress are achieved.Moreover, voltage-balance control could be easily achieved with the input terminal and the output terminal sharing the same ground.In other words, the proposed IPOS-SC-TLB converter integrates nearly all the merits of the other four TLB converters.However, there is also a disadvantage that the imbalance current between the two power switches S 1 , S 2 .As analyzed in Equation ( 28), the average current of S 2 is U o /R higher than the average current of S 1 .

Comparative Analysis
Energies 2018, 11, x FOR PEER REVIEW 13 of 26 Comparative analyses of SC-TLB, SI-TLB, SI-FC-TLB, PI-FC-TLB and the proposed IPOS-SC-TLB are presented in Table 2. L, S, D, and C represent the quantities of inductors, switches, diodes and capacitors, respectively.DS means the quantity of driver supplies and G means the voltage gains.Besides, UVPS, UVPD, and UVPC respectively represent the voltage stresses across switches, diodes, capacitors; and IVPS1, IVPS2, and IVPD represent the average current across switches S1, S2 and diodes, respectively."Self-balance" means the input inductor currents could be self-balanced and "same ground" means the input terminal and the output terminal share the same ground.In addition, the voltage gain comparison curves are presented in Figure 9.
As the output terminals of Boost I and Boost II are connected in series, the two Boost modules have the same output current.As the average currents across C 1 and C 2 are both equal to zero during one switching period, there is: In addition, the power losses of D 2 and S 2 produced in the switched-capacitor network are small but could not be ignored.But the power losses should be attributed to the Boost II as D 2 and S 2 help formulate the Boost II.As a result, there is: Based on ( 36)-(38), we have: As analyzed above, the two split inductor currents could be self-balanced, but the two output capacitor voltages could not be self-balanced.Considering the voltage drops of IGBT and diode, the voltage difference between C 1 and C 2 could be described by the sum of the voltage drop of one IGBT and the voltage drop of one diode.Besides, the parasitic resistances of L 1 and L 2 are labelled as r L and the parasitic resistance of C f is labelled as r Cf .As the average currents across L 1 and L 2 are high, the voltage drops of parasitic resistances are large and could not be ignored.Under this condition, the two output capacitor voltages could be rewritten as: The two split inductors are designed to attain the same parameters.Owing to the automatic balanced inductor currents, the voltage difference between C 1 and C 2 could be described by: Considering ( 15)-( 42) is further simplified as: It can be seen from ( 43) that the voltage imbalance issue is related to the output characteristic and the parasitic parameters, including the average input current I in , the duty cycle d, the equivalent series resistance r Cf of the flying-capacitor, and the voltage drops of IGBTs and diodes.The capacitances of the two output capacitors have no effect on the voltage imbalance issue, which is quite different from the conventional three-level boost converter shown in Figure 2a.

Three-Loop Control Strategy
To address the voltage imbalance issue and to achieve stale operation of the IPOS-SC-TLB converter, a three-loop control strategy including an output voltage loop, an input current loop and a voltage-balance loop is proposed in this section.The voltage loop and the current loop respectively controls the output voltage and the input inductor currents, while the voltage-balance loop helps alleviate the voltage imbalance issue.However, the voltage loop and the voltage-balance loop will influence each other if no decoupling scheme is employed.To decouple the output voltage loop and the voltage-balance loop, the derivation analysis has been done as follows.
Duty cycles d 1 , d 2 in (44) are both composed of the common duty cycle d and the voltage-balance duty cycles ∆d 1 , ∆d 2 .Also, I L1 , I L2 in (45) are both composed of the average inductor current I L and the voltage-balance inductor current ∆I L1 , ∆I L2 : In the IPOS-SC-TLB converter, the relationship of the input inductor currents and the output current could be described by: (1 By substituting (44) and ( 45) into (46), there is: When the output voltage is not disturbed, the output current variation ∆I o is equal to zero.Thus, (47) could be simplified by: When the IPOS-SC-TLB converter works at stable steady state, ∆I L1 and ∆I L2 indirectly reflect the values of ∆d 1 , ∆d 2 .According to (38), it is not difficult to deduce the following formula: In the three-loop control strategy, to decouple the voltage loop and the voltage-balance loop, the sum of ∆d 1 and ∆d 2 should be equal to zero.Thus, according to (49), there is: Then, the reference inductor currents of Boost I and Boost II could be concluded as follows: According to (51), the three-loop control strategy is presented in Figure 10.The regulators of the output voltage loop and the voltage-balance loop adopt proportional-integral controller while the regulator of the current loop adopts proportional controller.The controllers can be designed based on a small-signal linearized model of the dc/dc converter, which can be developed according to the classic average modeling method for power converters [35,36].The inner current control loop is designed to respond faster than the outer voltage control loop so that the two control loops can be designed independently.As a result, when dealing with the inner loop, we take the outer loop as a constant input.On the other hand, the inner current control loop can be approximated as a simple lag block when we proceed with the voltage loop.The voltage-balance loop has the slowest response.When designing the controller for the voltage-balance loop, the voltage and current control loop can be considered being in steady state already.Classic Bode-plot and root-locus proportional-integral controller design procedures [36] can be used to obtain the parameters for the controllers.Nevertheless, it should be noted that due to the nonlinearity of power devices, the designed controller parameters need to be further tuned for the actual circuit.Besides, the carrier signals C a1 , C a2 are with phase-shifted 180 degrees to realize interleaved scheme for the switches S 1 and S 2 .
Energies 2018, 11, x FOR PEER REVIEW 17 of 26 lag block when we proceed with the voltage loop.The voltage-balance loop has the slowest response.When designing the controller for the voltage-balance loop, the voltage and current control loop can be considered being in steady state already.Classic Bode-plot and root-locus proportional-integral controller design procedures [36] can be used to obtain the parameters for the controllers.Nevertheless, it should be noted that due to the nonlinearity of power devices, the designed controller parameters need to be further tuned for the actual circuit.Besides, the carrier signals Ca1, Ca2 are with phase-shifted 180 degrees to realize interleaved scheme for the switches S1 and S2.The two sampled capacitor voltages UC1, UC2 are added together and then compared with the output voltage reference Uo* to output the average inductor current IL through the voltage loop regulator.ΔIL is achieved through the voltage-balance loop regulator by comparing UC1 and UC2.ΔIL2 equals to −ΔIL1 according to (50).The inductor current references IL1*, IL2* in (51) could be achieved through the decoupled scheme.Then, IL1* and IL2* compares with IL1 and IL2, and pass though the two current loop regulators to output the duty cycles of Boost I and Boost II as follows: When UC1 is bigger than UC2, the voltage-balance process is: ΔIL becomes positive, which makes IL1* decrease and IL2* increase.As a result, d1 decreases while d2 increases, i.e., the turn-on time of S1 decreases while that of S2 increases.Thus, UC1 decreases while UC2 increases.Finally, UC1 equals to UC2 after several switching periods.When UC1 is smaller than UC2, UC1 and UC2 could be also balanced according to a similar voltage-balance process.

Simulation Verification
To verify the correctness and feasibility of the IPOS-SC-TLB converter, a simulation model adopting the proposed three-loop control strategy with 400 W output power has been implemented.The detailed simulation and experimental parameters are presented in Table 3.The two sampled capacitor voltages U C1 , U C2 are added together and then compared with the output voltage reference U o * to output the average inductor current I L through the voltage loop regulator.∆I L is achieved through the voltage-balance loop regulator by comparing U C1 and U C2 .∆I L2 equals to −∆I L1 according to (50).The inductor current references I L1 *, I L2 * in (51) could be achieved through the decoupled scheme.Then, I L1 * and I L2 * compares with I L1 and I L2 , and pass though the two current loop regulators to output the duty cycles of Boost I and Boost II as follows: When U C1 is bigger than U C2 , the voltage-balance process is: ∆I L becomes positive, which makes I L1 * decrease and I L2 * increase.As a result, d 1 decreases while d 2 increases, i.e., the turn-on time of S 1 decreases while that of S 2 increases.Thus, U C1 decreases while U C2 increases.Finally, U C1 equals to U C2 after several switching periods.When U C1 is smaller than U C2 , U C1 and U C2 could be also balanced according to a similar voltage-balance process.

Simulation Verification
To verify the correctness and feasibility of the IPOS-SC-TLB converter, a simulation model adopting the proposed three-loop control strategy with 400 W output power has been implemented.The detailed simulation and experimental parameters are presented in Table 3.The input voltage varies between 48 V and 120 V, and the output voltage is controlled to be stable at 400 V.The switching frequency of the converter is set as 25 kHz.Two inductors are both chosen as about 900 µH with 0.1 ohm equivalent series resistance.Three capacitors are all set as 470 µF with 0.28 ohm equivalent series resistance.Each of the two IGBT switches has a voltage drop of 2.4 V and each of the three diodes has a voltage drop of 2.0 V. Figure 11 shows the simulation results when the input voltage is 48 V and Figure 12 shows the simulation results when the input voltage is 120 V.It can be seen that the IPOS-SC-TLB converter can output a stable dc voltage of 400 V under both the two different input voltages.The voltage difference between U C1 and U C2 is about 20 V under the input voltage 48 V and 10 V under the input voltage 120 V without voltage-balance control.However, once the voltage-balance control loop is added, U C1 and U C2 are balanced with the same voltage 200 V. Besides, in the whole experimental process, a small voltage difference between U C1 and U Cf is about 4.4 V, which is the sum of the voltage drop of one IGBT and the voltage drop of one diode.The input voltage varies between 48 V and 120 V, and the output voltage is controlled to be stable at 400 V.The switching frequency of the converter is set as 25 kHz.Two inductors are both chosen as about 900 μH with 0.1 ohm equivalent series resistance.Three capacitors are all set as 470 μF with 0.28 ohm equivalent series resistance.Each of the two IGBT switches has a voltage drop of 2.4 V and each of the three diodes has a voltage drop of 2.0 V. Figure 11 shows the simulation results when the input voltage is 48 V and Figure 12 shows the simulation results when the input voltage is 120 V.It can be seen that the IPOS-SC-TLB converter can output a stable dc voltage of 400 V under both the two different input voltages.The voltage difference between UC1 and UC2 is about 20 V under the input voltage 48 V and 10 V under the input voltage 120 V without voltage-balance control.However, once the voltage-balance control loop is added, UC1 and UC2 are balanced with the same voltage 200 V. Besides, in the whole experimental process, a small voltage difference between UC1 and UCf is about 4.4 V, which is the sum of the voltage drop of one IGBT and the voltage drop of one diode.More importantly, Figure 13 shows the two split inductor current waveforms of the converter without voltage-balance control and with voltage-balance control when the input voltage is 48 V.Under the condition without voltage-balance control, the average values of the two inductor currents are equal while a little different under the condition with voltage-balance control.Because the duty cycle d1 and the duty cycle d2 are the same under the condition without voltage-balance control but d1 is a little smaller than d2 under the condition with voltage-balance control.Besides, the input current ripple is smaller than the inductor current ripples, and input current ripple frequency is 50 kHz, which is two times the switching frequency 25 kHz.The input voltage varies between 48 V and 120 V, and the output voltage is controlled to be stable at 400 V.The switching frequency of the converter is set as 25 kHz.Two inductors are both chosen as about 900 μH with 0.1 ohm equivalent series resistance.Three capacitors are all set as 470 μF with 0.28 ohm equivalent series resistance.Each of the two IGBT switches has a voltage drop of 2.4 V and each of the three diodes has a voltage drop of 2.0 V. Figure 11 shows the simulation results when the input voltage is 48 V and Figure 12 shows the simulation results when the input voltage is 120 V.It can be seen that the IPOS-SC-TLB converter can output a stable dc voltage of 400 V under both the two different input voltages.The voltage difference between UC1 and UC2 is about 20 V under the input voltage 48 V and 10 V under the input voltage 120 V without voltage-balance control.However, once the voltage-balance control loop is added, UC1 and UC2 are balanced with the same voltage 200 V. Besides, in the whole experimental process, a small voltage difference between UC1 and UCf is about 4.4 V, which is the sum of the voltage drop of one IGBT and the voltage drop of one diode.More importantly, Figure 13 shows the two split inductor current waveforms of the converter without voltage-balance control and with voltage-balance control when the input voltage is 48 V.Under the condition without voltage-balance control, the average values of the two inductor currents are equal while a little different under the condition with voltage-balance control.Because the duty cycle d1 and the duty cycle d2 are the same under the condition without voltage-balance control but d1 is a little smaller than d2 under the condition with voltage-balance control.Besides, the input current ripple is smaller than the inductor current ripples, and input current ripple frequency is 50 kHz, which is two times the switching frequency 25 kHz.More importantly, Figure 13 shows the two split inductor current waveforms of the converter without voltage-balance control and with voltage-balance control when the input voltage is 48 V.Under the condition without voltage-balance control, the average values of the two inductor currents are equal while a little different under the condition with voltage-balance control.Because the duty cycle d 1 and the duty cycle d 2 are the same under the condition without voltage-balance control but d 1 is a little smaller than d 2 under the condition with voltage-balance control.Besides, the input current ripple is smaller than the inductor current ripples, and input current ripple frequency is 50 kHz, which is two times the switching frequency 25 kHz.
Under the condition without voltage-balance control, the average values of the two inductor currents are equal while a little different under the condition with voltage-balance control.Because the duty cycle d1 and the duty cycle d2 are the same under the condition without voltage-balance control but d1 is a little smaller than d2 under the condition with voltage-balance control.Besides, the input current ripple is smaller than the inductor current ripples, and input current ripple frequency is 50 kHz, which is two times the switching frequency 25 kHz.The simulated voltage waveforms and current waveforms are presented in Figure 14.The voltage stress across all power devices are half of the output voltage.The average current across every diode is 1 A, which is the same as the output current.Additionally, the average current across the switch S 2 is bigger than S 1 because the current across the diode D 2 added on the current of S 2 .These results prove correctness of the theoretically derived results shown in (28).On the whole, the simulation results basically verify the effectiveness of the IPOS-SC-TLB converter and the proposed three-loop control strategy.The simulated voltage waveforms and current waveforms are presented in Figure 14.The voltage stress across all power devices are half of the output voltage.The average current across every diode is 1 A, which is the same as the output current.Additionally, the average current across the switch S2 is bigger than S1 because the current across the diode D2 added on the current of S2.These results prove correctness of the theoretically derived results shown in (28).On the whole, the simulation results basically verify the effectiveness of the IPOS-SC-TLB converter and the proposed three-loop control strategy.

Experimental Verification
To verify the converter and three-loop control strategy further, an experimental prototype with the same parameters shown in simulation model is built and it is given in Figure 15.It should be noted that the inductors L1, L2 are respectively designed to be 915 μH, 895 μH with some deviations in fact.The two switches are both selected as IGBT G80N60, which have a voltage drop of 2.4 V and the three diodes are selected as DSEP30-06B, which have a voltage drop of 2.0 V.The control loop of

Experimental Verification
To verify the converter and three-loop control strategy further, an experimental prototype with the same parameters shown in simulation model is built and it is given in Figure 15.It should be noted that the inductors L 1 , L 2 are respectively designed to be 915 µH, 895 µH with some deviations in fact.The two switches are both selected as IGBT G80N60, which have a voltage drop of 2.4 V and the three diodes are selected as DSEP30-06B, which have a voltage drop of 2.0 V.The control loop of the converter was implemented based on Dspace 1103.
Energies 2018, 11, x FOR PEER REVIEW 20 of 26 V under different input voltages.The input current is continuous with a small current ripple and the input current ripple frequency is 50 kHz, which is two times the switching frequency 25 kHz.Moreover, it is easy to observe that as the duty cycle approaches 0.50, the input current ripple becomes almost zero, which verifies (32).i in (5A/div)  The input current and capacitor voltages of the IPOS-SC-TLB converter under different input voltages are presented in Figure 16, and the corresponding capacitor voltages are presented in Figure 17.The inductor currents across L 1 , L 2 and the drive signals of S 1 , S 2 are presented in Figure 18.It can be seen that the output voltage is stable at 400 V and the three capacitor voltages are stable with 200 V under different input voltages.The input current is continuous with a small current ripple and the input current ripple frequency is 50 kHz, which is two times the switching frequency 25 kHz.Moreover, it is easy to observe that as the duty cycle approaches 0.50, the input current ripple becomes almost zero, which verifies (32).
To show voltage stresses across all the switches and diodes, the terminal voltage waveforms of S 1 , S 2 , D 1 , D 2 , and D 3 are presented in Figures 19-21.It should be noted that u S1 , u S2 are defined to describe the voltage difference between the drain terminal and the source terminal of S 1 and S 2 , respectively.u D1 , u D2 , u D3 are the voltage differences between the cathode and the anode of D 1 , D 2 and D 3 .It can be seen that all the voltage stresses of the switches and diodes are 200 V, which is half of the output voltage 400 V.It matches with (12).In addition, the current I S2 is the sum of I S1 and I D2 , which matches with (20) and (21).For example, when the input voltage is 48 V, I S1 , I S2 , I D2 are 3.74 A, 4.78 A and 1.13 A, respectively.It is not difficult to know that the switching state of D 1 is complementary to that of D 2 , and the switching state of D 1 is 180 degrees shifted from that of D 3 .The switching state of S 1 is also 180 degrees shifted from that of S 2 .All of these results can verify the correctness of the operating principle of the IPOS-SC-TLB converter.To show voltage stresses across all the switches and diodes, the terminal voltage waveforms of S1, S2, D1, D2, and D3 are presented in Figures 19-21.It should be noted that uS1, uS2 are defined to describe the voltage difference between the drain terminal and the source terminal of S1 and S2, respectively.uD1, uD2, uD3 are the voltage differences between the cathode and the anode of D1, D2 and D3.It can be seen that all the voltage stresses of the switches and diodes are 200 V, which is half of the output voltage 400 V.It matches with (12).In addition, the current IS2 is the sum of IS1 and ID2, which matches with ( 20) and (21).For example, when the input voltage is 48 V, IS1, IS2, ID2 are 3.74 A, are presented in Figures 22 and 23.The experimental results indicate that when the voltage-balance loop is not added, there is about 13.0 V voltage difference between UC1 and UC2.For example, when the input voltage is 48 V, the tested duty cycle is around 0.83.According to (43), the voltage difference between UC1 and UC2 is 11.26 V under the input voltage of 48 V.The tested voltage difference of 13.00 V basically matches the theoretical value 11.26 V with some voltage error.When the voltage-balance loop is added, the voltage difference becomes nearly zero.Figure 24 shows the theoretical voltage gain and the experimental voltage gain versus duty cycle when Uin is 48 V.It can be seen that the theoretical voltage gain and the experimental voltage gain have the same increasing trend though some deviations exist.The experimental voltage gain basically matches the theoretical voltage gain when the duty cycle varies between 0.2 and 0.5.However, when Figure 24 shows the theoretical voltage gain and the experimental voltage gain versus duty cycle when Uin is 48 V.It can be seen that the theoretical voltage gain and the experimental voltage gain have the same increasing trend though some deviations exist.The experimental voltage gain basically matches the theoretical voltage gain when the duty cycle varies between 0.2 and 0.5.However, when More importantly, the voltage-balance experimental waveforms of the IPOS-SC-TLB converter are presented in Figures 22 and 23.The experimental results indicate that when the voltage-balance loop is not added, there is about 13.0 V voltage difference between U C1 and U C2 .For example, when the input voltage is 48 V, the tested duty cycle is around 0.83.According to (43), the voltage difference between U C1 and U C2 is 11.26 V under the input voltage of 48 V.The tested voltage difference of 13.00 V basically matches the theoretical value 11.26 V with some voltage error.When the voltage-balance loop is added, the voltage difference becomes nearly zero.Figure 24 shows the theoretical voltage gain and the experimental voltage gain versus duty cycle when Uin is 48 V.It can be seen that the theoretical voltage gain and the experimental voltage gain have the same increasing trend though some deviations exist.The experimental voltage gain basically matches the theoretical voltage gain when the duty cycle varies between 0.2 and 0.5.However, when the duty cycle is over 0.50, the experimental theoretical voltage gain is less than the theoretical voltage gain, and their difference increases with the duty-cycle increasing.This phenomenon may be due to the non-linearity of power electronic components and the fact the true values of parasitic parameters are hard to obtain.
The conversion efficiency curves versus output power for the IPOS-SC-TLB converter under different input voltages are given in Figure 25.The minimum efficiency and the maximum efficiency are 92.08% and 94.20%, respectively, at an input voltage of 48 V; 95.13% and 96.55% at the input Figure 24 shows the theoretical voltage gain and the experimental voltage gain versus duty cycle when U in is 48 V.It can be seen that the theoretical voltage gain and the experimental voltage gain have the same increasing trend though some deviations exist.The experimental voltage gain basically matches the theoretical voltage gain when the duty cycle varies between 0.2 and 0.5.However, when the duty cycle is over 0.50, the experimental theoretical voltage gain is less than the theoretical voltage gain, and their difference increases with the duty-cycle increasing.This phenomenon may be due to the non-linearity of power electronic components and the fact the true values of parasitic parameters are hard to obtain.
The conversion efficiency curves versus output power for the IPOS-SC-TLB converter under different input voltages are given in Figure 25.The minimum efficiency and the maximum efficiency are 92.08% and 94.20%, respectively, at an input voltage of 48 V; 95.13% and 96.55% at the input voltage of 72 V; 96.08% and 97.32% at the input voltage 100 V; 96.62% and 98.57% at an input voltage of 120 V.It can be seen that the proposed converter is not efficient in low voltage levels, such as 48 V in the experiment.To make it efficient, the converter should be implemented with optimized design, including component selection, coupling inductor design and applying soft switching technique.For component selection, wide bandgap device (SiC, GaN) with much smaller parasitic parameters should be a good solution, which could not only reduce conduction and switching losses, but also enhance the switching frequency to reduce passive components' size and parasitic parameters as well.Coupling design for the two inductors L 1 and L 2 will help reduce size and improve efficiency of the converter.Soft switching technique applied on this converter will help enhance conversion efficiency.
Energies 2018, 11, x FOR PEER REVIEW 23 of 26 voltage of 72 V; 96.08% and 97.32% at the input voltage 100 V; 96.62% and 98.57% at an input voltage of 120 V.It can be seen that the proposed converter is not efficient in low voltage levels, such as 48 V in the experiment.To make it efficient, the converter should be implemented with optimized design, including component selection, coupling inductor design and applying soft switching technique.For component selection, wide bandgap device (SiC, GaN) with much smaller parasitic parameters should be a good solution, which could not only reduce conduction and switching losses, but also enhance the switching frequency to reduce passive components' size and parasitic parameters as well.Coupling design for the two inductors L1 and L2 will help reduce size and improve efficiency of the converter.Soft switching technique applied on this converter will help enhance conversion efficiency.Based on all the experimental results, the theoretical analysis of the IPOS-SC-TLB converter is correct and the three-loop control strategy is feasible.The effectiveness of the proposed IPOS-SC-TLB converter has been verified.voltage of 72 V; 96.08% and 97.32% at the input voltage 100 V; 96.62% and 98.57% at an input voltage of 120 V.It can be seen that the proposed converter is not efficient in low voltage levels, such as 48 V in the experiment.To make it efficient, the converter should be implemented with optimized design, including component selection, coupling inductor design and applying soft switching technique.For component selection, wide bandgap device (SiC, GaN) with much smaller parasitic parameters should be a good solution, which could not only reduce conduction and switching losses, but also enhance the switching frequency to reduce passive components' size and parasitic parameters as well.Coupling design for the two inductors L1 and L2 will help reduce size and improve efficiency of the converter.Soft switching technique applied on this converter will help enhance conversion efficiency.Based on all the experimental results, the theoretical analysis of the IPOS-SC-TLB converter is correct and the three-loop control strategy is feasible.The effectiveness of the proposed IPOS-SC-TLB converter has been verified.

Conclusions
This paper presents an input-parallel-output-series three-level Boost converter, which can step Based on all the experimental results, the theoretical analysis of the IPOS-SC-TLB converter is correct and the three-loop control strategy is feasible.The effectiveness of the proposed IPOS-SC-TLB converter has been verified.

Conclusions
This paper presents an input-parallel-output-series three-level Boost converter, which can step up the input voltage to a high voltage level, as well as attaining low voltage stress, low current stress and small input current ripple.Another advantage of the proposed topology is the automatic current balancing function.There is also a disadvantage that the imbalance current between the two power switches S 1 , S 2 .The average current of S 2 is U o /R higher than the average current of S 1 .
Author Contributions: J.C. proposed the topology and control strategy, and built the simulation model and experimental prototype.C.W. and J.L. helped do comparative analysis and wrote the paper.
5, the flying-capacitor C f is only discharged during Stage II and the average discharging current flowing through C f is I L2 with the discharging time (1 − d)T s .When d is smaller than 0.5, Energies 2018, 11, 2631 11 of 26 the flying-capacitor C f is discharged during Stage II and Stage IV with the average discharging current I L2 and the total discharged time (1 − d)T s .It can be seen that the decreased charges of C f during one switching period is I L2 *(1 − d)T s no matter what the duty cycle d is.Therefore, by applying Ampere-Second Balance Principle on C f , we have:

Figure 8 .
Figure 8. IPOS-SC-TLB with a small stray inductor L s .

Figure 11 .
Figure 11.Simulated voltage waveforms when U in is 48 V: (a) U o ; (b) U C1 , U C2 , and U Cf .

Figure 12 .
Figure 12.Simulated voltage waveforms when U in is 120 V: (a) U o ; (b) U C1 , U C2 , and U Cf .

Figure 13 .
Figure 13.Simulated current waveforms when Uin is 48 V: (a) without voltage-balance control; (b) with voltage-balance control.

Figure 13 .
Figure 13.Simulated current waveforms when U in is 48 V: (a) without voltage-balance control; (b) with voltage-balance control.

Figure 22 .Figure 22 .Figure 23 .
Figure 22.Voltage balance process of C 1 , C 2 when U in is 48 V: (a) from no voltage-balance control to voltage-balance control; (b) from voltage-balance control to no voltage-balance control.

Figure 23 .
Figure 23.Voltage balance process of C 1 , C 2 when U in is 120 V: (a) from no voltage-balance control to voltage-balance control; (b) from voltage-balance control to no voltage-balance control.

Figure 24 .
Figure 24.The theoretical voltage gain and the experimental voltage gain versus duty cycle when Uin is 48 V.

Figure 24 .
Figure 24.The theoretical voltage gain and the experimental voltage gain versus duty cycle when U in is 48 V.

Figure 24 .
Figure 24.The theoretical voltage gain and the experimental voltage gain versus duty cycle when Uin is 48 V.

Funding:
This research was funded by China Postdoctoral Science Foundation, grant number 2017M612908.Conflicts of Interest: The authors declare no conflict of interest.Nomenclature List of Abbreviations IPOS-SC-TLB input-parallel-output-series switched-capacitor three-level boost HVDC high voltage direct current SI serial-interleaved PI parallel-interleaved SI-TLB serial-interleaved three-level boost PIB parallel-interleaved boost SI-FC-TLB serial-interleaved flying-capacitor three-level boost PI-FC-TLB parallel-interleaved flying-capacitor three-level boost PI-SFC-TLB parallel-interleaved symmetric flying-capacitor three-level boost SC-TLB switched-capacitor three-level boost IPOS-TLB1 input-parallel-output-series three-level boost 1 IPOS-TLB2

Table 1 .
Comparative analysis between SI and PI topologies.

Table 1 .
Comparative analysis between SI and PI topologies.
input-parallel-output-series three-level boost 2 List of Symbols U in average input voltage U o , I o average output voltage and average output currentU o * output voltage reference U C1 , U C2 , U Cf average voltages of capacitors C 1 , C 2 , C f ∆U voltage difference between C 1 and C f , i L1 , i L2 currents of inductors L 1 , L 2 I L1 , I L2 average currents of inductors L 1 , L 2 I L1 *, I L2 * reference currents of inductors L 1 , L 2 ∆i L1 , ∆i L2 current ripples of inductors L 1 , L 2 ∆i in input current ripple I D1 , I D2 , I D3 average currents of diodes D 1 , D 2 , D 3 I S1 , I S2average currents of switches S 1 , S 2