PIDR Sliding Mode Current Control with Online Inductance Estimator for VSC-MVDC System Converter Stations under Unbalanced Grid Voltage Conditions

This study aims to present a novel proportional-integral-derivative-resonant law-based sliding mode current control strategy with online inductance estimator (PIDR-SMCC-OIE) for voltage source converter medium voltage direct current (VSC-MVDC) system converter stations under unbalanced grid voltage conditions. A generalized current reference calculation method, by which the ratio of the amplitude of the active power ripple to that of the reactive power ripple can be continuously controlled without current distortion is presented. A dynamic model of the current control errors in the positive sequence synchronous reference frame is developed, and a PIDR law-based sliding mode current controller is designed, where derivatives of the current references are obtained by simple algebraic operations. An OIE adopting the dynamic filtering method and gradient algorithm is proposed to further improve system robustness. In this OIE, the converter pole voltages are obtained by computation utilizing the gate signals of the switching devices and the DC bus voltage, so that no additional voltage sensors are needed. To verify effectiveness of the PIDR-SMCC-OIE strategy, simulation studies on a two-terminal VSC-MVDC system are conducted in PSCAD/EMTDC. The results show it can provide satisfactory performance over a wide range of operating conditions.


Introduction
Owing to obvious advantages over its AC counterpart in terms of flexibility of power control, transmission capacity, integration of distributed generations (DG) etc., the voltage source converter medium voltage direct current (VSC-MVDC) system-based distribution network (DN) has been attracting ever-increasing interests in recent years [1][2][3][4][5].The operation of the VSC-MVDC system depends on highly controllable power electronic converters.However, the operating conditions of the DN often change violently, parameter uncertainties and different kinds of disturbance always exist, three-phase voltage unbalance is a common phenomenon [6,7].Therefore, the robustness as well as performance of the control strategies for VSC-MVDC system converter stations (CS) under unbalanced grid voltage (UBGV) conditions deserve serious concern.
Current control is one of the most commonly adopted strategies for VSC control.Generally, it is realized in the d-q synchronous reference frame (SRF) by use of the vector-oriented control method [8,9].However, the performance will be decreased under UBGV conditions [10].In order to obtain satisfactory performance in these situations, the currents can be controlled in the positive sequence (PS) SRF or in the static two-phase reference frame (STP RF).In references [11,12], current control strategies in the PS SRF with proportional-integral (PI) plus resonant (PIR) controllers are proposed for modular multi-level converter high voltage DC (MMC-HVDC) system and doubly fed induction generator (DFIG) respectively.In references [13,14], current control strategies in the STP RF are proposed for VSC-HVDC system and MMC respectively, where proportional-resonant (PR) controllers are adopted to realize current tracking function.In references [15,16], current control strategies in the PS SRF with PI plus vector resonant (PIVR) controllers are proposed for DFIG and MMC-HVDC systems respectively.Under general conditions, these linear controllers can provide satisfactory performances.However, the performances are related to the operating points and affected by the nonlinearity feature of VSC.Moreover, as the non-ideal resonant law is often used [17,18], high gains are required to eliminate the steady state errors, which will reduce the stability margins.
Owing to excellent dynamic performance, deadbeat control (DBC) and model predictive control (MPC) have been studied extensively in the control of VSC.In reference [19], a DBC-based current control strategy with current predictive calibration is proposed for grid-connected VSC inverter (VSI).
In reference [20], a multistep MPC-based current control strategy is proposed for cascaded H-bridge inverters.The DBC and MPC can eliminate the steady state errors within several control beats.However, their performances depend heavily on the accuracy of the model and is significantly affected by the time delays in the control loops.To overcome these drawbacks, extra compensation measures have to be taken [21,22], which complicates the controller structure.Besides, generally the DBC and MPC-based control strategies obtain the voltage vector by look-up table.Consequently, the switching frequency is not fixed, which increases the difficulty of the AC side filter design.
To reduce the adverse influences of parameter uncertainty and nonlinearity, many nonlinear control methods have been studied for the control of VSC.In reference [23], a direct Lyapunov control (DLC)-based current control strategy is proposed for integration of DG into the grid.In reference [24], a DLC-based controller with a DC-side voltage regulator in a hierarchical primary control structure is presented for an islanded micro grid.Adoption of DLC ensures asymptotic stability of the system, and in the meantime makes it robust against parameter uncertainty and disturbance.In references [25,26], current control strategies based on differential flatness control (DFC) are proposed for VSC rectifier (VSR) and MMC, respectively.Through design of appropriate flat outputs and planning of the reference trajectories, the control objectives are achieved.At the same time, system robustness is guaranteed by feedback of the control errors and their integrals.An interconnection and damping assignment passivity-based controller is proposed for VSC-HVDC system in reference [27].With this controller, influence of the equivalent resistance of the DC side is eliminated, and as a result dynamic performance of the system is remarkably improved.A droop-passivity-based controller is proposed for grid-connected single-phase VSI to achieve high performance in the presence of nonlinear loads in reference [28].By design of the power capability curves and the current reference generation scheme, precise power sharing and harmonic compensation are achieved.However, in order to achieve accurate current tracking control under UBGV conditions, the resonant law is necessary.Using the above nonlinear methods will probably bring difficulties in constructing the Lyapunov function and design of the controllers.
As a matured nonlinear control method, sliding mode control (SMC) can simplify the system design and is robust against parameter uncertainty and disturbance.As a result, the SMC has been extensively applied the control of power electronic converters [29][30][31][32].In references [6,29] and reference [9], SMC-based direct power control (DPC) strategies and a current control strategy are presented for DFIG and VSC-HVDC system, respectively.In references [4,30], integral SMC-based DPC and current control strategies are presented for VSC-MVDC system and static synchronous Energies 2018, 11, 2599 3 of 20 compensator respectively, where the integral actions are included to achieve accurate power and current control.As the output active and reactive power should contain sinusoidal components to obtain non-distorted AC currents under UBGV conditions, in reference [31] an integral plus resonant SMC-based direct power controller is presented for VSC-HVDC system, to fully eliminate the steady state errors.In reference [32], a controller including three sub-loops with a combined utilization of the passive-injection, DLC and SMC is presented for the MMC-HVDC system.The simulation results show that satisfactory performance is achieved, and at the same time, the circulating currents are significantly reduced and balanced capacitor voltages for the sub-modules are obtained.
In practice, parameters of the controller are the trade-offs between system robustness and the equivalent control bandwidth.One effective way to improve system robustness without obvious dynamic performance reduction is to eliminate the adverse effect of parameter uncertainty.To this purpose, adaptive control-based current control strategies are studied.In references [8,33], adaptive current control strategies for VSC-HVDC system and VSI are proposed respectively.However, the control law and the adaptation law are coupled together.This not only entails a large amount of parameter tuning work, but system performance depends heavily on the behavior of the adaptation law.In reference [34], an MPC-based current control strategy with online disturbance observer (ODO) is proposed for VSR.The ODO is used to identify the lumped effects of parameter uncertainty and disturbance; however, its realization is complex.In reference [35], a predictive control-based sensorless current control strategy for VSR is proposed.However, appropriate excitation signals should be injected to obtain accurate inductance parameters, which complicates the implementation.
On the other hand, the control objectives are important for the operation of VSC-MVDC system under UBGV conditions.In the reported current control strategies, the following four objectives are often applied [8,36], i.e., (1) eliminating the active power ripples at the point of common coupling (PCC); (2) eliminating the reactive power ripples at the PCC; (3) obtaining balanced AC current; and (4) eliminating DC bus voltage ripples.Under general circumstances, these four objectives can meet related requirements.However, they are not sufficient for system operation optimization.In reference [36], a current control strategy to realize soft switching between the first three objectives is presented for DG.However, the oscillating amplitude ratio (OAR) of the active power ripple to the reactive power ripple cannot be continuously controlled.In reference [13], an optimal current control strategy under UBGV conditions is proposed for VSC-HVDC system.In reference [37], a flexible current control strategy to realize coordinated control of the power oscillations and the current quality is proposed.Although the OARs presented in references [13,37] can be controlled continuously, current distortion happens.
This study aims to present a novel proportional-integral-derivative-resonant law-based sliding mode current control strategy with online inductance estimator (PIDR-SMCC-OIE) for VSC-MVDC system converter station under UBGV conditions.The three main contributions of this paper are as follows.First, a generalized current reference calculation (GCRC) method, by which the OAR of the active power ripple to the reactive power ripple can be continuously controlled, is proposed.Second, a PIDR law-based sliding mode controller is proposed for the CS to achieve accurate current control, where the derivatives of the current references are obtained by simple algebraic operations.Third, to further improve system robustness, an OIE based on the dynamic filtering method and the gradient algorithm is presented.This OIE utilizes the gate signals of the switching devices and the DC bus voltage to compute the converter pole voltages, and thus no additional voltage sensors are needed.Finally, simulation studies on a two-terminal VSC-MVDC system are performed in PSCAD/EMTDC to verify the effectiveness of the PIDR-SMCC-OIE strategy.
The remainder of the paper is arranged as follows.In Section 2, a mathematic model of the CS under UBGV conditions is developed, power flow analysis is conducted, and the GCRC method is derived.In Section 3, the PIDR-SMCC controller and the OIE is designed.In Section 4, simulation results on a two-terminal VSC-MVDC system are presented, and in Section 5 conclusions are drawn.

Schematic of the VSC-MVDC System Studied
The single-line diagram of the two-terminal VSC-MVDC system studied is shown in Figure 1.The system mainly consists of two converter stations (CS1 and CS2), the AC filtering inductor and DC bus capacitor for each CS, and the DC transmission lines.To the DC transmission lines, there may be connected loads and DGs.In the figure, the main technical parameters are listed.Those with a unit provided denote the actual physical values and those without a unit denote the per-unit values.

Schematic of the VSC-MVDC System Studied
The single-line diagram of the two-terminal VSC-MVDC system studied is shown in Figure 1.The system mainly consists of two converter stations (CS1 and CS2), the AC filtering inductor and DC bus capacitor for each CS, and the DC transmission lines.To the DC transmission lines, there may be connected loads and DGs.In the figure, the main technical parameters are listed.Those with a unit provided denote the actual physical values and those without a unit denote the per-unit values.

~ ~
A   The structures of the current control loops for each CS are identical, so that their controllers are designed under a unified framework.In addition, assume the grid voltage on each side contains the fundamental components only and that the grid frequency is 50 Hz if not otherwise specified.

Mathematical Model of the CS
Under unbalanced grid voltage conditions, the space vectors of the grid voltage, current and the converter pole voltage can be decomposed into the PS and negative sequence (NS) components.In Figure 3, the space vector of the grid voltage in the PS and NS SRF is shown as an example.The schematic of three-phase VSC for each CS is shown in Figure 2. In the figure, e ga , e gb , e gc , and i ga , i gb , i gc denote the grid voltage and current, respectively; u ca , u cb , u cc denote the converter pole voltage, R g and L g denote the resistance and inductance of the AC filtering inductor; C and u dc denote the DC bus capacitor and voltage respectively.

Schematic of the VSC-MVDC System Studied
The single-line diagram of the two-terminal VSC-MVDC system studied is shown in Figure 1.The system mainly consists of two converter stations (CS1 and CS2), the AC filtering inductor and DC bus capacitor for each CS, and the DC transmission lines.To the DC transmission lines, there may be connected loads and DGs.In the figure, the main technical parameters are listed.Those with a unit provided denote the actual physical values and those without a unit denote the per-unit values.

~ ~
A   The structures of the current control loops for each CS are identical, so that their controllers are designed under a unified framework.In addition, assume the grid voltage on each side contains the fundamental components only and that the grid frequency is 50 Hz if not otherwise specified.

Mathematical Model of the CS
Under unbalanced grid voltage conditions, the space vectors of the grid voltage, current and the converter pole voltage can be decomposed into the PS and negative sequence (NS) components.In Figure 3, the space vector of the grid voltage in the PS and NS SRF is shown as an example.The structures of the current control loops for each CS are identical, so that their controllers are designed under a unified framework.In addition, assume the grid voltage on each side contains the fundamental components only and that the grid frequency is 50 Hz if not otherwise specified.

Mathematical Model of the CS
Under unbalanced grid voltage conditions, the space vectors of the grid voltage, current and the converter pole voltage can be decomposed into the PS and negative sequence (NS) components.In Figure 3, the space vector of the grid voltage in the PS and NS SRF is shown as an example.
. Space vector of the gird voltage in the positive sequence (PS) and negative sequence (NS) synchronous reference frame (SRF).
In Figure 3, the superscript + and − denote the PS and NS SRF, and the subscript + and − denote the PS and NS voltage and current components, respectively.We can see from the figure the PS voltage components rotate in the counter-clockwise direction with the synchronous angular speed ω , the NS voltage components rotate in the clockwise direction with an angular speed of ω − .In the STP RF, the space vectors of the grid voltage gαβ E , grid current gαβ I , and the converter pole voltage cαβ U can be expressed as: where and where gd e + , gd i + , cd u + and gq e + , gq i + , cq u + denote the d and q-axis components of the grid voltage, current and the converter pole voltage in the PS SRF, respectively, and the term denotes the clockwise rotational operator of twice the grid frequency.
In the STP RF, the dynamic model of VSC in space vector from is: In Figure 3, the superscript + and − denote the PS and NS SRF, and the subscript + and − denote the PS and NS voltage and current components, respectively.We can see from the figure the PS voltage components rotate in the counter-clockwise direction with the synchronous angular speed ω, the NS voltage components rotate in the clockwise direction with an angular speed of −ω.
In the STP RF, the space vectors of the grid voltage E gαβ , grid current I gαβ , and the converter pole voltage U cαβ can be expressed as: where E + gdq+ , I + gdq+ , U + cdq+ and E − gdq− , I − gdq− , U − cdq− denote the PS and NS space vectors of the grid voltage, current and the converter pole voltage, respectively, with: and e + gd+ , i + gd+ , u + cd+ and e + gq+ , i + gq+ , u + cq+ denote the d and q-axis PS components of the grid voltage, current and the converter pole voltage in the PS SRF, respectively; e − gd− , i − gd− , u − cd− and e − gq− , i − gq− , u − cq− denote the d and q-axis NS components of the grid voltage, current and the converter pole voltage in the NS SRF, respectively.
Therefore, in the PS SRF, the space vectors of the grid voltage E + gdq , grid current I + gdq and the converter pole voltage U + cdq can be expressed as: where e + gd , i + gd , u + cd and e + gq , i + gq , u + cq denote the d and q-axis components of the grid voltage, current and the converter pole voltage in the PS SRF, respectively, and the term e −j2ωt denotes the clockwise rotational operator of twice the grid frequency.In the STP RF, the dynamic model of VSC in space vector from is: Combine Equations ( 1) and ( 5) to Equations ( 7) and ( 8), mathematic model of the VSC under UBGV conditions in the PS SRF can be obtained as: When the grid voltage is balanced, the NS components of the grid voltage, current and the converter pole voltage are null, which means the dynamic equation in this situation is a special case of the one when the voltage is unbalanced.

Instantaneous Power Flow Analysis
When the grid voltage is unbalanced, instantaneous power at the PCC can be calculated as: where I + gdq denotes the complex conjugate of the current vector.Substitute Equations ( 2) and (3) into Equation (10) and through some mathematical manipulations, the active power and reactive power at the PCC can be obtained as: where P g0 and Q g0 denote the average components, P gcos2 , P gsin2 and Q gcos2 , Q gsin2 denote the ripple components of the active power and reactive power respectively.For convenience, the power terms can be expressed in the following compact form: From Equation (12) we can see that it is the interaction between the PS (NS) voltage and the NS (PS) current that produces the active and reactive power ripples.
Similarly, the active power ripple terms at the AC side of VSC can be calculated as: where P ccos2 and P csin2 denote the instantaneous active power ripples, which are sinusoidal signals of twice the grid frequency.
Similarly, the apparent power S L , active power P L and the reactive power Q L , consumed in the AC filtering inductor can be calculated as: It can be seen from Equation ( 14) when the AC current is unbalanced, the instantaneous reactive power consumed in the inductor is constant, while the instantaneous active power it consumed is not zero but sinusoidal components of twice the grid frequency.

Conventional Current Reference Calculation Method
For convenience, the conventional current control objectives (OBJ) without current distortion and the corresponding current reference calculation methods are directly given below.OBJ 1: Eliminating the active power ripples at the PCC To achieve this objective, the current references are calculated as: where k dd and k qd are: k dd = e − gd− /e + gd+ , k qd = e − gq− /e + gd+ .OBJ 2: Eliminating the reactive power ripples at the PCC Similarly, the current references of this objective are: OBJ 3: Obtaining three-phase balanced current The current references for this objective are: OBJ 4: Eliminating DC bus voltage ripples The active power ripples pass through the VSC should be eliminated to achieve constant DC bus voltage.To this purpose, we can have: Then, the current references for this control objective can be obtained as: which indicates the NS current components are necessary to eliminate the DC bus voltage ripples.

The Proposed GCRC Method
The previous four control objectives can meet the related requirements for many applications.However, they are not sufficient for system optimization.In this paper, a GCRC method is presented to make the OAR of the active power ripple to the reactive power ripple continuously controllable, namely, OBJ 5.The current references of this GCRC method are calculated as: where k sk denotes the slack coefficient.Substitute Equation (20) into Equation ( 12), we have: From Equation ( 21) we can see P g0 and Q g0 are not affected by k sk .When k sk = 1, P gsin2 and P gcos2 are zero, Q gsin2 and Q gcos2 are at their peaks Q gsin2m and Q gcos2m .When k sk = −1, Q gsin2 and Q gcos2 are zero, P gsin2 and P gcos2 are at their peaks P gsin2m and P gcos2m .As k dd and k qd are very small in practice, the amplitude of the active power ripples and that of the reactive power ripples change almost linearly with k sk , and moreover, if the influences of the square terms of k dd and k qd in the denominators are neglected, it can be inferred from Equation (22) to Equation ( 25) In Figure 4, an example is given to show the relationships between P gsin2 , P gcos2 , Q gsin2 , Q gcos2 and k sk .In the figure, k dd = −0.13,k qd = −0.006,P * g0 = 0.9 p.u, Q * g0 = −0.2p.u.
Energies 2018, 11, x FOR PEER REVIEW 9 of 20 In Figure 4, an example is given to show the relationships between Pgsin2, Pgcos2, Qgsin2, Qgcos2 and ksk.In the figure ,   Suppose Pgcos2m, Qgsin2m and Pgsin2m, Qgcos2m are Am and Bm respectively, then we have: The amplitudes of the active power ripples rplam P and the reactive power ripples rplam Q can be obtained as: ( ) From Equations ( 28) and ( 29) we can see the amplitudes of the reactive power ripples decrease from the maximum to zero and that of the active power ripples increase from zero to the maximum, as ksk changes from 1 to −1.When sk 0 k = , the amplitudes of the active power ripples and the reactive power ripples equal, which corresponds to the situation of obtaining balanced AC currents.

Dynamics of the Current Control Errors in the PS SRF
Define the d and q-axis current references as where these include the derivatives of the current references.
The NS current references can be expressed in the PS SRF as: where * gd i + − and * gq i + − are the d and q-axis NS current references in the PS SRF, respectively.Suppose P gcos2m , Q gsin2m and P gsin2m , Q gcos2m are A m and B m respectively, then we have: The amplitudes of the active power ripples P rplam and the reactive power ripples Q rplam can be obtained as: From Equations ( 28) and ( 29) we can see the amplitudes of the reactive power ripples decrease from the maximum to zero and that of the active power ripples increase from zero to the maximum, as k sk changes from 1 to −1.When k sk = 0, the amplitudes of the active power ripples and the reactive power ripples equal, which corresponds to the situation of obtaining balanced AC currents.

Dynamics of the Current Control Errors in the PS SRF
Define the d and q-axis current references as i + * gd and i + * gq , and the respective current control errors as i + ged and i + geq respectively.Taking i + ged and i + geq as the state variables, the dynamics of the current control errors can be obtained as: where these include the derivatives of the current references.
The NS current references can be expressed in the PS SRF as: where i + * gd− and i + * gq− are the d and q-axis NS current references in the PS SRF, respectively.
Energies 2018, 11, 2599 10 of 20 The current in the PS SRF can be expressed as: As i + * gd+ and i + * gq+ are DC components, then we have: Combine Equation (31) to Equation ( 33), the derivatives of the d-and q-axis current references in the PS SRF can be obtained as: (35) which means that the derivatives of the current references can be obtained through simple algebraic operations, which simplifies the implementation of the controller.

PIDR-SMCC Current Controller Design
Transform the current control error equations Equation ( 30 T denotes the control input vector, and T denotes the nonlinear functions in the dynamic model, with: where diag(a 1 , a 2 ) denotes a diagonal matrix with a 1 and a 2 as the main diagonal elements, δ + gd (t, x) and δ + gq (t, x) denote the lumped uncertainties in the d-and q-axis current control sub-systems.
In the following, the arguments of various functions will not be written for convenience.Assume δ + gd and δ + gq satisfy: with ρ mgd and ρ mgq denoting the upper bounds of the respective uncertainties.Design the sliding manifold (SM) for the d-and q-axis current control subsystems as: with: where p denotes the Laplace operator, ω R = 2ω denotes the resonant frequency, ω c denotes the bandwidth parameter of the resonant law, K PId , K PIq , K Rd and K Rq are positive real numbers.The derivative of s is: with: Utilizing V = s T s/2 as the Lyapunov function candidate, then the derivative of V along system state trajectories can be obtained as: Design the control law u as: with: where η d > ρ md , η q > ρ mq and K sd > 0, K sq > 0.Then, we have: which indicates that the system is stable.
From the definition of the SM and Barbalat s Lemma it can be inferred that the DC components of the current control errors will converge to zero.In the following, we will prove convergence of the sinusoidal components to zero using the method of reduction to absurdity.Suppose the sinusoidal components of i + ged and i + geq will not converge to zero.Then, there will be sinusoidal components in s d and s q , and consequently, V will fluctuate in a sine-wave pattern.From Equation (49) we know that V is non-increasing, which contradicts the assumption.Therefore, i + ged and i + geq will converge to zero.

Online Inductance Estimator Design
The grid voltage, current and the converter pole voltage always satisfy the Kirchhoff's voltage law.This feature can be used for AC line parameter estimation.The AC voltages of the VSC (u cabc ) is required for the OIE design.In this paper we utilize the gate signals of the switching devices and the DC bus voltage to compute u cabc , instead of measuring it, so that no additional sensors are needed.To this purpose, we firstly change the non-ideal converter bridge into an ideal one as shown in Figure 5.

Online Inductance Estimator Design
The grid voltage, current and the converter pole voltage always satisfy the Kirchhoff's voltage law.This feature can be used for AC line parameter estimation.The AC voltages of the VSC (ucabc) is required for the OIE design.In this paper we utilize the gate signals of the switching devices and the DC bus voltage to compute ucabc, instead of measuring it, so that no additional sensors are needed.To this purpose, we firstly change the non-ideal converter bridge into an ideal one as shown in Figure 5.In the figure, Rt represents the overall resistance of each AC line branch, including the effects introduced by the forward voltage drop of each arm, ucabc represents the converter pole voltage of this ideal VSC.Meanings of the other symbols are the same as those defined in Figure 2.

Inductance Parameter Estimation Model
In the a-b-c RF, the current dynamic model is: z e u = − , then Equation (50) can be expressed as: Filtering each side of Equation ( 52) with a first-order filter f M , i.e., multiply each side by ) with f λ being a known positive real constant.Then, we have: ( ) where , and: Express Equation (53) as where ha denotes the true parameter values that vary sufficiently slow.In the figure, R t represents the overall resistance of each AC line branch, including the effects introduced by the forward voltage drop of each arm, u cabc represents the converter pole voltage of this ideal VSC.Meanings of the other symbols are the same as those defined in Figure 2.

Inductance Parameter Estimation Model
In the a-b-c RF, the current dynamic model is: with: and s k denotes the switching function.Denote y = i gk and z = e gk − u ck , then Equation (50) can be expressed as: Filtering each side of Equation ( 52) with a first-order filter M f , i.e., multiply each side by 1/(p + λ f ) with λ f being a known positive real constant.Then, we have: where h 1 = R gt /L g , h 2 = 1/L g , and: Express Equation (53) as y = Wh a with: where h a denotes the true parameter values that vary sufficiently slow.

The Gradient Algorithm Define h p = [ h 1p h 2p ]
T and h d = [ h 1d h 2d ] T = h p − h a as the estimation results at time t and the errors between the true values and the estimated values, respectively.Then, the predicted output at time t is y p = Wh p .Assume y pa is the error between the predicted output and the actual output, i.e., Choose the adaptation law as: where γ = diag(γ 1 , γ 2 ) > 0 denotes the adaptation gain matrix.Substituting Equation (55) into Equation ( 56) yields: Utilizing V a = h d T γ −1 h d as the Lyapunov function candidate, then the derivative of V a along the state trajectories can be obtained as: which means this OIE is always stable and the parameter estimation errors keep decreasing.
In reference [38], convergence of the estimation results is proved.As the process is much involved, only the results are given here: If the input signals meet the persisting excitation condition, convergence of the estimation results is ensured.For the linear system in Equation ( 53), m sinusoidal signals in the input guarantees accurate estimation of at least 2m parameters [39].For this OIE, there is at least the grid voltage components in w 2 , so that convergence of two parameter estimation results can be ensured, i.e., h p converges to h a is proved.

Block Diagram of the PIDR-SMCC-OIE Strategy
Block diagram of the PIDR-SMCC-OIE current control strategy under UBGV conditions is as shown in Figure 6.In the figure, PLL denotes the phase-locked loop, SCE denotes sequence component extraction, and SVPWM denotes space vector pulse width modulation.
Energies 2018, 11, x FOR PEER REVIEW 13 of 20 Then, the predicted output at time t is p p y Wh = .Assume ypa is the error between the predicted output and the actual output, i.e., Choose the adaptation law as: diag , 0 γ γ γ = > denotes the adaptation gain matrix.
Substituting Equation (55) into Equation (56) yields: Utilizing as the Lyapunov function candidate, then the derivative of a V along the state trajectories can be obtained as: which means this OIE is always stable and the parameter estimation errors keep decreasing.
In reference [38], convergence of the estimation results is proved.As the process is much involved, only the results are given here: If the input signals meet the persisting excitation condition, convergence of the estimation results is ensured.For the linear system in Equation ( 53), m sinusoidal signals in the input guarantees accurate estimation of at least 2m parameters [39].For this OIE, there is at least the grid voltage components in w2, so that convergence of two parameter estimation results can be ensured, i.e., hp converges to ha is proved.

Block Diagram of the PIDR-SMCC-OIE Strategy
Block diagram of the PIDR-SMCC-OIE current control strategy under UBGV conditions is as shown in Figure 6.In the figure, PLL denotes the phase-locked loop, SCE denotes sequence component extraction, and SVPWM denotes space vector pulse width modulation.We can see from the figure that the control structure is simple, and moreover, the PIDR-SMCC controller and the OIE are decoupled, so that they can be designed independently.We can see from the figure that the control structure is simple, and moreover, the PIDR-SMCC controller and the OIE are decoupled, so that they can be designed independently.

General Configuration
To verify the effectiveness of the PIDR-SMCC-OIE strategy, simulation studies are conducted on the two-terminal VSC-MVDC system in PSCAD/EMTDC.In the simulations, CS1 and CS2 are operated as rectifier and inverter respectively, the loads and DGs connected to the DC transmission lines are taken as lumped active power disturbances.
The main parameters of the PIDR-SMCC-OIE controller are listed in Table 1.

Parameters Value
The per-unit values are used in the simulation results.The AC and DC voltage bases are 10 kV and 20 kV respectively.The power base is 15 MVA and the inductance base is 12 mH.To maintain the DC voltage along the transmission line within specified range, the DC bus voltage on CS1 side is controlled at 1.025 p.u.In addition, in order to facilitate the waveform display, the simulation data in PSCAD/EMTDC are imported into MATLAB (R2016a) for plotting.
The symbols used in the simulation results and their meanings are listed in Table 2.
Table 2. Symbols used in the simulation results and their meanings.

Symbol Meaning
u dc1 , u dc2 DC bus voltage of CS1 and CS2 E g1 , E g2 Three-phase grid voltage on CS1 and CS2 side I g1 , I g2 Three-phase AC current on CS1 and CS2 side P g1 , Q g1 , P g2 , Q g2 Active and reactive power exchange at the PCC of CS1 and CS2 L g1 , L g2 The estimated inductance for CS1 and CS2

Simulation Results
For convenience, define the following specified operating condition (SOC), under which most of the simulation studies are conducted.Initially, the grid voltage is three-phase balanced.At 0.1 s, single-phase to ground faults happen to phase A of AC bus B 1 and phase C of AC bus B 2 .At 0.2 s, both the faults are cleared and the grid voltages restore to the initial states.The voltage waveforms at PCC1 and PCC2 are as shown in Figure 7. Besides, the inductance of the AC inductors for both CS are set to 75% of the nominal values if not otherwise specified, to investigate robustness of the system.

General Configuration
To verify the effectiveness of the PIDR-SMCC-OIE strategy, simulation studies are conducted on the two-terminal VSC-MVDC system in PSCAD/EMTDC.In the simulations, CS1 and CS2 are operated as rectifier and inverter respectively, the loads and DGs connected to the DC transmission lines are taken as lumped active power disturbances.
The main parameters of the PIDR-SMCC-OIE controller are listed in Table 1.The per-unit values are used in the simulation results.The AC and DC voltage bases are 10 kV and 20 kV respectively.The power base is 15 MVA and the inductance base is 12 mH.To maintain the DC voltage along the transmission line within specified range, the DC bus voltage on CS1 side is controlled at 1.025 p.u.In addition, in order to facilitate the waveform display, the simulation data in PSCAD/EMTDC are imported into MATLAB (R2016a) for plotting.
The symbols used in the simulation results and their meanings are listed in Table 2.
Table 2. Symbols used in the simulation results and their meanings.

Symbol Meaning udc1, udc2
DC bus voltage of CS1 and CS2 Eg1, Eg2 Three-phase grid voltage on CS1 and CS2 side Ig1, Ig2 Three-phase AC current on CS1 and CS2 side Pg1, Qg1, Pg2, Qg2 Active and reactive power exchange at the PCC of CS1 and CS2 Lg1, Lg2 The estimated inductance for CS1 and CS2

Simulation Results
For convenience, define the following specified operating condition (SOC), under which most of the simulation studies are conducted.Initially, the grid voltage is three-phase balanced.At 0.1 s, single-phase to ground faults happen to phase A of AC bus B1 and phase C of AC bus B2.At 0.2 s, both the faults are cleared and the grid voltages restore to the initial states.The voltage waveforms at PCC1 and PCC2 are as shown in Figure 7. Besides, the inductance of the AC inductors for both CS are set to 75% of the nominal values if not otherwise specified, to investigate robustness of the system.
(a) (b)  In Figure 8 the responses of CS1 and CS2 to the SOC for OBJ 1 and OBJ 2 respectively are shown.From Figure 8 we can see the active power ripples at PCC1 and the reactive power ripples at PCC2 are fully eliminated without current distortion, with the PIDR-SMCC controller.Moreover, the transient performances for both CS are satisfactory.In Figure 9 From Figure 9 we can see the expected control objectives are achieved with the combined function of the GCRC method and the PIDR-SMCC controller.The OAR for CS1 is about 1/3 and that for CS2 is about 3, which is consistent with the theoretical analysis.Figure 10 shows the responses of CS1 and CS2 to the SOC with PIVR controller and PIR controller, respectively.The inductances of the AC inductors for both CS are the nominal values, the control objectives are the same as those in Figure 8.The proportional and integral gains of the two controllers are 1500 and 30,000 respectively.The resonant gains are 18,000 for the PIR controller and 40 for the PIVR controller.From Figure 8 we can see the active power ripples at PCC1 and the reactive power ripples at PCC2 are fully eliminated without current distortion, with the PIDR-SMCC controller.Moreover, the transient performances for both CS are satisfactory.In Figure 9, responses of CS1 and CS2 to the SOC for the control objectives of OBJ 5 are shown.For CS1, k sk = 0.5; for CS2, k sk = −0.5.From Figure 8 we can see the active power ripples at PCC1 and the reactive power ripples at PCC2 are fully eliminated without current distortion, with the PIDR-SMCC controller.Moreover, the transient performances for both CS are satisfactory.In Figure 9 From Figure 9 we can see the expected control objectives are achieved with the combined function of the GCRC method and the PIDR-SMCC controller.The OAR for CS1 is about 1/3 and that for CS2 is about 3, which is consistent with the theoretical analysis.Figure 10 shows the responses of CS1 and CS2 to the SOC with PIVR controller and PIR controller, respectively.The inductances of the AC inductors for both CS are the nominal values, the control objectives are the same as those in Figure 8.The proportional and integral gains of the two controllers are 1500 and 30,000 respectively.The resonant gains are 18,000 for the PIR controller and 40 for the PIVR controller.From Figure 9 we can see the expected control objectives are achieved with the combined function of the GCRC method and the PIDR-SMCC controller.The OAR for CS1 is about 1/3 and that for CS2 is about 3, which is consistent with the theoretical analysis.Figure 10 shows the responses of CS1 and CS2 to the SOC with PIVR controller and PIR controller, respectively.The inductances of the AC inductors for both CS are the nominal values, the control objectives are the same as those in Figure 8.The proportional and integral gains of the two controllers are 1500 and 30,000 respectively.The resonant gains are 18,000 for the PIR controller and 40 for the PIVR controller.We can see from Figure 10 the steady state performances of both CS are satisfactory with the PIVR and PIR controllers, respectively.However, these are obtained by high controller gains, which will reduce the stability margins.To investigate robustness of the two controllers, responses of CS1 and CS2 to the SOC with reduced AC inductances are shown in Figure 11.In this figure, the grid voltage conditions and the control objectives are the same as those for Figure 10   From Figure 11a we can see that the performances of both CS get worse when the inductances of the AC inductors are reduced by 20%.This is because the reduction of the inductances is equivalent to increase of the control gains.As a result, the system is approaching the stability boundary as the inductance decreases.In Figure 12, the responses of CS1 and CS2 to the SOC with the function of the PIDR-SMCC-OIE controller are shown.The inductances of the AC inductors are 0.7 p.u for both CS, and the control objectives for CS1 and CS2 are to eliminate the active power ripples at PCC1 and to obtain balanced three-phase currents, respectively.We can see from Figure 10 the steady state performances of both CS are satisfactory with the PIVR and PIR controllers, respectively.However, these are obtained by high controller gains, which will reduce the stability margins.To investigate robustness of the two controllers, responses of CS1 and CS2 to the SOC with reduced AC inductances are shown in Figure 11.In this figure, the grid voltage conditions and the control objectives are the same as those for Figure 10 and the inductances of the AC inductors are set to 80% of the nominal values for both CS.We can see from Figure 10 the steady state performances of both CS are satisfactory with the PIVR and PIR controllers, respectively.However, these are obtained by high controller gains, which will reduce the stability margins.To investigate robustness of the two controllers, responses of CS1 and CS2 to the SOC with reduced AC inductances are shown in Figure 11.In this figure, the grid voltage conditions and the control objectives are the same as those for Figure 10   From Figure 11a we can see that the performances of both CS get worse when the inductances of the AC inductors are reduced by 20%.This is because the reduction of the inductances is equivalent to increase of the control gains.As a result, the system is approaching the stability boundary as the inductance decreases.In Figure 12, the responses of CS1 and CS2 to the SOC with the function of the PIDR-SMCC-OIE controller are shown.The inductances of the AC inductors are 0.7 p.u for both CS, and the control objectives for CS1 and CS2 are to eliminate the active power ripples at PCC1 and to obtain balanced three-phase currents, respectively.From Figure 11a we can see that the performances of both CS get worse when the inductances of the AC inductors are reduced by 20%.This is because the reduction of the inductances is equivalent to increase of the control gains.As a result, the system is approaching the stability boundary as the inductance decreases.In Figure 12, the responses of CS1 and CS2 to the SOC with the function of the PIDR-SMCC-OIE controller are shown.The inductances of the AC inductors are 0.7 p.u for both CS, and the control objectives for CS1 and CS2 are to eliminate the active power ripples at PCC1 and to obtain balanced three-phase currents, respectively.From Figure 13 we can see that the DC bus voltage ripples on both sides are fully eliminated.The inductance estimation results deviate from the true values for both CS, during the power step-up.However, they are still accurate with relative errors no greater than ±1%.In Figure 14, the    From Figure 13 we can see that the DC bus voltage ripples on both sides are fully eliminated.The inductance estimation results deviate from the true values for both CS, during the power step-up.However, they are still accurate with relative errors no greater than ±1%.In Figure 14, the From Figure 13 we can see that the DC bus voltage ripples on both sides are fully eliminated.The inductance estimation results deviate from the true values for both CS, during the power step-up.However, they are still accurate with relative errors no greater than ±1%.In Figure 14  In this case, the grid voltages are the same as those in Figure 13 and the control objectives are the same as those in Figure 8, for both CS.Initially, the inductances of the AC inductors are 1.0 p.u; at 0.05 s, they are stepped to 0.5 p.u and then stepped back to 1.0 p.u at 0.2 s.
We can see from Figure 14 that the OIE tracks rapidly and accurately the inductance changes all through the process.As a result, the steady state performances of CS1 and CS2 are satisfactory with the PIDR-SMCC-OIE controller even in the presence of the combined effects of voltage disturbances and inductance parameter step changes, although it takes longer time for both CS to settle down.

Conclusions
In this paper, a PIDR law-based sliding mode current control strategy with online inductance estimator (i.e., the PIDR-SMCC-OIE strategy) is presented for VSC-MVDC system converter station, under unbalanced grid voltage conditions.The main conclusions are as the following.First, through adding a slack coefficient to the conventional current reference calculation equations, the ratio of the active power ripple amplitude to that of the reactive power ripple can be continuously controlled without current distortion.Second, adoption of the SMC method simplifies the controller design and guarantees closed-loop stability of the system in the Lyapunov sense in the presence of parameter uncertainty and disturbance.Moreover, derivatives of the current references are obtained by simple algebraic operations, which facilitate the implementation of the controller.Third, the OIE presented is easy to implement with no additional sensors needed, and it can provide accurate estimates under both balanced and unbalanced grid voltage conditions.Fourth, application of the Barbalat′s lemma and the reduction to absurdity method proves convergence of the current control errors to zero.Theoretical analysis and simulation studies in PSCAD/EMTDC verify the effectiveness and superiority of the proposed PIDR-SMCC-OIE strategy.

Figure 1 .
Figure 1.Single-line diagram of the two-terminal voltage source converter medium voltage direct current (VSC-MVDC) system studied.

Figure 2 .
Figure 2. Schematic of three-phase VSC for each converter station.

Figure 1 .
Figure 1.Single-line diagram of the two-terminal voltage source converter medium voltage direct current (VSC-MVDC) system studied.

Figure 1 .
Figure 1.Single-line diagram of the two-terminal voltage source converter medium voltage direct current (VSC-MVDC) system studied.

Figure 2 .
Figure 2. Schematic of three-phase VSC for each converter station.

Figure 2 .
Figure 2. Schematic of three-phase VSC for each converter station.

Figure 3 .
Figure 3. Space vector of the gird voltage in the positive sequence (PS) and negative sequence (NS) synchronous reference frame (SRF).

Figure 4 .
Figure 4.An example to show the relationships between P gsin2 , P gcos2 , Q gsin2 , Q gcos2 and k sk .
) into the following compact form: dx dt = F(x) + G(x)u + δ(t, x) − dx r dt , where x = [ i + ged i + geq ] T denotes the state vector, x r = [ x rd x rq ] T denotes the current reference vector, u = [ u + d u + q ]

Figure 5 .
Figure 5. Schematic of VSC system with ideal switch.

Figure 5 .
Figure 5. Schematic of VSC system with ideal switch.

Figure 7 .
Figure 7.The grid voltage waveforms of the specified operating condition (SOC) for CS1 (a) and CS2 (b).

Figure 7 .
Figure 7.The grid voltage waveforms of the specified operating condition (SOC) for CS1 (a) and CS2 (b).

Figure 9 .
Figure 9. Responses of CS1 (a) and CS2 (b) to the SOC for OBJ 5.

Figure 8 .
Figure 8. Responses of CS1 (a) and CS2 (b) to the SOC for OBJ 1 and OBJ 2 respectively.

Figure 9 .
Figure 9. Responses of CS1 (a) and CS2 (b) to the SOC for OBJ 5.

Figure 9 .
Figure 9. Responses of CS1 (a) and CS2 (b) to the SOC for OBJ 5.
and the inductances of the AC inductors are set to 80% of the nominal values for both CS.

Figure 11 .
Figure 11.Responses of CS1 (a) and CS2 (b) to the SOC by the PIVR and PIR controllers with 20% reduced inductances respectively.

Figure 10 .
Figure 10.Responses of CS1 (a) and CS2 (b) to the SOC with proportional-integral plus vector resonant and proportional-integral plus resonant (PIR) controllers respectively.
and the inductances of the AC inductors are set to 80% of the nominal values for both CS.

Figure 11 .
Figure 11.Responses of CS1 (a) and CS2 (b) to the SOC by the PIVR and PIR controllers with 20% reduced inductances respectively.

Figure 11 .
Figure 11.Responses of CS1 (a) and CS2 (b) to the SOC by the PIVR and PIR controllers with 20% reduced inductances respectively.

Figure 12 .
Figure 12.Responses of CS1 (a) and CS2 (b) to the SOC with the function of the PIDR-SMCC-OIE controller for OBJ 1 and OBJ 3 respectively.From Figure12we can see both the transient and steady state performances of CS1 and CS2 are satisfactory with the PIDR-SMCC-OIE controller, and the inductance estimation results converge to the true values under both balanced and unbalanced grid voltage conditions.In Figure13, responses of CS1 and CS2 to active power step changes and the SOC under UBGV conditions are shown.The initial average active power demand for CS2 is −0.6 p.u.At 0.1 s, this figure steps up to −0.8 p.u and then stepped back to −0.6 p.u at 0.2 s.The inductances of the AC inductors are 0.7 p.u and the control objectives are to eliminate the DC bus voltage ripples, for both CS.

Figure 13 .
Figure 13.Responses of CS1 (a) and CS2 (b) to active power step changes under unbalanced grid voltage (UBGV) conditions for obtaining constant DC bus voltage.

Figure 12 .
Figure 12.Responses of CS1 (a) and CS2 (b) to the SOC with the function of the PIDR-SMCC-OIE controller for OBJ 1 and OBJ 3 respectively.From Figure12we can see both the transient and steady state performances of CS1 and CS2 are satisfactory with the PIDR-SMCC-OIE controller, and the inductance estimation results converge to the true values under both balanced and unbalanced grid voltage conditions.In Figure13, responses of CS1 and CS2 to active power step changes and the SOC under UBGV conditions are shown.The initial average active power demand for CS2 is −0.6 p.u.At 0.1 s, this figure steps up to −0.8 p.u and then stepped back to −0.6 p.u at 0.2 s.The inductances of the AC inductors are 0.7 p.u and the control objectives are to eliminate the DC bus voltage ripples, for both CS.

Figure 12 .
Figure 12.Responses of CS1 (a) and CS2 (b) to the SOC with the function of the PIDR-SMCC-OIE controller for OBJ 1 and OBJ 3 respectively.From Figure 12 we can see both the transient and steady state performances of CS1 and CS2 are satisfactory with the PIDR-SMCC-OIE controller, and the inductance estimation results converge to the true values under both balanced and unbalanced grid voltage conditions.In Figure 13, responses of CS1 and CS2 to active power step changes and the SOC under UBGV conditions are shown.The initial average active power demand for CS2 is −0.6 p.u.At 0.1 s, this figure steps up to −0.8 p.u and then stepped back to −0.6 p.u at 0.2 s.The inductances of the AC inductors are 0.7 p.u and the control objectives are to eliminate the DC bus voltage ripples, for both CS.

Figure 13 .
Figure 13.Responses of CS1 (a) and CS2 (b) to active power step changes under unbalanced grid voltage (UBGV) conditions for obtaining constant DC bus voltage.

Figure 13 .
Figure 13.Responses of CS1 (a) and CS2 (b) to active power step changes under unbalanced grid voltage (UBGV) conditions for obtaining constant DC bus voltage.
, the responses of both CS to inductance parameter step changes under UBGV conditions are shown to investigate the tracking performance of the OIE.

Figure 14 .
Figure 14.Responses of CS1 (a) and CS2 (b) to inductance parameter step changes under UBGV conditions.