A Modular ACDC Power Converter with Zero Voltage Transition for Electric Vehicles

A study of the fundamental of operation of a three-phase AC-DC power converter that uses Zero-Voltage Transition (ZVT) together with Space Vector Pulse Width Modulation (SVPWM) is presented. The converter is basically an active rectifier divided into two converters: a matrix converter and an H bridge, which transfer energy through a high-frequency transformer, resulting in a modular AC-DC wireless converter appropriate for Plug-in Electric Vehicles (PEVs). The principle of operation of this converter considers high power quality, output regulation and low semiconductor power loss. The circuit operation, idealized waveforms and modulation strategy are explained together with simulation results of a 5 kW design.


Introduction
AC-DC power converters are typically used in Plug-in Electric Vehicles (PEVs) that require high reliability, reduced total harmonic distortion (THD) of the drawn currents and output regulation to charge batteries or supercapacitors with high performance and satisfy stringent power quality and density standards [1][2][3].Electric Vehicle (EV) systems need to consider power quality regulations that typically include the harmonic emission during the charging and transient states, which have been analyzed with different standards and methods as the works described in [4,5].Moreover, high-frequency switching techniques can increase the power quality, density and energy transfer reliability of AC-DC power converters without altering the basic topology configuration, keeping output controllability and reliability [6]; however, high AC line currents, drawn by the converter to rapidly charge the storage devices distributed along the traction DC link of the EV, may endanger the EV charger operator or impair the charger connector and, therefore, the supply drawn currents are limited to gain reliability causing slow energy transfer [7].
An available method of ensuring operator reliability with high currents, obtaining a simple way of connecting the charge uses wireless power transfer [8][9][10].This is a twofold method, since the technique commonly uses a transformer to effectively isolate the power transfer from the user, and provides possible circuit splitting since the transformer is operated as an intermediary between two modules.For example, the converter presented in [11] uses a Medium-Frequency-Transformer for wind power conversion applications; however, the system uses an indirect matrix converter with three output phases that increases the circuit complexity and the magnetic components.EVs typically us two modules, where the first module is located on a charging station and the other on board the vehicle, improving the power density of the converter and increasing the EV distance range since the on-board The topology arises from the idea of splitting a conventional active rectifier in two modules as is shown in Figure 1.The off-board module of the converter is a three-phase current fed matrix converter that generates a single phase high-frequency current.This converter is intended to be located outside the electric vehicle in the charging station.The matrix converter has six bi-directional switches (Q1-Q6) and is fed by the line current of inductors L. The primary side of a high-frequency transformer is connected at the output of the matrix converter to allow wireless power transfer between the matrix converter and the second module.The on-board module uses the secondary side of the high-frequency transformer and a series inductor, Ls, partially formed by the transformer leakage inductance and an additional inductor, The on-board module uses the secondary side of the high-frequency transformer and a series inductor, L s , partially formed by the transformer leakage inductance and an additional inductor, Energies 2017, 10, 1386 3 of 23 together with an H bridge to regulate the output voltage, V o .The H bridge inverts the output voltage with a phase-shifted Pulse Width Modulation (PWM) technique, such that a quasi-square with a ±nV o amplitude is generated on the primary side of the transformer, v prim.In this way, the conventional SVPWM technique is modified to obtain three-level PWM voltage waveforms which are used to control the line currents together with the supply voltage.

Principle of Operation
The control strategy used in the AC-DC converter is based in a SVPWM technique allowing DC output voltage regulation using an index modulation, being easy to implement with a fast response compared to other methods of PWM [17][18][19].The conventional SVPWM technique is modified with a ZVT strategy, in such a way that the semiconductor devices are soft switched.The fundamental of operation of the SVPWM technique with ZVT is described below assuming negligible output voltage ripple and lossless components.Figure 2a-c show the active rectifier switching states, S a , S b and S c , of a conventional SVPWM scheme for one switching period in the first sector, which ranges from 0 • to 60 • , where 1 and 0 indicate on and off states respectively.These switching states are splitted to define the switching states of the H bridge and those of the matrix converter.
Energies 2017, 10, 1386 3 of 24 together with an H bridge to regulate the output voltage, Vo.The H bridge inverts the output voltage with a phase-shifted Pulse Width Modulation (PWM) technique, such that a quasi-square with a ±nVo amplitude is generated on the primary side of the transformer, vprim.In this way, the conventional SVPWM technique is modified to obtain three-level PWM voltage waveforms which are used to control the line currents together with the supply voltage.

Principle of Operation
The control strategy used in the AC-DC converter is based in a SVPWM technique allowing DC output voltage regulation using an index modulation, being easy to implement with a fast response compared to other methods of PWM [17][18][19].The conventional SVPWM technique is modified with a ZVT strategy, in such a way that the semiconductor devices are soft switched.The fundamental of operation of the SVPWM technique with ZVT is described below assuming negligible output voltage ripple and lossless components.Figure 2a-c show the active rectifier switching states, Sa, Sb and Sc, of a conventional SVPWM scheme for one switching period in the first sector, which ranges from 0° to 60°, where 1 and 0 indicate on and off states respectively.These switching states are splitted to define the switching states of the H bridge and those of the matrix converter.The H-bridge switching states S x and S y are presented in Figure 2d,e, with a duty cycle of 50% and a short-circuit period, T SV0H , that generates the voltages v xG (Figure 2f), and v yG (Figure 2g) referred to the G node of the DC rail.The H-bridge voltage (Figure 2h), v xy = v xG − v yG , clamps the secondary side of the transformer to zero Volts when the H bridge is in the short-circuit state.During the first semi cycle, ∆T/2, the voltage in the secondary side of the transformer, v sec , is clamped to V o and the switching states of the matrix converter legs, S am , S bm and S cm (Figure 2i-k) are equal to S a , S b and S c respectively.When S a , S b and S c are equalized in the three inverters legs, a short-circuit occurs; which is caused in the modular version through the H bridge during T SV0H , such that the matrix converter retains the last switching state combination.During the second semi cycle, a mirrored state sequence occurs, since the output voltage in the H bridge becomes v sec = −V o and the switching states in the matrix converter are the complement of S a , S b and S c .The H-bridge short-circuit is caused again and the matrix converter retains the last switching states when S a , S b and S c are equal.In this way, the neutral combination is again caused by the H bridge instead of the matrix converter.
The matrix converter voltages referred to the DC rail node G, v acG , v bcG and v ccG are shown in Figure 2l-n, which are the product of the primary voltage v prim (v prim = nv sec ) and the individual switching state of each leg.When the short-circuit is caused by the H bridge, the matrix converter voltages are clamped to zero Volts.

SVPWM Technique
Six active voltage space vectors, sv 1 to sv 6 , are obtained at the central nodes of the matrix converter shown in Figure 1b by using six switching states combinations, SQ 1 to SQ 6 , which are listed in Table 1, with respect to the states of S am , S bm and S cm .These space vectors are plotted in the bi-dimensional α-β plane of Figure 3 using the Clarke transform [20].sv 1 to sv 6 are generated using the switching states of the matrix converter together with its output voltage ±nV o .A neutral space vector, sv 0 , is produced by using any state combination of the matrix converter together with the H-bridge short-circuit.sv 0 is located at the origin of the α-β plane.The H-bridge switching states Sx and Sy are presented in Figure 2d,e, with a duty cycle of 50% and a short-circuit period, TSV0H, that generates the voltages vxG (Figure 2f), and vyG (Figure 2g) referred to the G node of the DC rail.The H-bridge voltage (Figure 2h), vxy = vxG − vyG, clamps the secondary side of the transformer to zero Volts when the H bridge is in the short-circuit state.During the first semi cycle, ∆T/2, the voltage in the secondary side of the transformer, vsec, is clamped to Vo and the switching states of the matrix converter legs, Sam, Sbm and Scm (Figure 2i-k) are equal to Sa, Sb and Sc respectively.When Sa, Sb and Sc are equalized in the three inverters legs, a short-circuit occurs; which is caused in the modular version through the H bridge during TSV0H, such that the matrix converter retains the last switching state combination.During the second semi cycle, a mirrored state sequence occurs, since the output voltage in the H bridge becomes vsec = −Vo and the switching states in the matrix converter are the complement of Sa, Sb and Sc.The H-bridge short-circuit is caused again and the matrix converter retains the last switching states when Sa, Sb and Sc are equal.In this way, the neutral combination is again caused by the H bridge instead of the matrix converter.
The matrix converter voltages referred to the DC rail node G, vacG, vbcG and vccG are shown in Figure 2l-n, which are the product of the primary voltage vprim (vprim = nvsec) and the individual switching state of each leg.When the short-circuit is caused by the H bridge, the matrix converter voltages are clamped to zero Volts.

SVPWM Technique
Six active voltage space vectors, sv1 to sv6, are obtained at the central nodes of the matrix converter shown in Figure 1b by using six switching states combinations, SQ1 to SQ6, which are listed in Table 1, with respect to the states of Sam, Sbm and Scm.These space vectors are plotted in the bi-dimensional α-β plane of Figure 3 using the Clarke transform [20].sv1 to sv6 are generated using the switching states of the matrix converter together with its output voltage ±nVo.A neutral space vector, sv0, is produced by using any state combination of the matrix converter together with the H-bridge short-circuit.sv0 is located at the origin of the α-β plane.

Switching State Combination Sam, Sbm and Scm
An arbitrary averaged voltage vector, vcav = Vcpk∟θc, can be generated at the converter input using a Volts-seconds balance to control the input line currents together with the supply voltages.Since the matrix converter output voltage reverses its biasing during half of the switching cycle, the Volts-seconds balance utilises the operating sector and its opposite sector of the α-β plane.For example, during the first semi cycle of a switching period in sector S1, vcav is determined by: where Whereas, during the second semi cycle, vcav is defined by: where θ c , can be generated at the converter input using a Volts-seconds balance to control the input line currents together with the supply voltages.Since the matrix converter output voltage reverses its biasing during half of the switching cycle, the Volts-seconds balance utilises the operating sector and its opposite sector of the α-β plane.For example, during the first semi cycle of a switching period in sector S 1 , v cav is determined by: where Whereas, during the second semi cycle, v cav is defined by: where , since v prim = −nV o .
Energies 2017, 10, 1386 5 of 23 The same procedure applies for the rest of the sectors.Table 2 summarizes the switching states according to the sector location of θ c together with the biasing of v prim .
Energies 2017, 10, 1386 5 of 24 The same procedure applies for the rest of the sectors.Table 2 summarizes the switching states according to the sector location of θc together with the biasing of vprim.vxy and vsec are shown in Figure 4a,b respectively for straight comparison to describe the generation of the secondary transformer current, iLS, shown in Figure 4c.During the first semicycle, iLS is assumed positive together with vsec clamped to Vo.The slope of iLs is negative since the converter voltage is greater than the AC supply voltage even when the matrix converter switches from SQ1 to SQ2; whilst during the H-bridge short circuit the matrix switching state SQ2 is retained, such that the slope of iLS is inverted.A current reversal occurs in iLs since vxy is clamped to −Vo and vsec to zero during an overlap period Tovl that is calculated with Equation (3): where Iprimpk is the peak magnitude of the current in the primary side of the transformer, iprim.
In this way, the ZVT is performed in the semiconductor devices during the current reversal to obtain soft commutation.The overlap period finishes when iLS reaches the same magnitude with an opposite sign, such that the first semi cycle becomes to an end.The second semi cycle is a mirror of the first since the complementary switching states of SQ1 and SQ2, SQ4 and SQ5 respectively, are used to operate the matrix converter and because the H bridge has clamped vxy to −Vo.
iLs is equal to niprim, where iprim depends on the switching of the line currents.Table 3 lists the equivalence of iprim respective to the line currents and the matrix switching states.4a,b respectively for straight comparison to describe the generation of the secondary transformer current, i LS , shown in Figure 4c.During the first semicycle, i LS is assumed positive together with v sec clamped to V o .The slope of i Ls is negative since the converter voltage is greater than the AC supply voltage even when the matrix converter switches from SQ 1 to SQ 2 ; whilst during the H-bridge short circuit the matrix switching state SQ 2 is retained, such that the slope of i LS is inverted.A current reversal occurs in i Ls since v xy is clamped to −V o and v sec to zero during an overlap period T ovl that is calculated with Equation (3): where I primpk is the peak magnitude of the current in the primary side of the transformer, i prim .
In this way, the ZVT is performed in the semiconductor devices during the current reversal to obtain soft commutation.The overlap period finishes when i LS reaches the same magnitude with an opposite sign, such that the first semi cycle becomes to an end.The second semi cycle is a mirror of the first since the complementary switching states of SQ 1 and SQ 2 , SQ 4 and SQ 5 respectively, are used to operate the matrix converter and because the H bridge has clamped v xy to −V o .
i Ls is equal to ni prim , where i prim depends on the switching of the line currents.Table 3   Table 3. iLS magnitude for each switching state.

ZVT AC-DC Converter
A block diagram for the AC-DC operation of the circuit of Figure 1b is shown in Figure 5.In this figure θc and the index modulation, Ma, are the inputs required for the SVPWM scheme.Since the converter of Figure 1b is divided into two parts, a sequenced operation is used and described below:

ZVT AC-DC Converter
A block diagram for the AC-DC operation of the circuit of Figure 1b is shown in Figure 5.In this figure θ c and the index modulation, M a , are the inputs required for the SVPWM scheme.Since the converter of Figure 1b is divided into two parts, a sequenced operation is used and described below:

H-Bridge and Matrix Converter Switching States
The derivation of the H-bridge and matrix converter control switching states is described using the block diagram of Figure 6, which are obtained from the switching states of the conventional active rectifier, as described in Section 2.2.Firstly, Sa, Sb and Sc are generated using θc and Ma.The conventional SVPWM active periods, Ta, Tb and Tc, are compared with a high-frequency carrier triangular waveform to produce three digital signals, PWMa, PWMb and PWMc, which are shown in Figure 7.These signals are multiplexed with respect to the sector location to derive the switching states Sa, Sb and Sc, (Figure 7e-g).The H-bridge switching states, Qa, Qc, Qb an Qd, are obtained with a sequential circuit using Sa, Sb and Sc as inputs.

H-Bridge and Matrix Converter Switching States
The derivation of the H-bridge and matrix converter control switching states is described using the block diagram of Figure 6, which are obtained from the switching states of the conventional active rectifier, as described in Section 2.

H-Bridge and Matrix Converter Switching States
The derivation of the H-bridge and matrix converter control switching states is described using the block diagram of Figure 6, which are obtained from the switching states of the conventional active rectifier, as described in Section 2.2.Firstly, Sa, Sb and Sc are generated using θc and Ma.The conventional SVPWM active periods, Ta, Tb and Tc, are compared with a high-frequency carrier triangular waveform to produce three digital signals, PWMa, PWMb and PWMc, which are shown in Figure 7.These signals are multiplexed with respect to the sector location to derive the switching states Sa, Sb and Sc, (Figure 7e-g).The H-bridge switching states, Qa, Qc, Qb an Qd, are obtained with a sequential circuit using Sa, Sb and Sc as inputs.Other set of multiplexers are utilized to derive three digital signals, S a ', S b ' and S c ', that produce the active switching states by using off and on states instead of the short and long pulse trains of PWM a and PWM c respectively, as is shown in Figure 7h-j.S a ', S b ' and S c ' are also multiplexed with respect to the sector location and are processed to derive the switching state of each matrix converter leg.The digital circuit to generate the matrix converter control signals for the first leg, Q 1a , Q 1b , Q 4a and Q 4b , is shown at the right-hand of Figure 6.This circuit commutates the switching states to the opposite side of the α-β plane, sending the complement states when v sec is clamped to negative voltage.The same circuit is used to generate the control signals for the second and third matrix converter legs.

Neutral-to-Active Switching Transition in the Matrix Converter
Since each bi-directional switch in the matrix converter is built with two semiconductor devices with a common collector configuration that allows the current flow in both directions, an overlap in all the matrix converter legs is required to commutate the flowing of current in one direction to the opposite direction during the negative biasing of vsec. Figure 8 shows the switching sequence of Q1a, Q1b and Q4a, Q4b to turn off Q1 and turn on Q4.

Neutral-to-Active Switching Transition in the Matrix Converter
Since each bi-directional switch in the matrix converter is built with two semiconductor devices with a common collector configuration that allows the current flow in both directions, an overlap in all the matrix converter legs is required to commutate the flowing of current in one direction to the opposite direction during the negative biasing of v sec .Figure 8 shows the switching sequence of Q 1a , Q 1b and Q 4a , Q 4b to turn off Q 1 and turn on Q 4 .

Neutral-to-Active Switching Transition in the Matrix Converter
Since each bi-directional switch in the matrix converter is built with two semiconductor devices with a common collector configuration that allows the current flow in both directions, an overlap in all the matrix converter legs is required to commutate the flowing of current in one direction to the opposite direction during the negative biasing of vsec. Figure 8 shows the switching sequence of Q1a, Q1b and Q4a, Q4b to turn off Q1 and turn on Q4.In Figure 8a, Q 1a and Q 1b are conducting the current in the blue or red arrow direction, i Q1 .When Q 1 and Q 4 are commutated to the on and off states respectively, Q 1b is turned off and Q 4b is turned on when the current is flowing in the blue arrow direction; and Q 1a is turned off and Q 4a is turned on when the current is flowing in the red arrow direction (Figure 8b).Finally, when the current flow stops due to the biasing inversion of v sec through the corresponding arrow, the transistors of Q 4 are turned on, (Figure 8c), and, therefore, the current in Q 4 , i Q4 , flows in the opposite direction through the matrix converter leg.
The logic circuit that generates the overlap in the first matrix converter leg is included in the right-hand of Figure 6.This diagram shows the zero crossing detector signals C z1 and C z2 that are used to indicate the end of the overlap.

Active-to-Active Switching Transition in the Matrix Converter
The transition between two active vectors takes place twice in a switching period.In Figure 2a the transition occurs from SQ 1 to SQ 2 during the first semi cycle; whereas in the second semi cycle, the transition occurs from SQ 5 to SQ 4 .The transition between adjacent active vectors implies a switching state change in one matrix converter leg.By instance, the state of the second matrix leg, S bm in Figure 2, switches from the off to the on state producing an active-to-active transition.The turn on-to-off sequence of Q 3 and Q 6 is shown in Figure 9.
Energies 2017, 10, 1386 9 of 24 In Figure 8a, Q1a and Q1b are conducting the current in the blue or red arrow direction, iQ1.When Q1 and Q4 are commutated to the on and off states respectively, Q1b is turned off and Q4b is turned on when the current is flowing in the blue arrow direction; and Q1a is turned off and Q4a is turned on when the current is flowing in the red arrow direction (Figure 8b).Finally, when the current flow stops due to the biasing inversion of vsec through the corresponding arrow, the transistors of Q4 are turned on, (Figure 8c), and, therefore, the current in Q4, iQ4, flows in the opposite direction through the matrix converter leg.
The logic circuit that generates the overlap in the first matrix converter leg is included in the right-hand of Figure 6.This diagram shows the zero crossing detector signals Cz1 and Cz2 that are used to indicate the end of the overlap.

Active-to-Active Switching Transition in the Matrix Converter
The transition between two active vectors takes place twice in a switching period.In Figure 2a the transition occurs from SQ1 to SQ2 during the first semi cycle; whereas in the second semi cycle, the transition occurs from SQ5 to SQ4.The transition between adjacent active vectors implies a switching state change in one matrix converter leg.By instance, the state of the second matrix leg, Sbm in Figure 2, switches from the off to the on state producing an active-to-active transition.The turn on-to-off sequence of Q3 and Q6 is shown in Figure 9.In Figure 9a, Q 6a and Q 6b are firstly turned on and the current flows in the red or blue arrow direction, i Q6 ; then, in Figure 9b Q 6a and Q 3a are turned off and on respectively to allow the current reversal in the matrix converter leg when the current is flowing in the blue arrow direction; or Q 6b and Q 3b are turned off and on respectively to allow the current reversal when the current is flowing in the red arrow direction.In this figure, the transistors of Q 6 are turned on for a period of time t D longer than the turning off time of the semiconductor device, t r , to guarantee that the current stops flowing through it.This bidirectional switch configuration comes to an end when the transistor of Q 6 is turned off as shown in Figure 9c.Lastly, the sequence finishes by turning on transistors of Q 3 , as shown in Figure 9d, with i Q3 flowing in the opposite direction.

Steady-State Analysis and Parameters Selection
A steady-state analysis of the AC-DC modular converter is derived using the generalized diagram of Figure 10, where v s is the three-phase source voltage vector, L is the line inductor, v L is the line inductor voltage vector, v cav is the converter voltage vector, n:1 is the transformer turns ratio that links the off-board AC-AC module with the AC-DC module; V o is the DC output voltage and R is the output load.
Energies 2017, 10, 1386 10 of 24 In Figure 9a, Q6a and Q6b are firstly turned on and the current flows in the red or blue arrow direction, iQ6; then, in Figure 9b Q6a and Q3a are turned off and on respectively to allow the current reversal in the matrix converter leg when the current is flowing in the blue arrow direction; or Q6b and Q3b are turned off and on respectively to allow the current reversal when the current is flowing in the red arrow direction.In this figure, the transistors of Q6 are turned on for a period of time tD longer than the turning off time of the semiconductor device, tr, to guarantee that the current stops flowing through it.This bidirectional switch configuration comes to an end when the transistor of Q6 is turned off as shown in Figure 9c.Lastly, the sequence finishes by turning on transistors of Q3, as shown in Figure 9d, with iQ3 flowing in the opposite direction.

Steady-State Analysis and Parameters Selection
A steady-state analysis of the AC-DC modular converter is derived using the generalized diagram of Figure 10, where vs is the three-phase source voltage vector, L is the line inductor, vL is the line inductor voltage vector, vcav is the converter voltage vector, n:1 is the transformer turns ratio that links the off-board AC-AC module with the AC-DC module; Vo is the DC output voltage and R is the output load.
In Figure 11 the amplitudes of vcav and vL are defined by: Whereas the current iL is obtained with Equation (9): Considering the phasorial diagram of Figure 11, vL is calculated using Equation (10): Equations ( 9) and ( 10) are used to derive the amplitude of iL, ILpk, which is defined by: where ω = 2πf.Assuming ideal conditions, a power balance is derived: The H-bridge switching states Sx and Sy are presented in Figure 2d,e, with a duty cycle of 50% and a short-circuit period, TSV0H, that generates the voltages vxG (Figure 2f), and vyG (Figure 2g) referred to the G node of the DC rail.The H-bridge voltage (Figure 2h), vxy = vxG − vyG, clamps the secondary side of the transformer to zero Volts when the H bridge is in the short-circuit state.During the first semi cycle, ∆T/2, the voltage in the secondary side of the transformer, vsec, is clamped to Vo and the switching states of the matrix converter legs, Sam, Sbm and Scm (Figure 2i-k) are equal to Sa, Sb and Sc respectively.When Sa, Sb and Sc are equalized in the three inverters legs, a short-circuit occurs; which is caused in the modular version through the H bridge during TSV0H, such that the matrix converter retains the last switching state combination.During the second semi cycle, a mirrored state sequence occurs, since the output voltage in the H bridge becomes vsec = −Vo and the switching states in the matrix converter are the complement of Sa, Sb and Sc.The H-bridge short-circuit is caused again and the matrix converter retains the last switching states when Sa, Sb and Sc are equal.In this way, the neutral combination is again caused by the H bridge instead of the matrix converter.
The matrix converter voltages referred to the DC rail node G, vacG, vbcG and vccG are shown in Figure 2l-n, which are the product of the primary voltage vprim (vprim = nvsec) and the individual switching state of each leg.When the short-circuit is caused by the H bridge, the matrix converter voltages are clamped to zero Volts.

SVPWM Technique
Six active voltage space vectors, sv1 to sv6, are obtained at the central nodes of the matrix converter shown in Figure 1b by using six switching states combinations, SQ1 to SQ6, which are listed in Table 1, with respect to the states of Sam, Sbm and Scm.These space vectors are plotted in the bi-dimensional α-β plane of Figure 3 using the Clarke transform [20].sv1 to sv6 are generated using the switching states of the matrix converter together with its output voltage ±nVo.A neutral space vector, sv0, is produced by using any state combination of the matrix converter together with the H-bridge short-circuit.sv0 is located at the origin of the α-β plane.

Switching State Combination Sam, Sbm and Scm
(0, 0, 1) SQ6 (1, 0, 1) An arbitrary averaged voltage vector, vcav = Vcpk∟θc, can be generated at the converter input using a Volts-seconds balance to control the input line currents together with the supply voltages.Since the matrix converter output voltage reverses its biasing during half of the switching cycle, the Volts-seconds balance utilises the operating sector and its opposite sector of the α-β plane.For example, during the first semi cycle of a switching period in sector S1, vcav is determined by: where Whereas, during the second semi cycle, vcav is defined by: where Energies 2017, 10, 1386 4 of 24 The H-bridge switching states Sx and Sy are presented in Figure 2d,e, with a duty cycle of 50% and a short-circuit period, TSV0H, that generates the voltages vxG (Figure 2f), and vyG (Figure 2g) referred to the G node of the DC rail.The H-bridge voltage (Figure 2h The matrix converter voltages referred to the DC rail node G, vacG, vbcG and vccG are shown in Figure 2l-n, which are the product of the primary voltage vprim (vprim = nvsec) and the individual switching state of each leg.When the short-circuit is caused by the H bridge, the matrix converter voltages are clamped to zero Volts.

SVPWM Technique
Six active voltage space vectors, sv1 to sv6, are obtained at the central nodes of the matrix converter shown in Figure 1b by using six switching states combinations, SQ1 to SQ6, which are listed in Table 1, with respect to the states of Sam, Sbm and Scm.These space vectors are plotted in the bi-dimensional α-β plane of Figure 3 using the Clarke transform [20].sv1 to sv6 are generated using the switching states of the matrix converter together with its output voltage ±nVo.
A neutral space vector, sv0, is produced by using any state combination of the matrix converter together with the H-bridge short-circuit.sv0 is located at the origin of the α-β plane.(1, 1, 0) SQ3 (0, 1, 0) SQ4 (0, 1, 1) SQ5 (0, 0, 1) SQ6 (1, 0, 1) An arbitrary averaged voltage vector, vcav = Vcpk∟θc, can be generated at the converter input using a Volts-seconds balance to control the input line currents together with the supply voltages.Since the matrix converter output voltage reverses its biasing during half of the switching cycle, the Volts-seconds balance utilises the operating sector and its opposite sector of the α-β plane.For example, during the first semi cycle of a switching period in sector S1, vcav is determined by: where Whereas, during the second semi cycle, vcav is defined by: where Energies 2017, 10, 1386 4 of 24 The H-bridge switching states Sx and Sy are presented in Figure 2d,e, with a duty cycle of 50% and a short-circuit period, TSV0H, that generates the voltages vxG (Figure 2f), and vyG (Figure 2g) referred to the G node of the DC rail.The H-bridge voltage (Figure 2h), vxy = vxG − vyG, clamps the secondary side of the transformer to zero Volts when the H bridge is in the short-circuit state.During the first semi cycle, ∆T/2, the voltage in the secondary side of the transformer, vsec, is clamped to Vo and the switching states of the matrix converter legs, Sam, Sbm and Scm (Figure 2i-k) are equal to Sa, Sb and Sc respectively.When Sa, Sb and Sc are equalized in the three inverters legs, a short-circuit occurs; which is caused in the modular version through the H bridge during TSV0H, such that the matrix converter retains the last switching state combination.During the second semi cycle, a mirrored state sequence occurs, since the output voltage in the H bridge becomes vsec = −Vo and the switching states in the matrix converter are the complement of Sa, Sb and Sc.The H-bridge short-circuit is caused again and the matrix converter retains the last switching states when Sa, Sb and Sc are equal.In this way, the neutral combination is again caused by the H bridge instead of the matrix converter.
The matrix converter voltages referred to the DC rail node G, vacG, vbcG and vccG are shown in Figure 2l-n, which are the product of the primary voltage vprim (vprim = nvsec) and the individual switching state of each leg.When the short-circuit is caused by the H bridge, the matrix converter voltages are clamped to zero Volts.

SVPWM Technique
Six active voltage space vectors, sv1 to sv6, are obtained at the central nodes of the matrix converter shown in Figure 1b by using six switching states combinations, SQ1 to SQ6, which are listed in Table 1, with respect to the states of Sam, Sbm and Scm.These space vectors are plotted in the bi-dimensional α-β plane of Figure 3 using the Clarke transform [20].sv1 to sv6 are generated using the switching states of the matrix converter together with its output voltage ±nVo.
A neutral space vector, sv0, is produced by using any state combination of the matrix converter together with the H-bridge short-circuit.sv0 is located at the origin of the α-β plane.

SQ6
(1, 0, 1) An arbitrary averaged voltage vector, vcav = Vcpk∟θc, can be generated at the converter input using a Volts-seconds balance to control the input line currents together with the supply voltages.Since the matrix converter output voltage reverses its biasing during half of the switching cycle, the Volts-seconds balance utilises the operating sector and its opposite sector of the α-β plane.For example, during the first semi cycle of a switching period in sector S1, vcav is determined by: where Whereas, during the second semi cycle, vcav is defined by: where In Figure 11 the amplitudes of v cav and v L are defined by: Whereas the current i L is obtained with Equation ( 9): Considering the phasorial diagram of Figure 11, v L is calculated using Equation (10): Equations ( 9) and ( 10) are used to derive the amplitude of i L , I Lpk , which is defined by: Energies 2017, 10, 1386 where ω = 2πf.Assuming ideal conditions, a power balance is derived: where P in and P out are the input and output power converter respectively and are equivalent to Equation ( 13): Substituting Equation ( 11) in ( 13), the power balance becomes: According to Figure 11, the AC-DC converter can operate under two extreme conditions; a minimum supply voltage, V spkmin , obtaining a maximum phase, ϕ max , with a maximum power demand at the output, P omax ; and a maximum supply voltage, V spkmax obtaining a minimum phase, ϕ min , with a minimum power demand at the output, P omin .Therefore, ϕ max and ϕ min are obtained using Equations ( 15) and ( 16) respectively: Considering P omax = 5 kW, P omin = 500 W, V spkmin = 144 V and V spkmax = 216 V, ϕ max and ϕ min are obtained for different values of L. Figure 12 is used to select the optimal L that allows an appropriate range of phase control.L was judged to be 3 mH, in such a way that ϕ can be ranged from 0.46 • to 10.3 where Pin and Pout are the input and output power converter respectively and are equivalent to Equation ( 13): Substituting Equation ( 11) in ( 13), the power balance becomes: According to Figure 11, the AC-DC converter can operate under two extreme conditions; a minimum supply voltage, Vspkmin, obtaining a maximum phase, φmax, with a maximum power demand at the output, Pomax; and a maximum supply voltage, Vspkmax obtaining a minimum phase, φmin, with a minimum power demand at the output, Pomin.Therefore, φmax and φmin are obtained using Equations ( 15) and ( 16) respectively:   12 is used to select the optimal L that allows an appropriate range of phase control.L was judged to be 3 mH, in such a way that φ can be ranged from 0.46° to 10.3°.The voltage Vcpk is expressed in function of the modulation index, Ma, when the converter operates with a SVPWM scheme [14], as follows: where Pin and Pout are the input and output power converter respectively and are equivalent to Equation ( 13): Substituting Equation ( 11) in ( 13), the power balance becomes: According to Figure 11, the AC-DC converter can operate under two extreme conditions; a minimum supply voltage, Vspkmin, obtaining a maximum phase, φmax, with a maximum power demand at the output, Pomax; and a maximum supply voltage, Vspkmax obtaining a minimum phase, φmin, with a minimum power demand at the output, Pomin.Therefore, φmax and φmin are obtained using Equations ( 15) and ( 16) respectively:   12 is used to select the optimal L that allows an appropriate range of phase control.L was judged to be 3 mH, in such a way that φ can be ranged from 0.46° to 10.3°.The voltage Vcpk is expressed in function of the modulation index, Ma, when the converter operates with a SVPWM scheme [14], as follows: The voltage V cpk is expressed in function of the modulation index, M a , when the converter operates with a SVPWM scheme [14], as follows: The minimum and maximum converter voltages, V cpkmin and V cpkmax , are utilized to obtain the minimum and maximum modulation indexes, M amin and M amax respectively, which are shown in (18) and ( 19): where V cpkmin = 144.004Volts and V cpkmax = 219.53Volts were calculated using Equation ( 7) for V spkmin and V spkmax respectively.An optimal value for n was determined by using Equations ( 18) and ( 19) and ranging n from 2 to 10, such that the results are plotted in Figure 13.n was selected to be 5 since M a can be set between 0.66 and 1 to control the amplitude of the converter input voltage.It was judged in this work that n should be 5 to allow the converter an appropriate SVPWM operation and leave a small upper range of M a for the ZVT effects since the maximum value of M a is 1.16 for SVPWM [20].
Energies 2017, 10, 1386 12 of 24 The minimum and maximum converter voltages, Vcpkmin and Vcpkmax, are utilized to obtain the minimum and maximum modulation indexes, Mamin and Mamax respectively, which are shown in (18) and ( 19): where Vcpkmin = 144.004Volts and Vcpkmax = 219.53Volts were calculated using Equation ( 7) for Vspkmin and Vspkmax respectively.An optimal value for n was determined by using Equations ( 18) and ( 19) and ranging n from 2 to 10, such that the results are plotted in Figure 13.n was selected to be 5 since Ma can be set between 0.66 and 1 to control the amplitude of the converter input voltage.It was judged in this work that n should be 5 to allow the converter an appropriate SVPWM operation and leave a small upper range of Ma for the ZVT effects since the maximum value of Ma is 1.16 for SVPWM [20].Equations ( 14) and (17) show that there is a compromise between the selection of the parameters n, φ and L to reach a wide range of Ma within the conventional active rectifier operation range.

Numerical Verification
To verify the principle of operation of the modular AC-DC converter and the SVPWM with ZVT control strategy, a simulation in Saber was performed using ideal components and the parameters listed in Table 4.  Equations ( 14) and (17) show that there is a compromise between the selection of the parameters n, ϕ and L to reach a wide range of M a within the conventional active rectifier operation range.

Numerical Verification
To verify the principle of operation of the modular AC-DC converter and the SVPWM with ZVT control strategy, a simulation in Saber was performed using ideal components and the parameters listed in Table 4.

Verification of the Modified SVPWM
A Saber simulation was performed synchronizing the operation of the divided rectifier control signals with the fundamental frequency of the supply, using the scheme of Figure 14.I Lpk is the current reference used to define θ c and M a for the SVPWM operation of the rectifier and cause high power factor as shown in Figure 11.The converter voltage was phase shifted to align the line currents with the supply using the vectorial control system of Figure 14.A reference current of I Lpk = 19.54A was used to obtain a 100 V, 5 kW output with high power factor supply.The component of V cav in the q axis, V cavq , was determined using Equation ( 7) and the phasorial diagram of Figure 11, V cavq = 22.1 V, such that V cavd = V spk = 180 V, therefore, the phase between v s and v cav was ϕ = 7

Verification of the Modified SVPWM
A Saber simulation was performed synchronizing the operation of the divided rectifier control signals with the fundamental frequency of the supply, using the scheme of Figure 14.ILpk is the current reference used to define θc and Ma for the SVPWM operation of the rectifier and cause high power factor as shown in Figure 11.The converter voltage was phase shifted to align the line currents with the supply using the vectorial control system of Figure 14.A reference current of ILpk = 19.54A was used to obtain a 100 V, 5 kW output with high power factor supply.The component of Vcav in the q axis, Vcavq, was determined using Equation ( 7) and the phasorial diagram of Figure 11, Vcavq = 22.1 V, such that Vcavd = Vspk = 180 V, therefore, the phase between vs and vcav was φ = 7°.To confirm the correct operation of the scheme shown in Figure 14, Figure 15 shows a Saber result plot of the supply and converter phases, θS and θC, for current references of 9.4 A and 19.54A and cause 2.5 kW and 5 kW respectively.In Figure 15a a phase shift of 3° is obtained, whereas in Figure 15b the phase shift becomes of 7° since the current reference was increased.The effectiveness of the SVPWM rectifier operation of the circuit of Figure 1b was verified analyzing the Saber simulation results of the line currents and input voltages of the converter.Figure 16a shows Saber results of the source voltage vaN and the line current ia.The resultant line current ia is sinusoidal with a 3.3% ripple.Figure 16b shows the five-level converter voltage, vacN, to verify the correct operation of the space vector strategy.The current and voltage in the primary side of the transformer, iprim and vprim are shown in Figure 16c, where iprim is the rectified version of the line currents, but, inverted in one quadrant of the switching cycle producing a high-frequency AC square current.To confirm the correct operation of the scheme shown in Figure 14, Figure 15 shows a Saber result plot of the supply and converter phases, θ S and θ C , for current references of 9.4 A and 19.54A and cause 2.5 kW and 5 kW respectively.In Figure 15a a phase shift of 3 • is obtained, whereas in Figure 15b the phase shift becomes of 7 • since the current reference was increased.The effectiveness of the SVPWM rectifier operation of the circuit of Figure 1b was verified analyzing the Saber simulation results of the line currents and input voltages of the converter.Figure 16a shows Saber results of the source voltage v aN and the line current i a .The resultant line current i a is sinusoidal with a 3.3% ripple.Figure 16b shows the five-level converter voltage, v acN , to verify the correct operation of the space vector strategy.The current and voltage in the primary side of the transformer, i prim and v prim are shown in Figure 16c, where i prim is the rectified version of the line currents, but, inverted in one quadrant of the switching cycle producing a high-frequency AC square current.
The operation of the H bridge was verified contrasting the conventional SVPWM states with the phase-shifted control signals of the H bridge. Figure 17 plots the Saber results of S a, S b and S c (Figure 17a-c, respectively) in contrast to S x and S y (Figure 17d,e).The H-bridge input voltages v xG and v yG are shown in Figure 17f,g, respectively, and its difference v xy is shown in Figure 17h.In the latter figure, v xy is a ±V o quasi-square waveform, whose zero level is effectively produced by the H-bridge overlap, which can be used to produce the neutral vectors required by the conventional rectifier states in a switching cycle.
simulation results of the line currents and input voltages of the converter.Figure 16a shows Saber results of the source voltage vaN and the line current ia.The resultant line current ia is sinusoidal with a 3.3% ripple.Figure 16b shows the five-level converter voltage, vacN, to verify the correct operation of the space vector strategy.The current and voltage in the primary side of the transformer, iprim and vprim are shown in Figure 16c, where iprim is the rectified version of the line currents, but, inverted in one quadrant of the switching cycle producing a high-frequency AC square current.The operation of the H bridge was verified contrasting the conventional SVPWM states with the phase-shifted control signals of the H bridge. Figure 17 plots the Saber results of Sa, Sb and Sc (Figure 17a-c, respectively) in contrast to Sx and Sy (Figure 17d,e).The H-bridge input voltages vxG and vyG are shown in Figure 17f,g, respectively, and its difference vxy is shown in Figure 17h.In the latter figure, vxy is a ±Vo quasi-square waveform, whose zero level is effectively produced by the H-bridge overlap, which can be used to produce the neutral vectors required by the conventional rectifier

ZVT Verification
The effects of the ZVT in the transistors of the matrix converter were initially verified analyzing the quasi-square voltages vxy and vsec together with the transformer secondary current, isec = iLs, as shown in Figure 19 for direct comparison with Figure 4.In Figure 19a,b, during the first semi cycle, vxy and vsec are clamped to Vo such that iLs (Figure 19c) has a smooth negative slope; however, this slope becomes positive when the H bridge is in its overlap state to produce a neutral voltage vector at the converter AC input.A expanded portion of the first semi cycle of iLs is shown in Figure 19d.

ZVT Verification
The effects of the ZVT in the transistors of the matrix converter were initially verified analyzing the quasi-square voltages vxy and vsec together with the transformer secondary current, isec = iLs, as shown in Figure 19 for direct comparison with Figure 4.In Figure 19a,b, during the first semi cycle,

ZVT Verification
The effects of the ZVT in the transistors of the matrix converter were initially verified analyzing the quasi-square voltages v xy and v sec together with the transformer secondary current, i sec = i Ls , as shown in Figure 19 for direct comparison with Figure 4.In Figure 19a,b, during the first semi cycle, v xy and v sec are clamped to V o such that i Ls (Figure 19c) has a smooth negative slope; however, this slope becomes positive when the H bridge is in its overlap state to produce a neutral voltage vector at the converter AC input.A expanded portion of the first semi cycle of i Ls is shown in Figure 19d.At the beginning of the second semicycle, iLs is reversed in an overlap period of TovL = 3 µs, as shown in the expanded portion of Figure 19e, which was confirmed using Equation (3), since vxy and vsec are now clamped to −Vo and zero respectively; whereas the rest of the second semicycle iLs becomes a mirrored wave of the first, which is shown in the expanded portion of Figure 19f.iLs is an AC trapezoidal waveform that is shaped by the switched operation of the H bridge and the matrix converter, which needs to be controlled to ensure stability and prevent saturation by the aid of a DC blocking capacitor, or a peak current control [21], since a high-frequency transformer is used in the proposed converter.
A zero-voltage switching transition is achieved in the matrix converter legs due to the zero-voltage biasing of its bidirectional switches whilst iLs is being reversed.This was verified analyzing the voltage and current waveforms in the first matrix leg switches Q1 and Q4 when an iLS reversal occurs.Figure 20 depicts the simulated switching transition result described in Figure 8 to turn on Q4 and turn off Q1.Initially in Figure 20, the switches of Q1, Q1a and Q1b, and those of Q4, Q4a and Q4b, are in the on and off states respectively.Later in Figure 20a, Q1a and Q4a have an overlap period that cause to the voltage of Q4, vQ4, decrease to zero, and then iQ4 increases as shown in Figure At the beginning of the second semicycle, i Ls is reversed in an overlap period of T ovL = 3 µs, as shown in the expanded portion of Figure 19e, which was confirmed using Equation (3), since v xy and v sec are now clamped to −V o and zero respectively; whereas the rest of the second semicycle i Ls becomes a mirrored wave of the first, which is shown in the expanded portion of Figure 19f.i Ls is an AC trapezoidal waveform that is shaped by the switched operation of the H bridge and the matrix converter, which needs to be controlled to ensure stability and prevent saturation by the aid of a DC blocking capacitor, or a peak current control [21], since a high-frequency transformer is used in the proposed converter.
A zero-voltage switching transition is achieved in the matrix converter legs due to the zero-voltage biasing of its bidirectional switches whilst i Ls is being reversed.This was verified analyzing the voltage and current waveforms in the first matrix leg switches Q 1 and Q 4 when an i LS reversal occurs.Figure 20 depicts the simulated switching transition result described in Figure 8 to turn on Q 4 and turn off Q 1 .Initially in Figure 20, the switches of Q 1 , Q 1a and Q 1b , and those of Q 4 , Q 4a and Q 4b , are in the on and off states respectively.Later in Figure 20a, Q 1a and Q 4a have an overlap period that cause to the voltage of Q 4 , v Q4 , decrease to zero, and then i Q4 increases as shown in Figure 20b, achieving a ZVT turn on in Q 4 during the current reversal.Whereas i Q4 increases, i Q1 falls to set Q 1 to the off state, as shown in Figure 20c, which depicts a hard switch off transition.During the overlap, v sec is clamped to zero and then biased to −V o at the end of the overlap, whilst the current reversal in i Ls occurs (Figure 20d).

Steady-State Power Balance Verification
To verify the input-to-output active power balance, the DC output power was calculated by the aid of the H-bridge output current i rect .The current i Ls and i rect are shown in Figure 22a,b, respectively.In these figures i Ls is seen to be rectified by the H bridge since i rect may become either ±i Ls , during the ±V o clamping of v xy respectively or zero when the H bridge is in its short-circuit state.The average or i rect , I rect , was calculated using the simulation results shown in Figure 22, and it was found that I rect = 50 A and, therefore, the output power is 5 kW, since the Saber simulation was performed assuming a constant DC output voltage of V o = 100 Volts.In this fashion, the output power equalizes the active supply power, demonstrating the principle of operation of the AC-DC divided converter of Figure 1b.

Steady-State Power Balance Verification
To verify the input-to-output active power balance, the DC output power was calculated by the aid of the H-bridge output current irect.The current iLs and irect are shown in Figure 22a,b, respectively.In these figures iLs is seen to be rectified by the H bridge since irect may become either ±iLs, during the ±Vo clamping of vxy respectively or zero when the H bridge is in its short-circuit state.The average or irect, Irect, was calculated using the simulation results shown in Figure 22, and it was found that Irect = 50 A and, therefore, the output power is 5 kW, since the Saber simulation was performed assuming a constant DC output voltage of Vo = 100 Volts.In this fashion, the output power equalizes the active supply power, demonstrating the principle of operation of the AC-DC divided converter of Figure 1b.To verify the high-quality supply currents the harmonic content in the line current ia was calculated, as shown in Figure 23; the measured current THD was 4.43%, being the power rated at 5 kW.Two main current harmonic clusters were found at the harmonic order of n = 242 and n = 488, corresponding to the frequencies of 14.5 kHz and 29.28 kHz, which were increased in amplitude since four switching transitions take place between space vector combinations during a switching period.To verify the high-quality supply currents the harmonic content in the line current i a was calculated, as shown in Figure 23; the measured current THD was 4.43%, being the power rated at 5 kW.Two main current harmonic clusters were found at the harmonic order of n = 242 and n = 488, corresponding to the frequencies of 14.5 kHz and 29.28 kHz, which were increased in amplitude since four switching transitions take place between space vector combinations during a switching period.To verify the high-quality supply currents the harmonic content in the line current ia was calculated, as shown in Figure 23; the measured current THD was 4.43%, being the power rated at 5 kW.Two main current harmonic clusters were found at the harmonic order of n = 242 and n = 488, corresponding to the frequencies of 14.5 kHz and 29.28 kHz, which were increased in amplitude since four switching transitions take place between space vector combinations during a switching period.The low order harmonic content of the input current was compared with the Standard EN61000-3-2 [22], for the limits of Class A converters. Figure 24 shows that the components are within the standard limits; for example, for n = 3, the amplitude is 0.39 A, 2% of the fundamental, that is less than limit, 2.3 A. The low order harmonic content of the input current was compared with the Standard EN61000-3-2 [22], for the limits of Class A converters. Figure 24 shows that the components are within the standard limits; for example, for n = 3, the amplitude is 0.39 A, 2% of the fundamental, that is less than limit, 2.3 A.

Comparison of the Proposed Converter with Other AC-DC Topologies
Table 5 presents a detailed comparison of the proposed topology with four other AC-DC converters of different levels.The first row of this table is referred to the charging power levels for EVs, which are currently three according to the International Electrotechnical Commission standard IEC61851 [23].Level 1 is for small on-board battery chargers with typical use in home or office; Level 2 is for medium power battery chargers that can be used in private or public outlets, and Level 3 is generally designed for a recharging station for commercial and public transportation.The proposed topology is intended for Level 3 applications, which justifies the use of a three-phase voltage supply.
Table 5 shows that the number of switching devices used in the proposed converter is slightly higher in contrast to the topologies described in [14][15][16]; however, only four of them are located on-board the vehicle.The use of the bidirectional switches in the matrix converter allows the possibility power flow reversal through the converter, being more suitable to future smart grids.The implementation of the proposed AC-DC modular converter is considering the use of high-frequency, nanocrystal magnetic materials for the transformer core.In this fashion, higher

Comparison of the Proposed Converter with Other AC-DC Topologies
Table 5 presents a detailed comparison of the proposed topology with four other AC-DC converters of different levels.The first row of this table is referred to the charging power levels for EVs, which are currently three according to the International Electrotechnical Commission standard IEC61851 [23].Level 1 is for small on-board battery chargers with typical use in home or office; Level 2 is for medium power battery chargers that can be used in private or public outlets, and Level 3 is generally designed for a recharging station for commercial and public transportation.The proposed topology is intended for Level 3 applications, which justifies the use of a three-phase voltage supply.Table 5 shows that the number of switching devices used in the proposed converter is slightly higher in contrast to the topologies described in [14][15][16]; however, only four of them are located on-board the vehicle.The use of the bidirectional switches in the matrix converter allows the possibility power flow reversal through the converter, being more suitable to future smart grids.The implementation of the proposed AC-DC modular converter is considering the use of high-frequency, nanocrystal magnetic materials for the transformer core.In this fashion, higher power capability may be obtained with distributed gapped cores, such as the used in [15], increasing the efficiency limit by the actual wireless coupling techniques used in actual AC-DC chargers for wireless electric vehicles [22].

Conclusions
The splitting of a conventional active rectifier into a matrix converter and an H bridge linked through a high-frequency transformer resulted in an AC-DC modular converter topology ideal for high power density applications.The converter portion on board makes the topology particularly attractive for PEV's; nevertheless, the technique is suitable for other applications.A SVPWM technique with ZVT was proposed for the described converter which allows symmetric generation of virtually square current waves that are attractive for high-frequency wireless transmission of high power.
The topology was verified using a numerical prediction performed in Saber which resulted in high-quality supply currents with a current THD of 4.43%.An input-to-output power balance was verified ensuring reliable power transmission.The high-frequency switching of 7.2 kHz allowed ZVT of the semiconductor devices, since a short overlap period was caused by a simple sequential logic circuitry which aids to the reduction of the switching power losses of typical SVPWM schemes; nevertheless, semiconductor current monitoring is required to obtain correct switching behavior of the matrix converter.
Future aims of research of this topology consider its practical development at higher switching frequencies, allowing further reduction of size and weight, possibility of wireless power transmission, which would be particularly attractive for reliable and risk free charging of electric vehicles.Furthermore, the application of the proposed topology could be examined for other power electronic topologies.

Figure 1 .
Figure 1.(a) Conventional active rectifier; (b) Circuit diagram of the proposed modular AC-DC converter.

Figure 1 .
Figure 1.(a) Conventional active rectifier; (b) Circuit diagram of the proposed modular AC-DC converter.

Figure 2 .
Figure 2. Derivation of the transistor switching states of the modular active rectifier of Figure 1b together with their voltage converter waveforms: (a) switching state S a ; (b) switching state S b ; (c) switching state S c ; (d) switching state S x ; (e) switching state S y ; (f) voltage v xG ; (g) voltage v yG ; (h) voltage v sec ; (i) switching state S am ; (j) switching state S bm ; (k) switching state S cm ; (l) voltage v acG ; (m) voltage v bcG ; (n) voltage v ccG .
(a) The conventional active rectifier switching states are generated using Ma and θc.These are equivalent to the control signals of Figure 2a-c.(b) Sam, Sbm and Scm, shown in Figure 2i-k, are generated and multiplexed to assign the control signals for each bi-direccional switch.(c) Sx and Sy, shown in Figure 2d,e, are generated from the active periods of the conventional active rectifier.(d) An overlap is required to turn on and off the bidirectional switches during the reversal of current iLS.
(a) The conventional active rectifier switching states are generated using M a and θ c .These are equivalent to the control signals of Figure 2a-c.(b) S am , S bm and S cm , shown in Figure 2i-k, are generated and multiplexed to assign the control signals for each bi-direccional switch.(c) S x and S y , shown in Figure 2d,e, are generated from the active periods of the conventional active rectifier.(d) An overlap is required to turn on and off the bidirectional switches during the reversal of current i LS .

Figure 5 .
Figure 5. Block diagram for AC-DC operation of the modular converter of Figure 1b.

Figure 6 .
Figure 6.Block diagram to generate the switching states for the matrix converter and the H bridge.Other set of multiplexers are utilized to derive three digital signals, Sa', Sb' and Sc', that produce the active switching states by using off and on states instead of the short and long pulse trains of PWMa and PWMc respectively, as is shown in Figure7h-j.Sa', Sb' and Sc' are also multiplexed with respect to the sector location and are processed to derive the switching state of each matrix converter leg.The digital circuit to generate the matrix converter control signals for the first leg, Q1a, Q1b, Q4a and Q4b, is shown at the right-hand of Figure6.This circuit commutates the switching states to the opposite side of the α-β plane, sending the complement states when vsec is clamped to negative voltage.The same circuit is used to generate the control signals for the second and third matrix converter legs.

Figure 5 .
Figure 5. Block diagram for AC-DC operation of the modular converter of Figure 1b.

24 Figure 5 .
Figure 5. Block diagram for AC-DC operation of the modular converter of Figure 1b.

Figure 6 .
Figure 6.Block diagram to generate the switching states for the matrix converter and the H bridge.

Figure 6 .
Figure 6.Block diagram to generate the switching states for the matrix converter and the H bridge.

Figure 8 .
Figure 8. Switching sequence in the on-to-off transition from neutral-to-active switching state.(a) initial current flow; (b) overlap time; (c) current flow in the opposite direction.

Figure 7 .
Figure 7. Generation of PWM signals, and conventional active rectifier switching states.(a) High-frequncy triangular carrier signal; (b) digital signal PWM a ; (c) digital signal PWM b ; (d) digital signal PWM c ; (e) switching state S a ; (f) switching state S b ; (g) switching state S c ; (h) digital signal S' a ; (i) digital signal S' b ; (j) digital signal S' c .

Figure 8 .
Figure 8. Switching sequence in the on-to-off transition from neutral-to-active switching state.(a) initial current flow; (b) overlap time; (c) current flow in the opposite direction.

Figure 8 .
Figure 8. Switching sequence in the on-to-off transition from neutral-to-active switching state.(a) initial current flow; (b) overlap time; (c) current flow in the opposite direction.

Figure 9 .
Figure 9. Switching sequence in the on-to-off transition from active-to-active switching state.(a) initial current flow; (b) overlap time; (c) current flow in the opposite direction; (d) bidirectional switch in on state.

Figure 9 .
Figure 9. Switching sequence in the on-to-off transition from active-to-active switching state.(a) initial current flow; (b) overlap time; (c) current flow in the opposite direction; (d) bidirectional switch in on state.

Figure 10 .
Figure 10.Generalized diagram for steady-state analysis

Figure 10 .
Figure 10.Generalized diagram for steady-state analysis ), vxy = vxG − vyG, clamps the secondary side of the transformer to zero Volts when the H bridge is in the short-circuit state.During the first semi cycle, ∆T/2, the voltage in the secondary side of the transformer, vsec, is clamped to Vo and the switching states of the matrix converter legs, Sam, Sbm and Scm (Figure 2i-k) are equal to Sa, Sb and Sc respectively.When Sa, Sb and Sc are equalized in the three inverters legs, a short-circuit occurs; which is caused in the modular version through the H bridge during TSV0H, such that the matrix converter retains the last switching state combination.During the second semi cycle, a mirrored state sequence occurs, since the output voltage in the H bridge becomes vsec = −Vo and the switching states in the matrix converter are the complement of Sa, Sb and Sc.The H-bridge short-circuit is caused again and the matrix converter retains the last switching states when Sa, Sb and Sc are equal.In this way, the neutral combination is again caused by the H bridge instead of the matrix converter.

Figure 11 .
Figure 11.Phasorial diagram for the AC-DC converter operation.

Figure 12 .
Figure 12. φmin and φmax obtained for different values of L.

Figure 11 .
Figure 11.Phasorial diagram for the AC-DC converter operation.

Figure 11 .
Figure 11.Phasorial diagram for the AC-DC converter operation.

Figure 12 .
Figure 12. φmin and φmax obtained for different values of L.

Figure 12 .
Figure 12. ϕ min and ϕ max obtained for different values of L.

Figure 13 .
Figure 13.M amin and M amax obtained for different n.

Figure 14 .
Figure 14.General scheme used in simulation.

Figure 14 .
Figure 14.General scheme used in simulation.

Figure 16 .
Figure 16.Simulation results (a) Supply voltage v aN and line current i a ; (b) converter voltage in phase a; and (c) High-frequency current and voltage in the primary side of the transformer.Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

Figure 17 . 24 Figure 17 .
Figure 17.Simulations results: conventional switching states (a) S a , (b) S b and (c) S c ; H-bridge switching states (d) S x and (e) S y and voltages (f) v xG (g) v yG and (h) v xy .Supply: 127 V, 60 Hz, Output: 100 V, 5 kW.

Figure
Figure 21a shows the simulated results of the opposite switching transition to turn on Q1 and turn off Q4. Mirrored waveforms are obtained for iQ1, iQ4, vQ1 and vQ4 in contrast to Figure 20.The ZVT is shown in Figure 21b when iQ1 becomes positive during the zero voltage in Q1. vsec is clamped to +Vo whilst iLs is reversed.

Figure
Figure21ashows the simulated results of the opposite switching transition to turn on Q 1 and turn off Q 4 .Mirrored waveforms are obtained for i Q1 , i Q4 , v Q1 and v Q4 in contrast to Figure20.The ZVT is shown in Figure21bwhen i Q1 becomes positive during the zero voltage in Q 1 .v sec is clamped to +V o whilst i Ls is reversed.

Figure
Figure21ashows the simulated results of the opposite switching transition to turn on Q1 and turn off Q4. Mirrored waveforms are obtained for iQ1, iQ4, vQ1 and vQ4 in contrast to Figure20.The ZVT is shown in Figure21bwhen iQ1 becomes positive during the zero voltage in Q1. vsec is clamped to +Vo whilst iLs is reversed.

Figure 23 .
Figure 23.Harmonic content for line current ia.Figure 23.Harmonic content for line current i a .

Figure 23 .
Figure 23.Harmonic content for line current ia.Figure 23.Harmonic content for line current i a .

Figure 24 .
Figure 24.Low Harmonic content for line current ia for comparison with Standard EN 61000-3-2.

Figure 24 .
Figure 24.Low Harmonic content for line current i a for comparison with Standard EN 61000-3-2.

Table 1 .
Switching states vectors of matrix converter.

Table 1 .
Switching states vectors of matrix converter.

Table 1 .
Switching states vectors of matrix converter.

Table 1 .
Switching states vectors of matrix converter.

Table 1 .
Switching states vectors of matrix converter.