A Switching Frequency Optimized Space Vector Pulse Width Modulation ( SVPWM ) Scheme for Cascaded Multilevel Inverters

This paper presents a novel switching frequency optimized space vector pulse width modulation (SVPWM) scheme for cascaded multilevel inverters. The proposed SVPWM is developed in a α′β′ coordinate system, in which the voltage vectors have only integer entries and the absolute increment of coordinate values between adjacent vectors is equal to dc-bus voltage of power cells (1 pu). The new SVPWM scheme is built with three categories of switching paths. During each switching path, the change of one phase voltage is limited in 1 pu. This contributes to decrease the number of commutations of switches. The proposed SVPWM scheme is validated on a 7-level cascaded inverter and the results show that it significantly outperforms traditional SVPWM schemes in terms of decreasing the number of switch commutations.

(2) Calculate the duty cycles for the three space vectors.
(3) Generate the switching sequences with specific constraint.
Because the space vector diagram of multilevel inverters is comprised of equilateral triangles in traditional αβ coordinate system, the location of reference voltage vector and the duty cycles of the three nearest vectors are obtained with extensive computation.Consequently, the implementation of Energies 2017, 10, 725 2 of 18 SVPWM schemes in αβ coordinate system usually becomes more complex as the number of levels increases.To speed up Step 1 and Step 2, various coordinate systems have been developed [18][19][20][21].
The determination of redundancies with specific constraint in Step 3 remains a big challenge for SVPWM schemes.In order to decrease the number of commutations of switches, some switching techniques have been developed in [22,23].By carefully selecting redundant switching positions in upper type triangle, lower type triangle and the section number, a minimum loss SVPWM scheme was proposed in [22].However, as the number of level increases, the selecting complexity of the redundancies increases and no generalized technique for redundancies and switching state transitions is developed.Based on two mappings, a SVPWM scheme is proposed in [23].Because the different "modes" need to be determined and the region number of the modulation triangle should be calculated in the SVPWM scheme, the rule of determining the switching sequences is still challenging so far.
In this paper, a novel switching frequency optimized SVPWM scheme is proposed and the main contributions are summarized below: (1) the proposed SVPWM scheme is developed in a α β coordinate system; (2) The change of one phase voltage is limited in 1 pu during each switching path; (3) The experimental results show that the proposed method significantly outperforms the traditional SVPWM schemes in terms of decreasing the number of commutations of switches.
The paper is organized as follows: Section 2 describes the concepts of basic switching mode and switching path.Section 3 presents the principle of the SVPWM scheme.The experimental results and comparative analysis are presented to validate the theoretical analysis in Section 4. Finally, the conclusions are presented in Section 5.

α β Coordinate System
A α β coordinate system is our developed coordinate system in [24].In the α β coordinate system, voltage vectors have integer entries and the absolute coordinate increment between adjacent vectors is equal to 1.The transformation matrix among the α β coordinate system, the traditional αβ coordinate system [1] and abc coordinate system are written in Equation (1): where, a, b and c are the normalized three phase voltages of multilevel inverters.[α β] T and [α β ] T are the coordinate values of [a b c] T in the traditional αβ coordinate system and the α β coordinate system, respectively.The projections of vectors for 3-level inverter in the αβ and α β coordinate system are shown in Figure 1, where, each vector is represented by one dot.
Energies 2017, 10, 725 2 of 18 The determination of redundancies with specific constraint in Step 3 remains a big challenge for SVPWM schemes.In order to decrease the number of commutations of switches, some switching techniques have been developed in [22,23].By carefully selecting redundant switching positions in upper type triangle, lower type triangle and the section number, a minimum loss SVPWM scheme was proposed in [22].However, as the number of level increases, the selecting complexity of the redundancies increases and no generalized technique for redundancies and switching state transitions is developed.Based on two mappings, a SVPWM scheme is proposed in [23].Because the different "modes" need to be determined and the region number of the modulation triangle should be calculated in the SVPWM scheme, the rule of determining the switching sequences is still challenging so far.
In this paper, a novel switching frequency optimized SVPWM scheme is proposed and the main contributions are summarized below: (1) the proposed SVPWM scheme is developed in a α′β′ coordinate system; (2) The change of one phase voltage is limited in 1 pu during each switching path; (3) The experimental results show that the proposed method significantly outperforms the traditional SVPWM schemes in terms of decreasing the number of commutations of switches.
The paper is organized as follows: Section 2 describes the concepts of basic switching mode and switching path.Section 3 presents the principle of the SVPWM scheme.The experimental results and comparative analysis are presented to validate the theoretical analysis in Section 4. Finally, the conclusions are presented in Section 5.

α′β′ Coordinate System
A α′β′ coordinate system is our developed coordinate system in [24].In the α′β′ coordinate system, voltage vectors have integer entries and the absolute coordinate increment between adjacent vectors is equal to 1.The transformation matrix among the α′β′ coordinate system, the traditional αβ coordinate system [1] and abc coordinate system are written in Equation (1): where, a, b and c are the normalized three phase voltages of multilevel inverters.[α β] T and [α′ β′] T are the coordinate values of [a b c] T in the traditional αβ coordinate system and the α′β′ coordinate system, respectively.The projections of vectors for 3-level inverter in the αβ and α′β′ coordinate system are shown in Figure 1, where, each vector is represented by one dot.Energies 2017, 10, 725 3 of 18

Three Basic Switching Modes
The basic switching mode and switching path are defined as follows: (1) Basic switching mode: the value of a, b or c is changed with 1 pu between two adjacent switching states.There are three kinds of basic switching modes in space vector diagram, and the three kinds of basic switching modes is named as diagonal switching mode, vertical switching mode, and horizontal switching mode in the paper, respectively.The three kinds of basic switching modes are illustrated in Figure 2.

Three Basic Switching Modes
The basic switching mode and switching path are defined as follows: (1) Basic switching mode: the value of a, b or c is changed with 1 pu between two adjacent switching states.There are three kinds of basic switching modes in space vector diagram, and the three kinds of basic switching modes is named as diagonal switching mode, vertical switching mode,and horizontal switching mode in the paper, respectively.The three kinds of basic switching modes are illustrated in Figure 2. (2) Switching path: a trajectory is formed by a finite number of basic switching modes in turn.
The increment expression of Equation ( 1) is described in Equation (2).
where, △a, △b and △c are the increment of a, b and c in the abc coordinate system.△α′ and △β′ are the increment of α′ and β′.
If phase A voltage is changed with 1 pu in one basic switching mode, subject to: Substituting Equation (3) in Equation ( 2), the expression of the diagonal switching mode is written in Equation ( 4): If phase B voltage is changed with 1 pu in one basic switching mode, subject to: Substituting Equation (5) in Equation ( 2), the expression of the vertical switching mode is written in Equation ( 6): If phase C voltage is changed with 1 pu in one basic switching mode, subject to: Substituting Equation (7) in Equation ( 2), the expression of the horizontal switching mode is written in Equation ( 8): (2) Switching path: a trajectory is formed by a finite number of basic switching modes in turn.
The increment expression of Equation ( 1) is described in Equation (2).
where, ∆a, ∆b and ∆c are the increment of a, b and c in the abc coordinate system.∆α and ∆β are the increment of α and β .
If phase A voltage is changed with 1 pu in one basic switching mode, subject to: Substituting Equation (3) in Equation ( 2), the expression of the diagonal switching mode is written in Equation ( 4): If phase B voltage is changed with 1 pu in one basic switching mode, subject to: Substituting Equation (5) in Equation ( 2), the expression of the vertical switching mode is written in Equation (6): If phase C voltage is changed with 1 pu in one basic switching mode, subject to: Substituting Equation (7) in Equation ( 2), the expression of the horizontal switching mode is written in Equation ( 8): Energies 2017, 10, 725 4 of 18 As shown in Figure 2, the locus of diagonal switching mode is from V 2 to V 1 , the locus of vertical switching mode is from V 2 to V 0 or V 1 to V 3 , and the locus of vertical switching mode is from V 3 to V 2 or V 0 to V 1 .The increment relationships between a, b, c and α , β are listed in Table 1.

Characteristics of Switching Paths
It is shown in Figures 1b and 2 that any triangle is formed by the above-mentioned three basic switching modes.If a switching path is composed of three sides of a triangle by end to end, the constraint relationships of the realization of the starting vector before and after the switching path can be written-in Equation ( 9): where, (a 0 , b 0 , c 0 ) and ( â0 , b0 , ĉ0 ) are the realization of the starting vector before and after switching path, respectively.The sign of (1, 1, 1) is determined by the direction of switching path.If the direction of switching path is clockwise, the sign is positive, otherwise the sign is negative.However, if the switching path is composed of four sides of a quadrangle by end to end, the constraint relationships of the realization of the starting vectors before and after switching path can be written as: ( â0 , b0 , ĉ0 ) = (a 0 , b 0 , c 0 ), (10) There are three kinds of quadrangles formed by right triangle A and B, and the three kinds of quadrangles are shown in Figure 3.
Energies 2017, 10, 725 4 of 18 As shown in Figure 2, the locus of diagonal switching mode is from V2 to V1, the locus of vertical switching mode is from V2 to V0 or V1 to V3, and the locus of vertical switching mode is from V3 to V2 or V0 to V1.The increment relationships between a, b, c and α′, β′ are listed in Table 1.

Characteristics of Switching Paths
It is shown in Figures 1b and 2 that any triangle is formed by the above-mentioned three basic switching modes.If a switching path is composed of three sides of a triangle by end to end, the constraint relationships of the realization of the starting vector before and after the switching path can be written-in Equation ( 9): where, are the realization of the starting vector before and after switching path, respectively.The sign of (1, 1, 1) is determined by the direction of switching path.If the direction of switching path is clockwise, the sign is positive, otherwise the sign is negative.
However, if the switching path is composed of four sides of a quadrangle by end to end, the constraint relationships of the realization of the starting vectors before and after switching path can be written as: There are three kinds of quadrangles formed by right triangle △A and △B, and the three kinds of quadrangles are shown in Figure 3.As described above, if switching paths consist of the four sides of the quadrangles, the proposed SVPWM scheme will be achieved.As described above, if switching paths consist of the four sides of the quadrangles, the proposed SVPWM scheme will be achieved.

Trajectory and Traversing Graphs of Reference Voltage Vector
Generally, the three normalized phase voltages a r , b r and c r for reference voltage vector V r can be defined in Equation (11): where, V m and ω are the peak voltage and angular frequency.E is dc-bus voltage of power cells.Substituting Equation (11) in Equation ( 1): where, [α r , β r ] T is the coordinate values of V r .Equation ( 12) can be rewritten as: The trajectory of V r is shown in Figure 4.It can be seen that the trajectory of V r is an ellipse.

Trajectory and Traversing Graphs of Reference Voltage Vector
Generally, the three normalized phase voltages ar, br and cr for reference voltage vector Vr can be defined in Equation (11): where, Vm and ω are the peak voltage and angular frequency.E is dc-bus voltage of power cells.Substituting Equation (11) in Equation ( 1): ) sin( 33 where, [ , ] Equation ( 12) can be rewritten as: The trajectory of Vr is shown in Figure 4.It can be seen that the trajectory of Vr is an ellipse.3. The Proposed SVPWM Scheme

Trajectory and Traversing Graphs of Reference Voltage Vector
Generally, the three normalized phase voltages ar, br and cr for reference voltage vector Vr can be defined in Equation (11): where, Vm and ω are the peak voltage and angular frequency.E is dc-bus voltage of power cells.Substituting Equation (11) in Equation ( 1): ) sin( 33 where, [ , ] Equation ( 12) can be rewritten as: The trajectory of Vr is shown in Figure 4.It can be seen that the trajectory of Vr is an ellipse.Where, m is modulation index, and the red and green ellipses are the trajectories of reference voltage vector with maximum modulation index and minimum modulation index in the corresponding case.If m is between maximum and minimum modulation index, the trajectories of reference voltage vector is plotted with cyan ellipse.As shown in Figure 5, any traversing graph is composed of three kinds of quadrilaterals.

Switching Path Planning
As shown in Figure 3, there are two common vertexes, named as interface vector 1 and interface vector 2 .If the interface vector is chosen as a starting vector, the three vectors in the same triangle can be applied with two basic switching modes.Otherwise, at least three basic switching modes are needed.
For example, if interface vector 1 (V 10 ) is chosen as the starting vector in A in Figure 3a, the three vectors can be applied with the switching path V 10 →V 11 →V 12 .If interface vector 2 (V 12 ) is chosen as starting vector, the three vectors can be applied with the switching path V 12 →V 11 →V 10 .However, if vector V 11 is chosen as a starting vector, the three vectors is applied with the switching path V 11 →V 12 →V 11 →V 10 or V 11 →V 10 →V 11 →V 12 .Hence, the non-common vertexes should be not chosen as a starting vector in the proposed SVPWM scheme.
The switching paths of the proposed SVPWM scheme are divided into three categories: switching paths in a triangle, switching paths not in a triangle but in a quadrilateral and switching paths between quadrilaterals.

Switching Paths in a Triangle
The switching paths in the same triangle for the three kinds of quadrangles are illustrated in Figures 6-8, respectively, where, V xout (x = 1, 2, 3) are the first, the second and the third vector in the previous switching path, and V xout (x = 1, 2, 3) are the first, the second and the third vector in the current switching path.The vertex with red circles is the third vector in the previous switching path.The direction of the switching path is marked with blue arrows.
Energies 2017, 10, 725 6 of 18 where, m is modulation index, and the red and green ellipses are the trajectories of reference voltage vector with maximum modulation index and minimum modulation index in the corresponding case.If m is between maximum and minimum modulation index, the trajectories of reference voltage vector is plotted with cyan ellipse.As shown in Figure 5, any traversing graph is composed of three kinds of quadrilaterals.

Switching Path Planning
As shown in Figure 3, there are two common vertexes, named as interface vector ① and interface vector ②.If the interface vector is chosen as a starting vector, the three vectors in the same triangle can be applied with two basic switching modes.Otherwise, at least three basic switching modes are needed.
For example, if interface vector ① (V10) is chosen as the starting vector in △A in Figure 3a, the three vectors can be applied with the switching path V10→V11→V12.If interface vector ② (V12) is chosen as starting vector, the three vectors can be applied with the switching path V12→V11→V10.However, if vector V11 is chosen as a starting vector, the three vectors is applied with the switching path V11→V12→V11→V10 or V11→V10→V11→V12.Hence, the non-common vertexes should be not chosen as a starting vector in the proposed SVPWM scheme.
The switching paths of the proposed SVPWM scheme are divided into three categories: switching paths in a triangle, switching paths not in a triangle but in a quadrilateral and switching paths between quadrilaterals.

Switching Paths in a Triangle
The switching paths in the same triangle for the three kinds of quadrangles are illustrated in Figures 6-8, respectively, where, V′xout(x = 1, 2, 3) are the first, the second and the third vector in the previous switching path, and Vxout(x = 1, 2, 3) are the first, the second and the third vector in the current switching path.The vertex with red circles is the third vector in the previous switching path.The direction of the switching path is marked with blue arrows.Energies 2017, 10, 725 7 of 18

Switching Paths not In a Triangle but in a Quadrilateral
The feature in this situation is that the switching path is from A into B. The switching paths for the three kinds of quadrangles are shown in Figures 9-11, respectively.Where, the solid and dashed arrows represent the direction of the current switching path and the previous switching path, respectively.The cyan arrows are the locus of reference vector.

Switching Paths between Quadrilaterals
The feature in this situation is that the switching path is from △B into △A.The transition graph between the first kind of quadrilateral and other kinds of quadrilaterals, the transition graph between the second kind of quadrilateral and other kinds of quadrilaterals, and the transition graph between the third kind of quadrilateral and other kinds of quadrilaterals are shown in Figure 12a-c, respectively.In Figure 12

Switching Paths between Quadrilaterals
The feature in this situation is that the switching path is from △B into △A.The transition graph between the first kind of quadrilateral and other kinds of quadrilaterals, the transition graph between the second kind of quadrilateral and other kinds of quadrilaterals, and the transition graph between the third kind of quadrilateral and other kinds of quadrilaterals are shown in Figure 12a-c, respectively.In Figure 12

Switching Paths between Quadrilaterals
The feature in this situation is that the switching path is from B into A. The transition graph between the first kind of quadrilateral and other kinds of quadrilaterals, the transition graph between the second kind of quadrilateral and other kinds of quadrilaterals, and the transition graph between the third kind of quadrilateral and other kinds of quadrilaterals are shown in Figure 12a-c, respectively.In Figure 12, AX (X = 1, 2, 3) and BX (X = 1, 2, 3) represent A and B triangle in the X th kind of quadrilateral, and AX (AY) (X = Y) represents the common A triangle in X th and Y th kind of quadrilateral.V 4x (x = 1, 2, . . ., 9, 10), V 5x (x = 1, 2, . . ., 9, 10) and V 6x (x = 1, 2, . . ., 9, 10) are the vectors in the transition graph.The feasible switching paths between different kinds of quadrilaterals are listed in Tables 2-4.

Switching Paths between Quadrilaterals
The feature in this situation is that the switching path is from △B into △A.The transition graph between the first kind of quadrilateral and other kinds of quadrilaterals, the transition graph between the second kind of quadrilateral and other kinds of quadrilaterals, and the transition graph between the third kind of quadrilateral and other kinds of quadrilaterals are shown in Figure 12a-c, respectively.In Figure 12  Step ( 5): If the first vector was located in zone III, the realization of the first vector is obtained with the realization (n, n, −n) of vector (2n, 0), and the switching path is comprised of the third kind of quadrilaterals.
Step (3): If the first vector was located in zone I, the realization of the first vector is obtained with the realization (−n, n, n) of vector (−2n, 2n), and the switching path consists of the first kind of quadrilaterals.
Step (4): If the first vector was located in zone II, the realization of the first vector is obtained with the realization (−n, n, n) of vector (−2n, 2n), and the switching path consists of the second kind of quadrilaterals.
Step ( 5): If the first vector was located in zone III, the realization of the first vector is obtained with the realization (n, n, −n) of vector (2n, 0), and the switching path is comprised of the third kind of quadrilaterals.
Step (3): If the first vector was located in zone I, the realization of the first vector is obtained with the realization (−n, n, n) of vector (−2n, 2n), and the switching path consists of the first kind of quadrilaterals.
Step (4): If the first vector was located in zone II, the realization of the first vector is obtained with the realization (−n, n, n) of vector (−2n, 2n), and the switching path consists of the second kind of quadrilaterals.
Step ( 5): If the first vector was located in zone III, the realization of the first vector is obtained with the realization (n, n, −n) of vector (2n, 0), and the switching path is comprised of the third kind of quadrilaterals.

Realization of Other Vectors
Upon the realization of the first vector, the realization of other vectors can be achieved with the increment relationships between (a, b, c) and (α′, β′) in the three basic switching modes, as shown in Figure 15.

Realization of Other Vectors
Upon the realization of the first vector, the realization of other vectors can be achieved with the increment relationships between (a, b, c) and (α , β ) in the three basic switching modes, as shown in Figure 15.

Flowchart of the Implementation of the SVPWM Scheme
The flowchart of the implementation of the SVPWM scheme is shown in Figure 16.The location of reference voltage vector and the selection strategy for the nearest three vectors can be obtained in [24].The planning of the switching paths is demonstrated in Section 3.2, and the realization of vectors is described in Section 3.3.

Experimental Setup
A 7-level cascaded multilevel inverter is built in the laboratory, as shown in Figure 17.Nine isolation DC power for the 7-level inverter are formed by nine 200 W isolation transformers and diode rectifier bridges.The dc-bus voltage of power cells is selected as 50 V.The model of switches in the inverter is IRFP460, and the driver circuits are composed of high-speed opt-coupler (model: 6N137) and IR2110.The inverter is controlled by a TMS320F28335 floating-point DSP from Texas Instruments (Dallas, TX, USA).The experimental setup is shown in Figure 18.

Flowchart of the Implementation of the SVPWM Scheme
The flowchart of the implementation of the SVPWM scheme is shown in Figure 16.The location of reference voltage vector and the selection strategy for the nearest three vectors can be obtained in [24].The planning of the switching paths is demonstrated in Section 3.2, and the realization of vectors is described in Section 3.3.

Flowchart of the Implementation of the SVPWM Scheme
The flowchart of the implementation of the SVPWM scheme is shown in Figure 16.The location of reference voltage vector and the selection strategy for the nearest three vectors can be obtained in [24].The planning of the switching paths is demonstrated in Section 3.2, and the realization of vectors is described in Section 3.3.

Experimental Setup
A 7-level cascaded multilevel inverter is built in the laboratory, as shown in Figure 17.Nine isolation DC power for the 7-level inverter are formed by nine 200 W isolation transformers and diode rectifier bridges.The dc-bus voltage of power cells is selected as 50 V.The model of switches in the inverter is IRFP460, and the driver circuits are composed of high-speed opt-coupler (model: 6N137) and IR2110.The inverter is controlled by a TMS320F28335 floating-point DSP from Texas Instruments (Dallas, TX, USA).The experimental setup is shown in Figure 18.

Experimental Setup
A 7-level cascaded multilevel inverter is built in the laboratory, as shown in Figure 17.Nine isolation DC power for the 7-level inverter are formed by nine 200 W isolation transformers and diode rectifier bridges.The dc-bus voltage of power cells is selected as 50 V.The model of switches in the inverter is IRFP460, and the driver circuits are composed of high-speed opt-coupler (model: 6N137) and IR2110.The inverter is controlled by a TMS320F28335 floating-point DSP from Texas Instruments (Dallas, TX, USA).The experimental setup is shown in Figure 18.

Experimental Results
The waveforms of the 7-level inverter with different modulation indexes are shown in Figure 19.Where, the fundamental frequency of output voltage is set to be 100 Hz.

Experimental Results
The waveforms of the 7-level inverter with different modulation indexes are shown in Figure 19.Where, the fundamental frequency of output voltage is set to be 100 Hz.

Experimental Results
The waveforms of the 7-level inverter with different modulation indexes are shown in Figure 19.Where, the fundamental frequency of output voltage is set to be 100 Hz.

Experimental Results
The waveforms of the 7-level inverter with different modulation indexes are shown in Figure 19.Where, the fundamental frequency of output voltage is set to be 100 Hz.As seen from Figure 19e,j, the phase voltage is kept at the highest level for some time without changing.The corresponding graph on uncharged parts of the phase voltage A and the traversing graph is illustrated in Figure 20.As shown in Figure 20, there is no diagonal switching mode in the magenta region.Hence, the phase voltage A remains unchanged.The similar conclusions can be obtained in the yellow region and the blue region.For simplicity, we choose 5-level inverter to analyze the number of commutations of switches for different switching paths.
There are two traversing graphs when the reference voltage are in the outermost layer, and the switching paths for the two traversing graphs are shown in Figure 21.Where, solid lines stand for the feasible basic switching modes, and dotted lines are the forbidden basic switching modes.As seen from Figure 19e,j, the phase voltage is kept at the highest level for some time without changing.The corresponding graph on uncharged parts of the phase voltage A and the traversing graph is illustrated in Figure 20.
Energies 2017, 10, 725 13 of 18 As seen from Figure 19e,j, the phase voltage is kept at the highest level for some time without changing.The corresponding graph on uncharged parts of the phase voltage A and the traversing graph is illustrated in Figure 20.As shown in Figure 20, there is no diagonal switching mode in the magenta region.Hence, the phase voltage A remains unchanged.The similar conclusions can be obtained in the yellow region and the blue region.For simplicity, we choose 5-level inverter to analyze the number of commutations of switches for different switching paths.
There are two traversing graphs when the reference voltage are in the outermost layer, and the switching paths for the two traversing graphs are shown in Figure 21.Where, solid lines stand for the feasible basic switching modes, and dotted lines are the forbidden basic switching modes.As shown in Figure 20, there is no diagonal switching mode in the magenta region.Hence, the phase voltage A remains unchanged.The similar conclusions can be obtained in the yellow region and the blue region.For simplicity, we choose 5-level inverter to analyze the number of commutations of switches for different switching paths.
There are two traversing graphs when the reference voltage are in the outermost layer, and the switching paths for the two traversing graphs are shown in Figure 21.Where, solid lines stand for the feasible basic switching modes, and dotted lines are the forbidden basic switching modes.If interface vector ① is chosen as the starting vector, the number of commutations of switches is 2Mj in a quadrilateral.Where, Mj = Mj1 + Mj2.Mj1 and Mj2 are the number of sampling points in △A and △B, respectively.If the starting vector of current quadrilateral and the ending vector of previous quadrilateral are the same vector, an extra switching modes need to be added.Therefore, the maximum number of commutations of switches for the first class switching path is: where, Mj = Mj1 + Mj2, and J is the number of quadrilateral.
With the above statistical method, the maximum number of commutations of switches for the second class switching path can be calculated as: Table 5 lists the number of commutations of switches for 5-level inverter in the first class switching paths shown in Figure 20a.As shown in Table 5, the actual number of commutations of switches is consistent with the theoretical calculation.The numbers of commutations of switches in one period with different number of sampling points by the proposed SVPWM scheme and the classical SVPWM scheme are shown in Figure 22.Where, the same realizations of all vectors are used by classical SVPWM scheme.If interface vector 1 is chosen as the starting vector, the number of commutations of switches 2M j in a quadrilateral.Where, M j = M j1 + M j2 .M j1 and M j2 are the number of sampling points in A and B, respectively.If the starting vector of current quadrilateral and the ending vector of previous quadrilateral are the same vector, an extra switching modes need to be added.Therefore, the maximum number of commutations of switches for the first class switching path is: where, M j = M j1 + M j2 , and J is the number of quadrilateral.
With the above statistical method, the maximum number of commutations of switches for the second class switching path can be calculated as: Table 5 lists the number of commutations of switches for 5-level inverter in the first class switching paths shown in Figure 20a.As shown in Table 5, the actual number of commutations of switches is consistent with the theoretical calculation.The numbers of commutations of switches in one period with different number of sampling points by the proposed SVPWM scheme and the classical SVPWM scheme are shown in Figure 22.Where, the same realizations of all vectors are used by classical SVPWM scheme.As shown in Figure 22, the average difference in terms of the number of commutations of switches is about 45% between the traditional SVPWM scheme and the proposed SVPWM scheme, which confirms the effectiveness of the proposed method in decreasing the number of commutations of switches.
Because all switching paths are comprised of the three switching modes, only one phase voltage limited in 1 pu is achieved.Compared to other PWM schemes [25][26][27], the proposed SVPWM scheme is also an effective way to decrease the di/dt of the output current and dV/dt of the output voltage for multilevel inverters as well as reduce the switching losses of switches.As shown in Figure 22, the average difference in terms of the number of commutations of switches is about 45% between the traditional SVPWM scheme and the proposed SVPWM scheme, which confirms the effectiveness of the proposed method in decreasing the number of commutations of switches.
Because all switching paths are comprised of the three switching modes, only one phase voltage limited in 1 pu is achieved.Compared to other PWM schemes [25][26][27], the proposed SVPWM scheme is also an effective way to decrease the di/dt of the output current and dV/dt of the output voltage for multilevel inverters as well as reduce the switching losses of switches.

Compared with Other PWM Schemes
Phase voltage and line-to-line voltage waveforms with in-phase disposition PWM (IPDPWM) scheme, phase shifted PWM (PSPWM) scheme, classical SVPWM scheme and proposed SVPWM scheme are shown in Figures 23 and 24, respectively.Where, the fundamental frequency of output voltage is 20 Hz.The modulation index m = 0.94, and the carrier frequency or the sampling frequency for these PWM schemes is 4200 Hz.

Compared with Other PWM Schemes
Phase voltage and line-to-line voltage waveforms with in-phase disposition PWM (IPDPWM) scheme, phase shifted PWM (PSPWM) scheme, classical SVPWM scheme and proposed SVPWM scheme are shown in Figures 23 and 24, respectively.Where, the fundamental frequency of output voltage is 20 Hz.The modulation index m = 0.94, and the carrier frequency or the sampling frequency for these PWM schemes is 4200 Hz.As IPDPWM scheme and PSPWM scheme belong to carrier modulation scheme, the THDs of phase voltage and line-to-line voltage with the two PWM schemes are higher than these of the other scheme.Because phase voltage is kept constant for some time to decrease the number of commutations of the switches in the proposed SVPWM scheme, the THDs of phase voltage with the proposed SVPWM scheme is higher than these of classical SVPWM scheme.However, the THDs of line-to-line voltage with the proposed SVPWM scheme is similar to these of classical SVPWM  As IPDPWM scheme and PSPWM scheme belong to carrier modulation scheme, the THDs of phase voltage and line-to-line voltage with the two PWM schemes are higher than these of the other scheme.Because phase voltage is kept constant for some time to decrease the number of commutations of the switches in the proposed SVPWM scheme, the THDs of phase voltage with the proposed SVPWM scheme is higher than these of classical SVPWM scheme.However, the THDs of line-to-line voltage with the proposed SVPWM scheme is similar to these of classical SVPWM  As IPDPWM scheme and PSPWM scheme belong to carrier modulation scheme, the THDs of phase voltage and line-to-line voltage with the two PWM schemes are higher than these of the other scheme.Because phase voltage is kept constant for some time to decrease the number of commutations of the switches in the proposed SVPWM scheme, the THDs of phase voltage with the proposed SVPWM scheme is higher than these of classical SVPWM scheme.However, the THDs of line-to-line voltage with the proposed SVPWM scheme is similar to these of classical SVPWM As IPDPWM scheme and PSPWM scheme belong to carrier modulation scheme, the THDs of phase voltage and line-to-line voltage with the two PWM schemes are higher than these of the other scheme.Because phase voltage is kept constant for some time to decrease the number of commutations of the switches in the proposed SVPWM scheme, the THDs of phase voltage with the proposed SVPWM scheme is higher than these of classical SVPWM scheme.However, the THDs of line-to-line voltage with the proposed SVPWM scheme is similar to these of classical SVPWM scheme.This is because that the proposed SVPWM scheme is derived from classical SVPWM scheme.As shown in Figure 25, the THD difference between the proposed SVPWM scheme and the classical SVPWM scheme is about 1.2%.Hence, if the proposed SVPWM scheme is used in motor speed control system, the time response of the rotor speed is slightly lower than that of the classical SVPWM scheme.

Conclusions
This paper proposes a novel switching frequency optimized SVPWM.The proposed SVPWM is developed in a α β coordinate system.By planning the switching paths, only one phase voltage limited in dc-bus voltage of power cells is achieved.The experimental results show that the proposed method significantly outperforms the traditional SVPWM in terms of decreasing the number of commutations of switches.

Figure 1 .
Figure 1.Space vector diagram for 3-level inverter in different coordinate systems, (a) in the traditional αβ coordinate system (b) in the α′β′ coordinate system.

Figure 1 .
Figure 1.Space vector diagram for 3-level inverter in different coordinate systems, (a) in the traditional αβ coordinate system (b) in the α β coordinate system.

Figure 2 .
Figure 2. Locus of three basic switching modes.

Figure 2 .
Figure 2. Locus of three basic switching modes.

Figure 3 .
Figure 3. Three kinds of quadrangles, (a) the first kind; (b) the second kind; (c) the third kind.

Figure 3 .
Figure 3. Three kinds of quadrangles, (a) the first kind; (b) the second kind; (c) the third kind.

Figure 5 Figure 5 .
Figure 5 demonstrates the different traversing graphs of reference voltage vector for 7-level inverter with different modulation indexes.

Figure 5
Figure 5 demonstrates the different traversing graphs of reference voltage vector for 7-level inverter with different modulation indexes.

Figure 5 Figure 5 .
Figure 5 demonstrates the different traversing graphs of reference voltage vector for 7-level inverter with different modulation indexes.

Figure 12 .
Figure 12.Transition graphs between different kinds of quadrilaterals, (a) the first kind of quadrilateral; (b) the second kind of quadrilateral; (c) the third kind of quadrilateral.

Figure 12 .
Figure 12.Transition graphs between different kinds of quadrilaterals, (a) the first kind of quadrilateral; (b) the second kind of quadrilateral; (c) the third kind of quadrilateral.

Figure 12 .
Figure 12.Transition graphs between different kinds of quadrilaterals, (a) the first kind of quadrilateral; (b) the second kind of quadrilateral; (c) the third kind of quadrilateral.

Figure 12 .
Figure 12.Transition graphs between different kinds of quadrilaterals, (a) the first kind of quadrilateral; (b) the second kind of quadrilateral; (c) the third kind of quadrilateral.

Figure 13 .
Figure 13.Space vector diagram with three zones.

Figure 15 .
Figure 15.Realization of other vectors, (a) in the first kind of quadrilateral; (b) in the second kind of quadrilateral; (c) in the third kind of quadrilaterals

Figure 16 .
Figure 16.Flowchart of the implementation of the SVPWM scheme.

Figure 15 .
Figure 15.Realization of other vectors, (a) in the first kind of quadrilateral; (b) in the second kind of quadrilateral; (c) in the third kind of quadrilaterals.

Figure 15 .
Figure 15.Realization of other vectors, (a) in the first kind of quadrilateral; (b) in the second kind of quadrilateral; (c) in the third kind of quadrilaterals

Figure 16 .
Figure 16.Flowchart of the implementation of the SVPWM scheme.

Figure 16 .
Figure 16.Flowchart of the implementation of the SVPWM scheme.

Figure 19 .
Figure 19.Waveforms of the 7-level inverter, (a) phase voltage A with m = 0.981; (b) line-to-line voltage AB with m = 0.981; (c) phase voltage A with m = 0.922; (d) line-to-line voltage AB with m = 0.922; (e) phase voltage A with m = 0.75; (f) details of the waveform in (f); (g) phase voltage A with m = 0.665; (h) phase voltage A with m = 0.665; (i) line-to-line voltage AB with m = 0.665; (j) details of the waveform in (j).

Figure 20 .
Figure 20.Corresponding graph on unchanged parts of the phase voltage A and traversing graph.

Figure 19 .
Figure 19.Waveforms of the 7-level inverter, (a) phase voltage A with m = 0.981; (b) line-to-line voltage AB with m = 0.981; (c) phase voltage A with m = 0.922; (d) line-to-line voltage AB with m = 0.922; (e) phase voltage A with m = 0.75; (f) details of the waveform in (f); (g) phase voltage A with m = 0.665; (h) phase voltage A with m = 0.665; (i) line-to-line voltage AB with m = 0.665; (j) details of the waveform in (j).

Figure 19 .
Figure 19.Waveforms of the 7-level inverter, (a) phase voltage A with m = 0.981; (b) line-to-line voltage AB with m = 0.981; (c) phase voltage A with m = 0.922; (d) line-to-line voltage AB with m = 0.922; (e) phase voltage A with m = 0.75; (f) details of the waveform in (f); (g) phase voltage A with m = 0.665; (h) phase voltage A with m = 0.665; (i) line-to-line voltage AB with m = 0.665; (j) details of the waveform in (j).

Figure 20 .
Figure 20.Corresponding graph on unchanged parts of the phase voltage A and traversing graph.

Figure 20 .
Figure 20.Corresponding graph on unchanged parts of the phase voltage A and traversing graph.

Figure 21 .
Figure 21.Switching paths for 5-level inverter in the outermost layer, (a) the first class switching path, (b) the second class switching path.

Figure 21 .
Figure 21.Switching paths for 5-level inverter in the outermost layer, (a) the first class switching path, (b) the second class switching path.

Figure 22 .
Figure 22.Numbers of commutations of switches with different number of sampling points in one period, (a) 42 sampling points; (b) 64 sampling points; (c) 84 sampling points; (d) 105 sampling points; (e) 126 sampling points.

Figure 22 .
Figure 22.Numbers of commutations of switches with different number of sampling points in one period, (a) 42 sampling points; (b) 64 sampling points; (c) 84 sampling points; (d) 105 sampling points; (e) 126 sampling points.

Figure 25 .
Figure 25.THDs of phase voltage and line-to-line voltage of 5-level inverter with different PWM schemes, (a) phase voltage; (b) line-to-line voltage.

Table 1 .
Three basic switching modes.

Table 1 .
Three basic switching modes.

Table 5 .
Number of commutations of switches for 5-level inverter.

Table 5 .
Number of commutations of switches for 5-level inverter.