Output Voltage Quality Evaluation of Stand-alone Four-Leg Inverters Using Linear and Non-Linear Controllers

This paper presents the design and experimental voltage quality evaluation of controllers for the output voltages of 3-phase four-leg voltage source inverters. These inverters are needed in stand-alone power systems to supply linear and non-linear, balanced or unbalanced loads with constant RMS value voltages at fixed frequency. Comparisons include closed loop outer voltage controllers based on predictive, sliding mode and decoupled proportional-integral controllers in dqo synchronous space, fitted with an inner hysteretic current loop vector controller in αβγ space. The 3-phase four-leg VSI output voltages waveform quality is analysed under unbalanced and non-linear loads.


Introduction
Many electric power systems, such as distributed generation systems, variable frequency fed stand-alone power systems, uninterruptible power supplies and active filters need the use of power electronic converters.These power converters, in a back-to-back connection, can output sinusoidal voltages with precise amplitude frequency, even if the stand-alone generator is operating at variable speed (frequency) to maximise its efficiency.Voltage source inverters (VSI) are commonly used to transfer power between a DC system to an AC system or to work as back-to-back power electronic converter to connect AC systems with different frequencies [1].
In three-phase low-voltage electric systems a neutral wire is usually needed to provide a current path for linear/non-linear unbalanced loads or to feed single-phase loads.Therefore, the 3-phase VSI must have an extra wire connection to the load neutral, becoming a four-wire inverter.
Four-wire inverters are capable of supplying unbalanced and/or non-linear loads connected to stand-alone power supply systems.Besides, they accept input power at any frequency from a rectifier, which is important to allow variable frequency generators.This solution avoids the use of the electric transformer ∆-Yg to obtain an access to neutral point [2,3].The neutral wire can be formed from the inverter using three different topologies: • 3-phase 4-wire.The neutral point is connected to midpoint of the DC-link capacitors [3][4][5]; • 3-phase four-leg.With an additional inverter leg enabling the neutral voltage control [6][7][8]; • a combination of DC split capacitors and the neutral leg.The control of the neutral point is decoupled from the control of the 3-phase VSI [9].
The first solution uses the 3-phase inverter that can be controlled as three independent single-phase inverters.The disadvantage for the split capacitor converter is the large and expensive DC-link capacitors needed to maintain acceptable voltage ripple level across the DC-link capacitors in case of a large zero-sequence current due to unbalanced or non-linear load [6].However, this topology has advantages, saving two power semiconductors and reducing control complexity [3].The four-leg VSI solution requires two additional power switches, but it offers advantages, such as an increased maximum output voltage value, a reduction of neutral currents and the possibility of neutral voltage control [6].In the third solution, the neutral point is still provided by two split capacitors and the fourth leg is really an active filter independent from the 3-phase legs.Thus, the fourth leg is controlled to cancel the zero-sequence current in unbalanced or non-linear loads, so that the neutral current does not flow through the DC-link capacitors.This approach needs a smaller DC-link capacitance for the same voltage ripple.However, it still suffers from insufficient use of the DC-link voltage as the first topology [10].Considering the merits and demerits of topologies for the 3-phase VSIs, in this study the four-leg VSI is considered for their advantages to high-performance applications, where a good power quality might be required, or when sensitive electronics equipment are used as four-leg VSI loads [10].
The four-leg VSI applicability to stand-alone power systems should take into account the control of the DC-link voltage, since the load transients on AC side may cause disturbances in the four-leg VSI DC side [11].Based on the stand-alone power sources that feed the four-leg inverter, a short-term or a long-term response energy storage system [12,13], should be considered to minimize the effect of disturbance transients analyzed in DC-link and to allow the four-leg inverter correct operation.In this paper, the control of DC voltage side is not presented, but it uses a supercapacitor energy storage system [14], that keeps the DC voltage within a maximum deviation of 4% from its nominal value, during the presented transient tests [15].
Considering performance, this paper presents the converter model and designs, evaluates and compares output voltage control loops based on predictive, sliding mode and proportional-integral controllers in dqo synchronous space.An internal hysteretic current loop vector controller in αβγ space is common to all the voltage controllers.The paper is organized as follows: Section II presents the four-leg VSI modelling.The four-leg VSI current loop vector controller in αβγ space is described in section III and voltage controllers are presented and discussed in section IV.In section V a performance evaluation of four-leg VSI with unbalanced and non-linear loads is presented.The paper closes with the conclusions and future work on this subject.

Four-Leg VSI Modelling
The 3-phase four-leg VSI supplied by a constant DC voltage, u DC , and the output LC filter are show in Figure 1.The outputs of four-leg VSI are denoted by phases a, b, c and the neutral n terminals and the LC filter output terminals denoted by A, B, C, and N (neutral).The three-phase LC filter reduces the output waveform carrier frequency components content.The semiconductors S 1k and S 2k are considered to be ideal.Their states can be represented by a leg switching variable, γ k , where k = {a, b, c, n} (1).
The voltages u a , u b , u c , u n measured between the terminals a, b, c, n and the negative DC-link of the four-leg VSI, can be expressed as in (2).The phase voltages of the four-leg inverter, u an , u bn , u cn are expressed in matrix form: The state-space matrix equations to calculate the four-leg VSI currents, i a , i b and i c , can be outlined as (4).
In (4), r f and L f represent, respectively, the LC filter parasite resistance and inductance per phase.The i a , i b , i c and i n represents, respectively, the four-leg VSI currents flowing in outer direction of the a, b, c, and n terminals.The u AN , u BN , u CN are the three phase-neutral load voltages and u Nn the voltage drop on neutral inductance filter.The I 3 represents the 3 by 3 identity matrix.The phase-neutral u AN , u BN , u CN voltages are derived from capacitor voltages equations in state-space form (5).
In (5), i ABC represents the 3-phase load currents and C f is the LC filter capacitance.For unbalanced loads the neutral currents, i n and i N , are obtained from Kirchhoff's first law of four-leg VSI currents circuit analysis (6).
The DC-link current, i o , depends of the switching state of each VSI leg, γ k , and the output currents, by (7).

Four-Leg VSI Output Voltage Vectors in Stationary αβγ Reference Frame
Using the Concordia matrix transformation [16], the voltages quantities in αβγ stationary reference frame, u α , u β and u γ are obtained.Depending on the γ k state values, the four-leg VSI has 2 4 possible states.Figure 2 presents the voltage vectors in αβγ space, V j (γ n , γ c , γ b , γ a ), where j = {0, 1, 2, ..., 15} represents the voltage vector number.The projection of the all voltages vectors in αβ plane match the well-known 3-leg VSI eight output voltages plane.

Current Loop Vector Controller
For short circuit protection and power limitation, an inner current control loop is adopted with a vector control strategy on the stationary α, β, γ space reference.The outer synchronous dqo frame voltage loops generate constant output voltages with constant frequency to supply both linear/non-linear, balanced/unbalanced loads, Figure 3.
The current loop vector controller (CVC) for the four-leg VSI is derived from the previously proposed vector current control for 3-phase 3-leg VSIs under balanced loads, that selects a suitable vector out of the 2 3 possible voltage vectors in the αβ plane reference [14,15].This technique is here extended to the 3-phase four-leg VSI, considering now the 2 4 u α , u β , u γ voltage vectors.
The input references currents, i * d , i * q , and i * o , are transformed to new input reference currents, i * α , i * β , and i * γ , using the dqo − αβγ rotational matrix transformation [16].The angular electrical speed and position are represented by, ω e and θ e , respectively.The measured four-leg VSI output currents are also transformed to αβγ coordinates using the Concordia transformation matrix.Comparing the references and output currents the errors of each αβγ components, e iα , e iβ and e iγ , are obtained (8).The CVC uses three hysteretic comparators to evaluate the current errors in three discrete values: negative, null and positive (9).
In ( 9), ∆ is the hysteresis band width and δ κ the output values of hysteretic comparators, δ α , δ β and δ γ .Equation ( 4) can be written in a compact form using αβγ coordinates from the Concordia transformation matrix: The CVC control strategy is described by (11).The selection of the αβγ voltage vector is obtained by the needed αβγ current time derivatives, according to (10).
Table 1 presents the voltage vector selection, based on the analysis of the current errors.In some cases more than one vector can be selected.The voltage vector decision, in the case where more than one vector is available, is solved considering the sum of two comparators output states with two different hysteretic levels, large and narrow, δ Lκ and δ Nκ , respectively, with κ ∈ {α, β, γ}. Figure 4 the αβγ vector currents controller using 3-level hysteretic comparators, δ κ , as a sum of large and narrow 2-level hysteretic comparators, δ Lκ and δ Nκ , respectively [17].In (12), this approach is shown to solve the multiple voltage vectors decision, using an example of Table 1 where The αβγ vector currents controller using 3-level hysteretic comparators.
The condition (δ α = 0) ∧ (δ β = 0) ∧ (δ γ = 0) implies the decision of the null voltage vectors, 0 or 15, to minimize the switching frequency, reducing the four-leg VSI switching losses.A simple algorithm to minimize the semiconductors commutations can be applied.The current error output states and the switching frequency of semiconductor devices depend on the hysteretic comparator window width.Reducing the hysteretic window leads to reduced current errors (ripple), but increases the semiconductor switching frequency.The optimum value of the width of hysteresis window should be balanced for currents admissible ripple and power converter switching losses.
Figure 5 shows the simulation of the 3-phase four-leg VSI currents with CVC.Unbalanced currents reference and linear loads were considered to obtain these results.The phase and neutral current references, i * a , i * b , i * c and i * n , respectively, are enclosed by the corresponding output currents ripple of the four-leg VSI.

Load Voltage Control
This section explains the design of optimal load voltage controllers that preserve the constant magnitude phase difference and frequency of symmetrical 3-phase sinusoidal load voltages.Starting from the load voltages dynamic model, a non-linear voltage controller is deduced from two control methods: the predictive control (Section 4.1) and the sliding mode control (Section 4.2); and for comparison purposes the classical PI controller (Section 4.3).Considering the Blondel-Park matrix transformation, C(θ e ) [16], and using the compact form relations (13), the load voltages dynamic model in (5), are expressed in the synchronous dqo frame reference, by (14).
In ( 14), the voltages u d , u q , u o , and the currents i d , i q , i o , represent, respectively, the u an , u bn , u cn and i a , i b , i c , four-leg VSI outputs voltages and currents, in dqo coordinates.In same way, i Ld , i Lq , i Lo , represent the 3-phase line loads currents i A , i B , i C .

Load Voltage Optimal Predictive Control
The main goal of Optimal Predictive Control (OPC), is to estimate the values of the dqo frame CVC current references, i * d , i * q , i * o , that minimize voltage errors [17,18].From the four-leg inverter output voltages dynamic model, described by (14), system stability conditions for predictive control are defined (15).
In ( 15), e um , u * m represent the voltage errors vector and the voltage references vector, respectively.The α um is a vector with the dqo controllability constants.Manipulating (15) together with ( 14) and considering α ud = α uq = α uo = α u , the load voltages control laws are obtained (16).

Load Voltage Sliding Mode Control
To design load voltage sliding mode controllers (SMC) able to ensure sinusoidal load voltages, sliding mode surfaces, must be obtained from the load voltage dynamic model (14) [17,19].The three sliding surfaces, S (e um , t) [20,21], are expressed based on dqo frame voltage errors (17).
Comparing the SMC with OPC, it can be seen that the control laws of ( 18) and ( 16), respectively, are similar.Both non-linear controllers, SMC and OPC, lead to the same control solution if β um = α −1 um .Also in SMC and OPC, the AC phase-neutral load voltages references, u * AN , u * BN , u * CN , are a balanced system, the dqo frame load voltages references, u * dqo , are constant in time.Then, the derivatives terms of load voltages references can be neglected in the steady-state.
To avoid large outputs of the derivative term given at high frequency or noise, from (18), the derivative term is modified by using a first-order high-pass filter to apply the derivative action only to low and medium frequencies [23].For digital signal implementation of the output voltage non-linear output controller, from (16) or (18), a discrete-time model of the CVC current references is used (19).
In (19), t s and t s+1 , are the actual and the next time sampling step ∆t u , respectively.The non-linear controller laws considers that the sampled dqo frame load voltages, u d (t s ), u q (t s ), u o (t s ), will follow their voltages references, u d (t s+1 ), u q (t s+1 ), u o (t s+1 ), in one voltage control loop sampling time, ∆t u .The actual time line load currents are represented in dqo frame by i Ld , i Lq , i Lo .
As can be seen from ( 14) the direct and quadrature axes are coupled through ω e C f term.The non-linear controller (19) uses decoupling terms to cancel this coupling.The currents, i Ld , i Lq and i Lo are measured and used to calculate the current references, i * d , i * q , i * o .

Load Voltage Decoupled PI Control
To use simple PI controllers it is necessary to decouple the cross coupling terms of the load voltage dynamic model ( 14).This can be done with two auxiliary variables [18], h d and h q , defined by (20).
Substituting ( 20) in ( 14), a decoupled model for the load voltages control can be obtained and the PI controllers, C m (s), with proportional and integral gains, K pm and K im , respectively, could be designed for each dqo frame control loop in the frequency-domain, taking into account a first order dynamics CVC model, , with unitary gain and T d as the dominant pole of average delay time, due the switching period of four-leg inverter, and m ∈ {d, q, o}, Figure 6.Two implementations of decoupled PI (DPI) controllers are considered the common implementation given by ( 21) and an alternative PI controller implementation, where the proportional gain, K pm is applied only to the output signal (22).
The closed loop transfers functions of four-leg inverter output voltage, , considering the two DPI approaches of ( 21) and ( 22) are given by ( 23) and (24), respectively.
The transfer function between the disturbance and the output voltage, u m (s) i Lm (s) , is given by (25).
From ( 24) or ( 25), the PI gains, K pm and K im , of each dqo closed loop transfer function, , are obtained by the ITAE criteria (integral function of time multiplied by the absolute magnitude of the error) in order to allow good disturbance rejection, considering the third-order system optimum coefficients for a step input [23] (26).
Figure 7 presents the step responses for both DPI controllers taking as an example the u q output voltage loop control.The usual PI controller presents a large overshoot, 46%, and the modified PI reduces the overshoot to 2%.The settling time is very close for both PI controllers, 1.5 ms and 1.3 ms, respectively.The disturbance time recovery is the same for both PI controllers, 1.5 ms.Considering the alternative PI controller (23), the control laws for i * d , i * q , i * o , are obtained by inversion of decoupling variables, h d and h q (27).
For the practical implementation, the PI controllers should have an anti-windup system to prevent the accumulation of integral errors when the currents limiters are active [23].

Performance Analysis of Four-Leg VSI
For comparison purposes a 3-phase four-leg VSI up to 20 kVA, with power factor of 0.8 lagging and an output sinusoidal voltage of 400 V-50 Hz was considered.The experimental results were obtained from a four-leg VSI laboratory prototype with the following parameters: u DC = 650 V; The four-leg VSI laboratory prototype, Figure 8, was developed using SKM200 half-bridge IGBT modules and the double driver SKHI 23/12R both from SEMIKRON (SEMIKRON International GmbH, Nuremberg, Germany).The control system was implemented in a FPGA development board Virtex® 6 (Xilinx Inc., San Jose, CA, USA) and the control algorithms for CVC and output voltage controllers (non-linear and linear) were developed in high-level programming language System Generator for DSP™ (Xilinx Inc., San Jose, CA, USA) under MATLAB® (The MathWorks Inc., Natick, MA, USA) and Simulink® (The MathWorks Inc., Natick, MA, USA) environments.
The data acquisition system is based on analog-digital converter ADC7609 (Analog Devices Inc, Norwood, MA, USA) and the currents and voltages were measured, respectively, through the Hall effect sensors LA100-P/SP3 and LV25-P/SP5 from LEM® (LEM Holding SA, Fribourg, Switzerland).The 3-phase four-leg voltage inverter output voltage waveform quality evaluation was divided into steady-state and dynamic response tests [24,25].To the evaluation of experimental results of the four-leg inverter at steady-state operation, the power quality monitoring Fluke 435 (Fluke Corporation, Everett, WA, USA) was used.

Steady-State Performance Analysis
The steady-state performance analysis is obtained considering three performance criterion: the voltage regulation, the voltage total harmonic distortion and the voltage imbalance [24,25].Voltage regulation, V R (%), is a quantity to evaluate the ability of the bus to supply the load currents without changing its voltage amplitude [25].The total harmonic distortion is the most common harmonic index used to indicate the harmonic content of a distorted waveform [25].The total voltage harmonic distortion, THD V , is defined as the rms of the harmonics, V h , expressed in percentage of the fundamental voltage component.The voltage imbalance (or unbalance) refers to the deviation of phase voltages from their rated values with respect to magnitude and phase.One of the methods for characterization of unbalance in power systems is done using the symmetrical components [26].The symmetrical components of output voltages are described by vector sum of the three systems of 3-phase quantities referred as the positive, negative and zero sequence components [16].For power quality evaluation, the voltage imbalance index can be defined in two components, V − imb and V 0 imb , that relate the steady-state output voltage negative and zero sequences components in percentage of the positive sequence component of the output voltage, respectively [27,28].
Figure 9 shows the four-leg inverter steady-state response when it is supplying a balanced linear load obtained from a three-phase resistors bank.Using the same resistive load bank, but with one of the phases disconnected, the steady-state response of the four-leg inverter to an unbalanced linear load is presented in Figure 10.The Table 2 presents the obtained performance analysis results of the four-leg VSI output voltages with linear loads.Comparing the experimental results of two types of output voltage controllers, non-linear (OPC/SMC) and linear (DPI), there is a better voltage waveform quality obtained by the OPC/SMC.This is due to the higher dynamic response speed of the output currents compared with DPI.
Considering the experimental results with balanced and unbalanced linear loads, the performance analysis of four-leg inverter at steady-state operation shows that the voltage deviation value is ±1.3%.There is a THD V up to 2%, and the voltage imbalance indexes, V − imb and V 0 imb , are up to 1.0% and 0.5%, respectively.
To evaluate the output voltage waveforms quality when the four-leg inverter supplies non-linear loads, two electrical circuits that uses diode bridges rectifiers, Figure 11, were considered.Figure 11a presents the balanced non-linear load tested and Figure 11b the unbalanced non-linear load that can be used as phase-neutral or as phase-phase load.3 presents the obtained performance analysis results of the four-leg VSI output voltages with non-linear loads.The four-leg inverter analysis with non-linear loads shows that the output voltages waveforms maintain the desired amplitude and frequency, however, the ripple increases regarding the experimental results with linear loads.However, with non-linear a higher similarity is verified in the results between the OPC/SMC and DPI controllers.
Considering the experimental results with non-linear loads, the performance analysis of four-leg inverter at steady-state operation shows that the voltage deviation is ±1.6%.There is a THD V up to 3%, and the voltage imbalance indexes, V − imb and V 0 imb , are up to 1.6% and 0.5%, respectively.

Dynamic Response Performance Analysis
For the dynamic response performance analysis, the instantaneous sag caused by an impact loading, Figure 14, was considered.To determine the dynamic response, two quantities are measured: the voltage notch amplitude, V not , and its time duration, ∆t [29].
Figure 15 shows a transient test with the four-leg inverter, when from no-load state is turned on a balanced linear load of 12.3 kW, obtained from three-phase resistance.The disturbance in the output voltages waveform has relative amplitude of 26.2% and occurs during 1ms, Figure 15a.Depending of the instant that the load is connected, the voltage disturbance could be imperceptible, as it is seen in Figure 15b, when tested with DPI controller.Figure 15c,d presents the energy storage system transient response to keep constant the DC-link voltage, u DC through the supercapacitors current, i SC .Figure 16 shows the transient test with unbalanced linear load of 8.1 kW, related to the circuit of Figure 11b connected into two output phases.The disturbance in the output voltage waveform presents relative amplitude of 71.8% with a duration of 1.8 ms, which occurred in the test of OPC/SMC, Figure 16a.
Figure 17 presents the direct starting of a three-phase induction motor of 7.5 kW, 400 V-50 Hz and one pair poles.In this laboratory test the current limiters of output voltage controllers, OPC/SMC and DPI, were set to ±30 A. Analyzing the experimental results shown in Figure 17, during the direct starting transient of the three-phase induction motor, there is a sag in the three-phase voltages applied to the motor, comparing with the voltages reference values.This voltage sag is due to the action of the inverter current limiter, I dmax , I qmax and I omax , presented in the output voltages controllers that prevents overcurrents in the four-leg inverter outputs.It is noted that the temporal evolution of the voltages and currents responses is very similar between the OPC/SMC and DPI controllers.
Figure 18 shows the transient test of a balanced non-linear load of 12.7 kW connection (the three-phase diode bridge rectifier load type of Figure 11a).It is noted a small disturbance in output voltages, more visible in the experimental results of the DPI output voltage controller, Figure 18b.Figure 18c,d present the energy storage system transient response to keep constant the DC-link voltage, u DC through the supercapacitors current, i SC .
The load type used in this experimental test has electrolytic capacitors in the DC side, which are initially discharged.Thus, when the load transient of this load type occurs, despite the reduced value of its power in continuous operation, has a considerable disturbance in the output voltage waveforms, due to the current required to initially charge the output load capacitors.
Comparing the experimental results of output voltages controllers, OPC/SMC and DPI, the disturbance caused by the unbalanced non-linear load connection transient is solved in one period time of AC output voltages, to either non-linear and linear controllers.
Figure 19 presents the transient test of the unbalanced non-linear load of 3.5 kW connection (the phase-neutral diode bridge rectifier load of Figure 11b).

Conclusions
This paper presented the design of current and voltage controllers for three-phase four-leg VSI.Predictive, sliding mode and decoupled PI controllers performance were designed, tested and results evaluated.The OPC, SMC and DPI controllers, together with the inner hysteretic current loop vector controller in αβγ space, lead to a variable switching frequency of the four-leg VSI with timely and precise control actions, determined by the control laws of each controller and the allowed currents ripple.The computational resources required to implement the linear and non-linear outer voltage controllers are similar.However, the development of the high-level programming language for non-linear controllers was realized in a more straightforward way, while the programming of the linear controller, due to the need of the anti-windup system, introduces some complexity in the PI controller, to enable it to operate correctly with high load currents.
The steady-state and dynamic performance analysis of the stand-alone four-leg inverter were measured experimentally.In steady-state, the output voltage RMS value presents a root-mean-square voltage deviation of ±1.6% with respect to a voltage reference of 230 V.There is a THD V , less than 3% for the measured loads and voltages imbalance indices, V − imb and V 0 imb , less than 1.6% and 0.5%, respectively.
The dynamic response performance analysis was measured experimentally, by analysing transients created by different types of loads.The results showed the four-leg inverter ability to hold load transients, in general, eliminating voltages notches in less than a half of the voltage waveform period.In the case of load transients that require high currents for a short period of time, the currents are limited to admissible current values by decreasing the output voltages when the current limiters stay active.
Globally, the tests with non-linear output voltage controllers, OPC and SMC, demonstrates a slightly better performance in the output voltages waveform quality than DPI.Overall, the experimental results confirm the output voltage waveform quality characteristics of the four-leg inverter to use in stand-alone power systems with linear and nonlinear, balanced and unbalanced loads.

Figure 1 .
Figure 1.Three-phase four-leg VSI and output LC filter.

Figure 3 .
Figure 3.The 3-phase four-leg VSI and their main control blocks.

Figure 5 .
Figure 5. Simulation result of 3-phase four-leg VSI with αβγ vector currents controller with current references to unbalanced load.

Figure 6 .
Figure 6.Block diagram of closed loop four-leg inverter output voltage control, considering the decoupled PI controllers.

Figure 7 .
Figure 7. Closed-loop step response of decoupled PI controller.

Figure 8 .
Figure 8.View of the four-leg VSI laboratorial setup.

Figures 12 and 13
Figures 12 and 13 presented the steady-state experimental results to evaluate the output voltage waveform quality of the four-leg inverter with balanced (12.7 kW) and unbalanced non-linear loads (phase-neutral, 3.5 kW), respectively.The Table3presents the obtained performance analysis results of the four-leg VSI output voltages with non-linear loads.

Figure 14 .
Figure 14.Example of dynamic voltage response analysis due a load transient (modified from [29]).

Table 2 .
Steady-State performance results of the four-leg VSI with linear loads.

Table 3 .
Steady-state performance results of the four-leg VSI with non-linear loads.