Performance Improvement for Two-Stage Single-Phase Grid-Connected Converters Using a Fast DC Bus Control Scheme and a Novel Synchronous Frame Current Controller

Two-stage single-phase grid-connected converters are widely used in renewable energy applications. Due to the presence of a second harmonic ripple across the DC bus voltage, it is very challenging to design the DC bus voltage control scheme in single-phase grid-connected inverters. The DC bus voltage controller must filter the ripple and balance a tradeoff between low harmonic distortion and high bandwidth. This paper presents a fast DC bus voltage controller, which uses a second order digital finite impulse response (FIR) notch filter in conjunction with input power feedforward scheme to ensure the steady-state and dynamic performance. To gain the input power without extra hardware, a Kalman filter is incorporated to estimate the DC bus input current. At the same time, a modulation compensation strategy is implemented to eliminate the nonlinearity of the grid current control loop, which is caused by the DC bus voltage ripple. Moreover, a novel synchronous frame current controller for single-phase systems is also introduced, and its equivalent model in stationary frame has been derived. Simulation and experimental results are provided to verify the effective of the proposed control scheme.


Introduction
Renewable energy is the key to future global sustainability.Two-stage converters are widely used for interfacing renewable energy resources with the utility grid.The first stage is typically a DC-DC converter for photovoltaics (PVs) or an AC-DC rectifier for wind turbines (WTs) [1].Normally, the first stage performs maximum power point tracking (MPPT) and boosts the input voltage into an appropriate level for the second stage.The main task of the second stage (a DC-AC inverter for most systems) is to ensure that all of the power extracted by the first stage is transferred to the grid stably and smoothly [2,3].Figure 1 shows the configuration of a two-stage single-phase grid-connected converter.
For a two-stage single-phase grid-connected converter, the instantaneous output power pulsates at twice line frequency (2-f).As a strong and robust MPPT control strategy is implemented for the first stage, the input power is controlled to a maximum and constant level at steady state [4].Thus, the DC bus is used to decouple the power pulsation of grid side from the source side.The DC bus capacitor functions as an internal energy storage device to supply the oscillatory output power demand.As a result, there is a 2-f ripple across the DC bus voltage.Regulating the DC bus voltage, which is conducted by the second stage, is vitally important in order to guarantee the reliable operation of the power systems [5].
Energies 2017, 10, 389 2 of 30 which is conducted by the second stage, is vitally important in order to guarantee the reliable operation of the power systems [5].The DC-AC inverter is controlled by a dual-loop control strategy.The outer loop controls the DC bus voltage by generating the reference current for the inner current loop.The inner controller is aimed to achieve adaptive and accurate current tracking.Conventionally, a proportional-integral (PI) controller is utilized to regulate the bus voltage, but it is hard to address the problem caused by the 2-f ripple.As a consequence, the reference for the output current is distorted, and there is a third harmonic component and a phase shift (which causes reactive current injection) at the grid current [6].According to IEEE standard 929-2000 [7], the current total harmonic distortion (THD) must be limited to less than 5%.In order to ensure the quality of the grid current, the bandwidth of the bus voltage control loop is significantly reduced, which makes the transient response poor.The designer has to use large capacitor or high-voltage power switching devices in case of triggering over the voltage protection or malfunction of the inverter during transients.A solution to reduce the 2-f voltage ripple is to connect the energy storage elements to the bus through an active low-frequency ripple control device (ALFRCD), which injects harmonic current into the DC bus [8,9].This approach solves the problem by essentially eliminating the ripple at the bus voltage, while using a minimal bus capacitor.Nevertheless, it exhibits low efficient, and needs complex hardware and control systems for power applications, which makes the overall system expensive or inefficient.
To suppress the distortion in the output current, a second order infinite impulse response (IIR) notch filter [10] or a high order FIR filter [11] can be introduced into the bus control loop to filter the second harmonic ripple.These methods successfully eliminate the distortion.However, since the notch filter brings about a large negative phase shift at the frequencies lower than the notch frequency, the increase of the bus voltage control loop crossover frequency is limited, and dynamic performance can't be good enough.In [12], a power feedforward control scheme, which is one of direct power control (DPC) schemes, is proposed to reduce the DC bus capacitance requirements and to improve the dynamic response for pulse width modulation (PWM) rectifiers.In order to implement the power feedforward control scheme in two-stage single-phase grid-connected converters, the DC bus input current is required and can be provided by the MPPT controller or extra current sensors.However, various topologies are used for the first stage, such as PV moduleintegrated DC-DC converters [13], interleaved parallel DC-DC converters [14], multi-string topologies [15] or multiple renewable energy sources [16].At the same time, the DC-AC inverters in distributed generation systems often provide multi-functions such as, energy management for energy storage devices, power sharing for local loads, communication devices, protection units, and the control center [17].Thus, controlling the two stages by separate processors is required to spread the computational load and enhance the flexible of the system, which makes the power feedforward control hard to implement.
The other main task of the inverter is to rapidly follow the reference current signals.Therefore, a fast and robust grid current control scheme is required.However, the 2-f voltage ripple also affects the grid side current control loop.Reference [18] illustrates that the current control loop turns to be a nonlinear system when considering the bus voltage ripple.The nonlinear section becomes a harmonics source for the output current.Besides, the current regulator should be selected reasonably.Synchronous frame controllers are originally introduced for three-phase systems, and then extended The DC-AC inverter is controlled by a dual-loop control strategy.The outer loop controls the DC bus voltage by generating the reference current for the inner current loop.The inner controller is aimed to achieve adaptive and accurate current tracking.Conventionally, a proportional-integral (PI) controller is utilized to regulate the bus voltage, but it is hard to address the problem caused by the 2-f ripple.As a consequence, the reference for the output current is distorted, and there is a third harmonic component and a phase shift (which causes reactive current injection) at the grid current [6].According to IEEE standard 929-2000 [7], the current total harmonic distortion (THD) must be limited to less than 5%.In order to ensure the quality of the grid current, the bandwidth of the bus voltage control loop is significantly reduced, which makes the transient response poor.The designer has to use large capacitor or high-voltage power switching devices in case of triggering over the voltage protection or malfunction of the inverter during transients.A solution to reduce the 2-f voltage ripple is to connect the energy storage elements to the bus through an active low-frequency ripple control device (ALFRCD), which injects harmonic current into the DC bus [8,9].This approach solves the problem by essentially eliminating the ripple at the bus voltage, while using a minimal bus capacitor.Nevertheless, it exhibits low efficient, and needs complex hardware and control systems for power applications, which makes the overall system expensive or inefficient.
To suppress the distortion in the output current, a second order infinite impulse response (IIR) notch filter [10] or a high order FIR filter [11] can be introduced into the bus control loop to filter the second harmonic ripple.These methods successfully eliminate the distortion.However, since the notch filter brings about a large negative phase shift at the frequencies lower than the notch frequency, the increase of the bus voltage control loop crossover frequency is limited, and dynamic performance can't be good enough.In [12], a power feedforward control scheme, which is one of direct power control (DPC) schemes, is proposed to reduce the DC bus capacitance requirements and to improve the dynamic response for pulse width modulation (PWM) rectifiers.In order to implement the power feedforward control scheme in two-stage single-phase grid-connected converters, the DC bus input current is required and can be provided by the MPPT controller or extra current sensors.However, various topologies are used for the first stage, such as PV module-integrated DC-DC converters [13], interleaved parallel DC-DC converters [14], multi-string topologies [15] or multiple renewable energy sources [16].At the same time, the DC-AC inverters in distributed generation systems often provide multi-functions such as, energy management for energy storage devices, power sharing for local loads, communication devices, protection units, and the control center [17].Thus, controlling the two stages by separate processors is required to spread the computational load and enhance the flexible of the system, which makes the power feedforward control hard to implement.
The other main task of the inverter is to rapidly follow the reference current signals.Therefore, a fast and robust grid current control scheme is required.However, the 2-f voltage ripple also affects the grid side current control loop.Reference [18] illustrates that the current control loop turns to be a nonlinear system when considering the bus voltage ripple.The nonlinear section becomes a harmonics source for the output current.Besides, the current regulator should be selected reasonably.Synchronous frame controllers are originally introduced for three-phase systems, and then extended to single-phase applications.In single-phase systems, the traditional approach is to create a set of imaginary quantities orthogonal to those of the single-phase system so as to obtain DC quantities by means of a αβ/dq transformation.The orthogonal component is provided by an orthogonal signal generation (OSG) block [19,20].This control method is described as virtual vector control.Although the steady-state performance of the virtual vector control is acceptable, the OSG block makes the controller complicated and hard to analyze the stability.As a result, the implementation of this method for a single-phase grid-connected inverter with an inductor-capacitor-inductor (LCL) filter is difficult.
In this paper, an accurate math model is proposed to analyze the ripple-caused harmonic for PI-based DC bus voltage control loop.A novel DC bus voltage controller is introduced, which is able to improve the transient response of the DC bus voltage control loop significantly.In this method, a second order digital FIR notch filter is implemented to eliminate the distortion in the reference current.At the same time, the input power feedforward control scheme is used to improve the dynamic performance.A DC bus input current estimator using a Kalman filter is established to identify the input current magnitude and to suppress noises without extra hardware.To eliminate the nonlinear section of grid current control system, which is caused by the DC bus voltage ripple, a modulation compensation strategy is also introduced.
Moreover, a novel synchronous frame current controller is proposed for a single-phase grid-connected inverter with an LCL filter.A theoretical analysis method is provided to illustrate its equivalent model in stationary frame.Thanks to the phase-locked loop (PLL), unlike the conventional proportional-resonant (PR) controller in stationary frame, the proposed synchronous frame controller is not sensitive to the grid fundamental frequency variation, while remaining the advantage of zero steady-state error and fast transient response.
This paper is organized as follows: Section 2 provides the analysis of the harmonic distortion caused by DC bus voltage ripple for a conventional control system, Section 3 presents the proposed DC bus voltage controller, the modulation compensation strategy and the novel synchronous frame current control scheme for single phase systems.Section 4 covers the system design and simulation.Section 5 presents experimental results of the proposed control scheme, and Section 6 draws a conclusion.

Bus Voltage Control System
Figure 2a shows the schematic of a single-phase grid-connected inverter with an LCL filter.C bus , L 1 , L 2 , C and R d are the bus capacitor, inverter side inductor, grid side inductor, the capacitor of LCL filter and damping resistor, respectively.i dc and i inv denote the input current and output current of the DC bus.i cbus , i c , i L1 and i g denote the current of C bus , C, L 1 and L 2 , respectively.v inv is the inverter output voltage.
Figure 2b presents a typical control system for the inverter.G c-bus (s) denotes the transfer function of the bus voltage controller, G c-current (s) denotes the transfer function of the inner current controller.The bus voltage controller ensures the bus voltage v bus equal to its reference value V ref .The output of bus voltage controller acts as the reference value for the amplitude of the output current and is called I ref .The signal after multiplication with the PLL signal, which is synchronous and in-phase with the grid voltage v g , generates a reference for the grid current and is denoted by i ref .The current control loop regulates the grid current (i g ) according to the reference (i ref ).Passive or active damping techniques are required to smooth the resonance peak of the LCL filter.
Conventionally, a PI controller is used to regulate the DC bus voltage.A simplified model of the bus voltage control system is presented in Figure 2c, where K pv and K iv are the proportional gain and the integral gain of the bus voltage controller, respectively.The block diagram shows that the bus voltage control loop is not in the form of a linear time invariant (LTI) loop, due to the two multiplications before and after the current control system.The two multiplications introduce time-varying terms into the equations, which lead to the intrinsic nonlinearity of single-phase systems.Generally, the current control loop is designed much faster than the bus voltage controller.Thus, the interaction between the two control loops can be neglected, and the designs of the two loops are done independently.During the analysis of bus voltage control system, we assume that the current control loop is fast and its transients are neglected as compared to the relative slow bus voltage control loop.Based on the assumption, the current control loop is substituted with unity gain.Generally, the current control loop is designed much faster than the bus voltage controller.Thus, the interaction between the two control loops can be neglected, and the designs of the two loops are done independently.During the analysis of bus voltage control system, we assume that the current control loop is fast and its transients are neglected as compared to the relative slow bus voltage control loop.
Based on the assumption, the current control loop is substituted with unity gain.The instantaneous output power of an inverter Pg is calculated as Where Vg is the amplitude of the grid voltage, ωg is the fundamental frequency of grid voltage.Ideally, Iref only contains DC component.Neglecting the possible power losses, the balance of the power relationship is expressed as Pin = Pbus + Pf + Pg.The input power to the bus (Pin) is extracted from the primary source.As a MPPT controller is implemented for the first stage, Pin is controlled to a maximum and constant level at steady state.Pf is the instantaneous power of the inverter output filter.Pbus denotes the instantaneous power of the bus capacitor.The DC bus capacitor is used to decouple the power ripple by providing low-frequency current.As a result, there is a 2-f ripple across the DC bus voltage.
A similar situation exists when three phase grid-connected voltage source converters mean to operate under voltage unbalanced sags produced by grid faults [21].A large power ripple is produced by the existence of negative sequence components in the grid voltage.The injection of negative-sequence currents can be used to suppress the oscillation on the DC bus voltage due to the oscillation of the power injected to the grid.However, when considering the power ripple produced by a large grid connection inductance, the designers face a dilemma whether to compensate the ripple in the power injected to the grid or the ripple in the converter output power.
Pf is neglected in this paper as it is a more general situation.The bus voltage is denoted by vbus.The energy of the bus capacitor is expressed as Ebus = 0.5 × Cbusvbus 2 .Since the bus voltage ripple Δvbus is much smaller than vbus in most situation, this nonlinear term is linearized as follows: The instantaneous output power of an inverter P g is calculated as Where V g is the amplitude of the grid voltage, ω g is the fundamental frequency of grid voltage.Ideally, I ref only contains DC component.Neglecting the possible power losses, the balance of the power relationship is expressed as P in = P bus + P f + P g .The input power to the bus (P in ) is extracted from the primary source.As a MPPT controller is implemented for the first stage, P in is controlled to a maximum and constant level at steady state.P f is the instantaneous power of the inverter output filter.P bus denotes the instantaneous power of the bus capacitor.The DC bus capacitor is used to decouple the power ripple by providing low-frequency current.As a result, there is a 2-f ripple across the DC bus voltage.
A similar situation exists when three phase grid-connected voltage source converters mean to operate under voltage unbalanced sags produced by grid faults [21].A large power ripple is produced by the existence of negative sequence components in the grid voltage.The injection of negative-sequence currents can be used to suppress the oscillation on the DC bus voltage due to the oscillation of the power injected to the grid.However, when considering the power ripple produced by a large grid connection inductance, the designers face a dilemma whether to compensate the ripple in the power injected to the grid or the ripple in the converter output power.
P f is neglected in this paper as it is a more general situation.The bus voltage is denoted by v bus .The energy of the bus capacitor is expressed as E bus = 0.5 × C bus v bus 2 .Since the bus voltage ripple ∆v bus is much smaller than v bus in most situation, this nonlinear term is linearized as follows: Figure 3 describes the formation process of the harmonic distortion.The 2-f ripple in bus voltage causes a same frequency ripple in the amplitude of reference current.After the regulation of the current control loop, the output current is distorted.In order to analyze the distortion, I ref is assumed to include a DC component (a 0 ) and a second harmonic component (a 2 ).θ is the phase angle of the second harmonic.4th and higher order harmonics are neglected in the analysis.I ref is given by: Considering the gain of the bus voltage controller G c-bus (s) at 2ω g , an equation is given as follows: t As derived in the Appendix A, Equations ( 5) and ( 6) are given as follows: where |∆v bus | pp is the peak to peak value of the bus voltage ripple at steady state.The grid current i g is therefore given by ( 7) and ( 8): where I g1 and I g3 are the amplitudes of fundamental component and third harmonic, respectively.ϕ stands for phase angle of the fundamental current.The THD of the gird current is approximately given by: Energies 2017, 10, 389 6 of 30 If a 0 >> a 2 , Equation ( 5) can be simplified as: Energies 2017, 10, 389 6 of 30 If a0 >> a2, Equation ( 5) can be simplified as: To verify the proposed math model, a two-stage single-phase PV system is simulated by using MathWorks MATLAB/Simulink software R2014b.The simulation parameters are described in Section 4. Figure 4 shows the amplitudes of the third harmonic current, which are obtained by using theoretical calculation and simulation.To verify the proposed math model, a two-stage single-phase PV system is simulated by using MathWorks MATLAB/Simulink software R2014b.The simulation parameters are described in Section 4. Figure 4 shows the amplitudes of the third harmonic current, which are obtained by using theoretical calculation and simulation.To verify the proposed math model, a two-stage single-phase PV system is simulated by using MathWorks MATLAB/Simulink software R2014b.The simulation parameters are described in Section 4. Figure 4 shows the amplitudes of the third harmonic current, which are obtained by using theoretical calculation and simulation.The input power of the inverter (P in ) is set as 1 kW.For the left diagram, C bus remains unchanged at 1000 µF.The amplitude of the third harmonic increases significantly with increasing the gain of the bus voltage controller (20log|G c-bus (j2ω g )|).The gain of the bus voltage controller is kept constant as −20 dB for the right diagram.The harmonic distortion decreases with the increasing of the DC bus capacitor.The simulation results match calculated values very well for C bus > 250 µF or 20log|G c-bus (j2ω g )| < −6.The difference between the two approaches is owing to fact that the proposed math model uses approximate value of bus voltage and neglects other harmonic sources.

Grid Current Control System
Similarly, like the bus voltage control system, the DC bus voltage ripple also has a great impact on the grid current control scheme, which is neglected and substituted with unity gain in Section 2.1.To analyze the ripple-caused problems for current control loop, a modified current control scheme, with the consideration of DC-link voltage ripple, is presented in Figure 5a.Where G PWM and G f (s) denote the transfer function of the PWM section and the output filter.Since the bus voltage ripple is time varying, the transfer function of the dashed box in Figure 5a cannot be derived.As pointed in [22], the nonlinear section becomes a harmonic source.However, for the current control scheme, it is very difficult to quantitatively calculate the amplitudes of the harmonics, which are caused by the bus voltage ripple.
In order to explain the process of harmonic generation, a simplified discrete-time mode is presented in Figure 5b.The reference current and the bus voltage ripple are supposed to be pure sinusoidal, i ref (n) = I ref cos(ω g nT s ), ∆v bus (n) = 0.5|∆v bus | pp × cos(2ω g nT s ).The output current i g (n) is created by multiplying the error signal err(n) by the bus voltage v bus (n).For multiplication in the time domain is equivalent to convolution in the frequency domain, the current harmonics are regarded as a convolution of error signals and the ripple signals.By filtering the 5th order harmonic from the feedback signal, a closed-form solution to calculate the amplitudes of the ripple-caused harmonics is proposed in [22].Nevertheless, the math model cannot be accurate for neglecting the gain variations of the current controller and output filter at different frequency stage, especially when a PR controller is implemented as the current controller.
Energies 2017, 10, 389 7 of 30 20log|Gc-bus(j2ωg)| < −6.The difference between the two approaches is owing to fact that the proposed math model uses approximate value of bus voltage and neglects other harmonic sources.

Grid Current Control System
Similarly, like the bus voltage control system, the DC bus voltage ripple also has a great impact on the grid current control scheme, which is neglected and substituted with unity gain in Section 2.1.To analyze the ripple-caused problems for current control loop, a modified current control scheme, with the consideration of DC-link voltage ripple, is presented in Figure 5a.Where GPWM and Gf(s) denote the transfer function of the PWM section and the output filter.Since the bus voltage ripple is time varying, the transfer function of the dashed box in Figure 5a cannot be derived.As pointed in [22], the nonlinear section becomes a harmonic source.However, for the current control scheme, it is very difficult to quantitatively calculate the amplitudes of the harmonics, which are caused by the bus voltage ripple.
In order to explain the process of harmonic generation, a simplified discrete-time mode is presented in Figure 5b.The reference current and the bus voltage ripple are supposed to be pure sinusoidal, iref(n) = Irefcos(ωgnTs), Δvbus(n) = 0.5|Δvbus|pp × cos(2ωgnTs).The output current ig(n) is created by multiplying the error signal err(n) by the bus voltage vbus(n).For multiplication in the time domain is equivalent to convolution in the frequency domain, the current harmonics are regarded as a convolution of error signals and the ripple signals.By filtering the 5th order harmonic from the feedback signal, a closed-form solution to calculate the amplitudes of the ripple-caused harmonics is proposed in [22].Nevertheless, the math model cannot be accurate for neglecting the gain variations of the current controller and output filter at different frequency stage, especially when a PR controller is implemented as the current controller.The PR controller is given by (11).Where Kp-pr and Kr-pr are the proportion gain and resonant gain of the controller, respectively.If a PR controller is used to regulate the grid current, its resonance frequency is in alignment with the fundamental frequency.The PR controllers present different gains at the fundamental frequency and other frequencies [23], which makes the calculation of the ripple-caused harmonic too complicated to be procurable:

G c-current (s)
From the aforementioned analysis, conclusions can be shown as follows: (1) The 2-f voltage ripple leads to a third harmonic component and a phase shift in the output current.In a similar way, 4-f power pulsation leads to 5th order harmonic current, and so on.(2) There is a negative correlation between the harmonic distortion (Ig3) and the bus capacitor value (Cbus).Larger capacitance leads to lower harmonic content, but increases the cost, size and weight of the converter.The PR controller is given by (11).Where K p-pr and K r-pr are the proportion gain and resonant gain of the controller, respectively.If a PR controller is used to regulate the grid current, its resonance frequency is in alignment with the fundamental frequency.The PR controllers present different gains at the fundamental frequency and other frequencies [23], which makes the calculation of the ripple-caused harmonic too complicated to be procurable: From the aforementioned analysis, conclusions can be shown as follows: (1) The 2-f voltage ripple leads to a third harmonic component and a phase shift in the output current.In a similar way, 4-f power pulsation leads to 5th order harmonic current, and so on.
(2) There is a negative correlation between the harmonic distortion (I g3 ) and the bus capacitor value (C bus ).Larger capacitance leads to lower harmonic content, but increases the cost, size and weight of the converter.(3) There is a positive correlation between the harmonic distortion and the gain of the bus voltage controller (|G c-bus (j2ω g )|).With a lower gain, there is less distortion in the grid current.However, a low gain may lead to poor transient response or to instability, two properties that are affected by one main parameter, the loop bandwidth.The bus voltage control loop presents a tradeoff between harmonic distortion and bandwidth, which is controlled by the gain of the controller.Thus, a simple PI controller, which is used as bus voltage controller, is unable to address the ripple-caused difficulties.(4) The 2-f bus voltage ripple also brings about a nonlinear section in the grid current control scheme, which makes contributions to the increase in harmonic component.

Proposed Control Scheme
To minimize the DC bus capacitor, the oscillation on the DC bus should be tolerated.Correspondingly, the control system should have the ability to suppress the ripple-caused distortion.This section introduces the proposed controller, which can achieve excellent steady-state and dynamic performances.
First of all, a second order FIR notch filter is introduced to bus voltage regulator with the purpose of filtering the double frequency ripple.The design of a bus control system including the second order FIR notch filter is discussed.The bus voltage control system is simplified as an approximate linear model.Based on the model, the stability analysis and parameters design for the bus voltage control loop can be carried out.To further improve dynamic response to input transient, an input current estimator using Kalman filter is also established to implement the input power feedforward.
Improvements for the current control loop are also presented in this section.As discussed in Section 2, the ripple-caused nonlinearity, in the grid current control scheme, becomes a harmonic source.To eliminate the nonlinearity, a modulation compensation strategy is proposed.With the implement of this strategy, the current control loop is linearized.The harmonic distortion is reduced, correspondingly.Moreover, a novel synchronous frame scheme is proposed to achieve high performance current tracking for the single-phase grid-connected systems.

FIR Notch Filter Inserted Bus Voltage Regulator
As described in Section 2.1, decreasing the gain of the bus voltage controller at 2ω g can reduce the harmonic distortion.Using a second order FIR notch filter, which is tuned at 2-f harmonic, in the bus control loop prevents the 2-f harmonic from polluting the reference current.By filtering the 2-f voltage ripple, the notch filter rejects both the third harmonic and the phase shift to the fundamental current.Moreover, since the grid voltage and grid current may contain undesired harmonic components, 4th and 6th order harmonic ripple components could be found in the DC bus voltage.Therefore, extra FIR notch filters, which are tuned at the 4th and 6th order harmonics, are also needed in some cases.
Since the bus voltage control loop is not linear and not time invariant, it is a great challenge to analyze the stability and dynamic response of the loop.Instead of using the direct and complex feedback signals, the control system is simplified in terms of the average signals.The advantage of the averaged signals method is that it leads to a linear and time invariant model.By averaging instantaneous signals over half of a line cycle ( 12) and ( 13), the average signals do not contain second harmonic components.They interact through operators that may be approximated as linear and time invariant [11].The average DC bus voltage is given as (12).v bus (t) only contains DC component at steady state.We also assume that the harmonic distortion is blocked by the controller, and only fundamental component in the grid current.Therefore, the average output power P g (t) is written as (13): where I g (t) is the peak value of fundamental grid current.I g (t) is also assumed be equal to the output of the bus voltage controller (I ref ).Since the second order ripple in the output power (P g = 0.5 × V g I g + 0.5 × V g I g cos(2ω g t)) is neglected, a constant gain 0.5 × V g is used to describe the relationship between I g (t) and P g (t).Thus, an approximate linear model of the bus voltage control system is obtained.Figure 6a gives the control block diagram of the FIR notch filter inserted bus voltage regulator (G c-bus (z)), which is comprised of an FIR notch filter (G NF (z)) and a loop compensator (H c (z)).
Energies 2017, 10, 389 9 of 30 where Ig(t) is the peak value of fundamental grid current.Ig(t) is also assumed be equal to the output of the bus voltage controller (Iref).Since the second order ripple in the output power (Pg = 0.5 × VgIg + 0.5 × VgIg cos(2ωgt)) is neglected, a constant gain 0.5 × Vg is used to describe the relationship between Ig(t) and Pg(t).Thus, an approximate linear model of the bus voltage control system is obtained.Figure 6a gives the control block diagram of the FIR notch filter inserted bus voltage regulator (Gc-bus(z)), which is comprised of an FIR notch filter (GNF(z)) and a loop compensator (Hc(z)).Unlike the high order FIR filter used in [11], the second order FIR has a simpler transfer function as follows: The second order FIR notch filter has been successful in the removal of power-line noise from biomedical signals.The major advantage of the FIR notch filter is its simplicity of the pole-zero placement on the unit circle method.The zeroes of the filter are placed on the unit circle at the position equivalent to the rejected frequency ωf.For a signal sampled at the frequency ωs, the zeroes are determined as z1,2 [24].BW is the bandwidth at −3 dB cutoff frequency of the notch filter, which Unlike the high order FIR filter used in [11], the second order FIR has a simpler transfer function as follows: The second order FIR notch filter has been successful in the removal of power-line noise from biomedical signals.The major advantage of the FIR notch filter is its simplicity of the pole-zero placement on the unit circle method.The zeroes of the filter are placed on the unit circle at the position Energies 2017, 10, 389 equivalent to the rejected frequency ω f .For a signal sampled at the frequency ω s , the zeroes are determined as z 1,2 [24].BW is the bandwidth at −3 dB cutoff frequency of the notch filter, which reduces the sensitivity of the grid fundamental frequency variation.BW and the quality factor (Q), which are also given by (15), determine the sharpness of the notch filter.
Figure 7 presents the bode diagrams of the second order FIR notch filters with different sampling frequencies.The filter is manifested as almost unity gain at low frequencies and a notch at the rejected frequency ω f .However, one thing needs to be noticed is that the magnitude of the filter at the high frequency (higher than ω f ) trends to increase when a high sampling rate is adopted.Typically, the bus voltage control loop is much slower than the current loop and the interactions between the two loops are neglected, thus, the two control loops can be designed independently.Correspondingly, we use different sampling rates for the two controllers.Unlike the current controller, a relative low sampling rate is enough for bus voltage controller in most applications.In order to filter the unnecessary high frequency noises, the bus voltage control system is operating at a low sampling rate, which makes the design of FIR notch filter and the loop compensator simpler.
Energies 2017, 10, 389 10 of 30 reduces the sensitivity of the grid fundamental frequency variation.BW and the quality factor (Q), which are also given by ( 15), determine the sharpness of the notch filter.Figure 7 presents the bode diagrams of the second order FIR notch filters with different sampling frequencies.The filter is manifested as almost unity gain at low frequencies and a notch at the rejected frequency ωf.However, one thing needs to be noticed is that the magnitude of the filter at the high frequency (higher than ωf) trends to increase when a high sampling rate is adopted.Typically, the bus voltage control loop is much slower than the current loop and the interactions between the two loops are neglected, thus, the two control loops can be designed independently.Correspondingly, we use different sampling rates for the two controllers.Unlike the current controller, a relative low sampling rate is enough for bus voltage controller in most applications.In order to filter the unnecessary high frequency noises, the bus voltage control system is operating at a low sampling rate, which makes the design of FIR notch filter and the loop compensator simpler.To achieve zero steady-state error during a step-up of the injected power, a discrete PI controller is employed as the compensator: where Kp is the proportional gain, Ki is the integral gain, Ts is the sampling period.Therefore, the modified controller is given by Gc-bus(z) = GNF(z)Hc(z), which has two design parameters Kp and Ki.
According to Figure 6a, the open loop transfer function for bus voltage control loop can be obtained as (17).Thus, designing the loop compensator by using the frequency response method is possible: The above analysis is based on several assumptions.Firstly, the current control loop is fast and robust.Secondly, the interactions between the bus voltage control loop and the current control loop are neglected.Thirdly, the bus voltage control loop is simplified in terms of the average signals to ignore the nonlinearity.However, these assumptions are violated when try to further increase the speed of bus voltage control loop.Since a more accurate math model is hard to establish, the practical approach is to limit the bus voltage control loop bandwidth to a suitable range so as to ensure the stability of the system and decrease the bus voltage fluctuations.To achieve zero steady-state error during a step-up of the injected power, a discrete PI controller is employed as the compensator: where K p is the proportional gain, K i is the integral gain, T s is the sampling period.Therefore, the modified controller is given by G c-bus (z) = G NF (z)H c (z), which has two design parameters K p and K i .According to Figure 6a, the open loop transfer function for bus voltage control loop can be obtained as (17).Thus, designing the loop compensator by using the frequency response method is possible: The above analysis is based on several assumptions.Firstly, the current control loop is fast and robust.Secondly, the interactions between the bus voltage control loop and the current control loop are neglected.Thirdly, the bus voltage control loop is simplified in terms of the average signals to ignore the nonlinearity.However, these assumptions are violated when try to further increase the speed of bus voltage control loop.Since a more accurate math model is hard to establish, the practical approach is to limit the bus voltage control loop bandwidth to a suitable range so as to ensure the stability of the system and decrease the bus voltage fluctuations.

Kalman-Filter-Based Input Power Feedforward
The input power feedforward control scheme is used to reduce capacitance energy storage requirements and to improve the dynamic response of the system.If the input power can be calculated in real time, the dynamic response to input transients can be improved to satisfy the wide range input change.Figure 6b shows the bus voltage control system with the input power feedforward scheme in continuous time domain.Considering the power loss, a factor k (0 < k < 1) is used to adjust the ratio of feedforward power.By moving the feedforward node of the input power P in (t) from the input of the bus voltage controller G c-bus (s) to the output, an equivalent model is given as Figure 6c.
Due to the lack of direct power measuring methods, a DC bus input current estimator offers an alternative solution for the implement of input power feedforward control scheme.A full order observer, which is based on volt ampere relation of the DC bus capacitor, is proposed to reduce the 2-f ripple in the DC bus voltage for a regenerative cascade inverter [25].However, the full order observer is very sensitive to the random measuring noise, which leads to a poor performance in real system.The Kalman filter is an optimal state estimator and is usually applied to a dynamic system that involves random noise environment.Thus, it is the suitable choice to detect the DC bus instantaneous input current under the measuring noise.In order to implement the design results into practical digital control systems, the design is directly carried out in discrete domain.The discrete domain system model is shown as below: where state vector T ; w k is the system noise, Γ k is the noise matrix, v k is the measuring noise; i dc (k) and i inv (k) are the input and output current of the DC bus in discrete time.The volt ampere relation of the DC bus capacitor is given as: The Kalman filter process for this system is given as follows [26]: where P k/k is the estimated variance matrix; K k is Kalman gain matrix; Q k is the variance matrix of the system noise vector; R k is the variance matrix of the measurement noise vector; Q k and R k are positive definite matrix.The initial estimated variance matrix P 0 and the initial estimated state x0 do not destroy the stability of Kalman filter.However, P 0 and x0 should be set carefully in case of the overflow in calculating P k or xk , which is conducted by a finite-word-length microcontroller unit (MCU).x0 is set according to the system state, and P k is limited to a suitable range.Arithmetic operations in MCU result in rounding errors, which perhaps cause that P k becomes a negative definite matrix and Kalman filter diverges.Thus, a modified P k (i, j) is used to simplify the calculation and to ensure the symmetry of the matrix: The inverter side current i inv (k) is calculated as follows: The inverter output voltage (v inv (k)) and the inverter side conductor current (i L1 (k)) are provided by the grid current control scheme.A proper R is used to smooth îdc , so as to neglect measuring noises and fast oscillations at the input power.Since P in is a constant (P in = v bus × i dc ) and v bus includes a 2-f ripple at steady-state, there will also be a slight 2-f ripple in the i dc .The estimated current îdc lags the actual current i dc , therefore, P in can't be achieved by multiplying v bus by îdc .To gain clean reference current signal, V ref instead of v bus is used as the multiplier to calculate the input power, and the feedforward term is also filtered by the FIR notch filter.Finally, Figure 6d presents the control block diagram of the proposed FIR notch filter inserted bus voltage regulator with the Kalman-filter-based input power feedforward scheme.

Modulation Compensation Strategy for Bus Voltage Ripple
To eliminate the nonlinearity of the current control loop, which is caused by the DC bus voltage ripple, a modulation compensation strategy is proposed in this section.As depicted in Figure 8a, this method simply inserts a term G cmp before the PWM section.When the bus voltage ripple increases, the compensator decreases the modulation index proportionally.As a result, the ripple-caused nonlinearity in the current control scheme is compensated: With implementing the modulation compensation strategy, an equivalent control model is shown in Figure 8b.By replacing modulator gain v bus with V ref , the current control system is completely linearized.
Energies 2017, 10, 389 12 of 30 The inverter side current iinv(k) is calculated as follows: The inverter output voltage (vinv(k)) and the inverter side conductor current (iL1(k)) are provided by the grid current control scheme.A proper R is used to smooth ˆdc i , so as to neglect measuring noises and fast oscillations at the input power.Since Pin is a constant (Pin = vbus × idc) and vbus includes a 2-f ripple at steady-state, there will also be a slight 2-f ripple in the idc.The estimated current ˆdc i lags the actual current idc, therefore, Pin can't be achieved by multiplying vbus by ˆdc i .To gain clean reference current signal, Vref instead of vbus is used as the multiplier to calculate the input power, and the feedforward term is also filtered by the FIR notch filter.Finally, Figure 6d presents the control block diagram of the proposed FIR notch filter inserted bus voltage regulator with the Kalman-filterbased input power feedforward scheme.

Modulation Compensation Strategy for Bus Voltage Ripple
To eliminate the nonlinearity of the current control loop, which is caused by the DC bus voltage ripple, a modulation compensation strategy is proposed in this section.As depicted in Figure 8a, this method simply inserts a term Gcmp before the PWM section.When the bus voltage ripple increases, the compensator decreases the modulation index proportionally.As a result, the ripple-caused nonlinearity in the current control scheme is compensated: With implementing the modulation compensation strategy, an equivalent control model is shown in Figure 8b.By replacing modulator gain vbus with Vref, the current control system is completely linearized.

Novel Synchronous Frame Current Control Scheme for Single-Phase Systems
In order to pursuit precise current tracking and high power quality, a fast and robust current control loop is required.Two common methods for current regulation of single phase grid-connected inverters are: (1) using PR controllers in stationary reference frame; and (2) using virtual vector control in synchronous reference frame.
Figure 9a presents the block diagrams of virtual vector control for current-regulated singlephase grid-connected inverters.Where id * and iq * , are the active and reactive reference current; iα and iβ are the feedback current in stationary frame; vd, vq, vα and vβ are output of controller in synchronous and stationary frame.An orthogonal current (iβ) is created to obtain DC quantities by means of a αβ/dq transformation.Thus, the PI controllers can be adopted to regulate the dq current, which present infinite control gain at the steady-state operating point and lead to zero steady-state error.In Figure 9, vα is fed into the PWM modulator, while vβ is discarded.Since the system variables are converted to DC quantities, the control loop has no dependence on the system frequency.The generation of iβ is described by an equivalent transfer function O(s) [27], in which iα is shifted 90°.By inserting two opposite frame transformations into Figure 9a, an equivalent block diagram is

Novel Synchronous Frame Current Control Scheme for Single-Phase Systems
In order to pursuit precise current tracking and high power quality, a fast and robust current control loop is required.Two common methods for current regulation of single phase grid-connected inverters are: (1) using PR controllers in stationary reference frame; and (2) using virtual vector control in synchronous reference frame.
Figure 9a presents the block diagrams of virtual vector control for current-regulated single-phase grid-connected inverters.Where i d * and i q * , are the active and reactive reference current; i α and i β are the feedback current in stationary frame; v d , v q , v α and v β are output of controller in synchronous and stationary frame.An orthogonal current (i β ) is created to obtain DC quantities by means of a αβ/dq transformation.Thus, the PI controllers can be adopted to regulate the dq current, which present infinite control gain at the steady-state operating point and lead to zero steady-state error.In Figure 9, v α is fed into the PWM modulator, while v β is discarded.Since the system variables are converted to DC quantities, the control loop has no dependence on the system frequency.The generation of i β is described by an equivalent transfer function O(s) [27], in which i α is shifted 90 • .By inserting two opposite frame transformations into Figure 9a, an equivalent block diagram is presented in Figure 9b.Where e α and e β are the error signals in stationary frame.Hilbert transform [28], fictive axis emulator [29], time delay [30], all pass filter [31] and second-order generalized integrator [32] are conventional OSG methods.Table 1 lists some OSG methods and the corresponding O(s).Where T 0 and ω 0 are the fundamental period and fundamental frequency.Although these methods provide satisfactory performance at steady-state, they suffer from several drawbacks.The delay to create orthogonal component slows down the system dynamic response.Frequency drifts result in an inaccurate phase shift, which leads to errors in active and reactive power control.Moreover, the OSG block makes the current controller complicated and difficult to analyze the stability.The influence, which is brought about by the interaction between α-axis component and β-axis component, is hard to analyze.Thus, the virtual vector control is seldom implemented for an inverter with an LCL filter.

Method Transfer Function
Time delay e −T 0 s 4 All pass filter Second-order generalized integrator presented in Figure 9b.Where eα and eβ are the error signals in stationary frame.Hilbert transform [28], fictive axis emulator [29], time delay [30], all pass filter [31] and second-order generalized integrator [32] are conventional OSG methods.Table 1 lists some OSG methods and the corresponding O(s).Where T0 and ω0 are the fundamental period and fundamental frequency.Although these methods provide satisfactory performance at steady-state, they suffer from several drawbacks.The delay to create orthogonal component slows down the system dynamic response.Frequency drifts result in an inaccurate phase shift, which leads to errors in active and reactive power control.Moreover, the OSG block makes the current controller complicated and difficult to analyze the stability.The influence, which is brought about by the interaction between α-axis component and β-axis component, is hard to analyze.Thus, the virtual vector control is seldom implemented for an inverter with an LCL filter.A droop-Lyapunov-based control technique is proposed for single-phase converters in [33,34].The control system is designed with respect to the accurate dynamic model of inverter developed in the d-q rotating frame.A capability curve for the entire operating condition is used to define the positive and negative maximum values for the d-q components of inverter currents.Excellent performance can be achieved for both stand-alone operating mode and grid-connected operating mode in the presence of nonlinear loads.However, precise circuit parameters are needed by the controller, which makes it challenging to apply the control strategy in practical system.
A novel synchronous frame current controller is proposed in this section.This method cancels the OSG block by assuming that the error signal eβ is equal to zero. Figure 10a presents the block diagram of the proposed control scheme.Using the math model described in [35], the equivalent transfer function in stationary reference frame for the dashed box in Figure 10a is derived as follows.A droop-Lyapunov-based control technique is proposed for single-phase converters in [33,34].The control system is designed with respect to the accurate dynamic model of inverter developed in the d-q rotating frame.A capability curve for the entire operating condition is used to define the positive and negative maximum values for the d-q components of inverter currents.Excellent performance can be achieved for both stand-alone operating mode and grid-connected operating mode in the presence of nonlinear loads.However, precise circuit parameters are needed by the controller, which makes it challenging to apply the control strategy in practical system.
A novel synchronous frame current controller is proposed in this section.This method cancels the OSG block by assuming that the error signal e β is equal to zero. Figure 10a presents the block diagram of the proposed control scheme.Using the math model described in [35], the equivalent transfer function in stationary reference frame for the dashed box in Figure 10a is derived as follows.The equivalent model of proportional controller and integral controller are separately established to analyze their performance in all frequencies.Then, the equivalent model, in stationary frame, for the proposed controller is obtained by summing them up.According to Fourier's theorem, the feedback error signals can be given as: where E is the amplitude of the error signal, and φ is the initial phase angle.nω0 represents the angle frequency of the signal.n can be an integer or a decimal (n ≥ 0).If n is equal to zero, it means the input signals is DC component.Therefore, all possible input error signals in different frequencies are under consideration.The transformation from the stationary to the synchronous frame for an arbitrary quantity is given by: Since Kp is a constant, the proportion controller in synchronous frame is the same as the proportion controller in stationary frame: The integral controller in synchronous frame is given by: Signals represented in time domain is: Substituting ( 24) and ( 25) into ( 26), the output signals of controller are given by: The equivalent model of proportional controller and integral controller are separately established to analyze their performance in all frequencies.Then, the equivalent model, in stationary frame, for the proposed controller is obtained by summing them up.According to Fourier's theorem, the feedback error signals can be given as: where E is the amplitude of the error signal, and ϕ is the initial phase angle.nω 0 represents the angle frequency of the signal.n can be an integer or a decimal (n ≥ 0).If n is equal to zero, it means the input signals is DC component.Therefore, all possible input error signals in different frequencies are under consideration.The transformation from the stationary to the synchronous frame for an arbitrary quantity is given by: Since K p is a constant, the proportion controller in synchronous frame is the same as the proportion controller in stationary frame: The integral controller in synchronous frame is given by: Energies 2017, 10, 389 15 of 30 Signals represented in time domain is: Substituting ( 24) and ( 25) into ( 26), the output signals of controller are given by: t cos(ϕ) cos(ω 0 t) − t sin(ϕ) sin(ω 0 t) + sin(ω 0 t) cos(ϕ)+cos(ω 0 t) sin(ϕ) 2ω 0 t cos(ϕ) sin(ω 0 t) + t sin(ϕ) cos(ω 0 t) + cos(ω 0 t+ϕ) − cos(nω 0 t+ϕ) ω 0 (n−1)(n+1) , n = 1 (29) Considering the error signal presented in (24), the relationship between the input and the output signals can be obtained.G I-eq (s) is the equivalent transfer function in stationary frame for the integral controller in synchronous frame.When n = 1: s cos(ϕ)−sin(ϕ)ω 0 (30) Substituting s by jω 0 , Equations ( 31) and ( 32) are obtained.Where e is the Euler's number: G I-eq (s) When n = 1, substituting nω 0 by ω: Substituting s by jω: Obviously, no matter whether n is equal to 1 or not, the gain of controller |G I-eq (s)| is From (29), phase relationship between the input and output signal can be summarized as that the output signal leads the input by 90 • for 0 ≤ n < 1 and lags the input by 90 • for n > 1.Thus, the integral controller in synchronous frame is equal to resonant controller in stationary frame.
A PI controller is regarded as the sum of a proportional controller and an integral controller.Therefore, from the above analysis, the proposed synchronous frame controller G c (s) is equivalent to a proportion-resonant controller in stationary frame as (35).
Figure 11a presents Bode diagrams for a PR controller and a resonant controller.Since the resonant term provides very little gain outside the band-pass, an improved PR controller is given by (36) to reduce sensitivity to variations in the interfaced-grid frequency [23].Where ω c is the bandwidth Energies 2017, 10, 389 16 of 30 at −3 dB cutoff frequency of the resonant controller.The presence of ω c seems to allow a degree of freedom in the design of the resonant frequency response.However, as depicted in Figure 11b, increasing ω c only decreases the peak amplitude of the resonant term at resonant frequency, without affecting the gain at other frequency stage.If there is a variation in reference frequency, a larger resonant gain K r-pr is required to ensure the performance of the controller.According to the PV power grid code in the China, the PV grid-connected inverters should run smoothly across a wide grid frequency range from 48 Hz to 50.5 Hz [36].K r-pr is too large to be unprocurable for such a large frequency variation.In [37], the grid frequency estimated by the PLL is used to adjust the parameters of the PR controller in real time, so as to eliminate difference between the grid frequency and resonant frequency.This control strategy is descripted as the frequency adaptive PR controller.Since the resonant frequency of proposed synchronous frame controller is always in alignment with grid fundamental frequency, a similar control performance as the frequency adaptive PR controller can be achieved by using a simpler approach: Energies 2017, 10, 389 16 of 30 Figure 11a presents Bode diagrams for a PR controller and a resonant controller.Since the resonant term provides very little gain outside the band-pass, an improved PR controller is given by (36) to reduce sensitivity to variations in the interfaced-grid frequency [23].Where ωc is the bandwidth at −3 dB cutoff frequency of the resonant controller.The presence of ωc seems to allow a degree of freedom in the design of the resonant frequency response.However, as depicted in Figure 11b, increasing ωc only decreases the peak amplitude of the resonant term at resonant frequency, without affecting the gain at other frequency stage.If there is a variation in reference frequency, a larger resonant gain Kr-pr is required to ensure the performance of the controller.According to the PV power grid code in the China, the PV grid-connected inverters should run smoothly across a wide grid frequency range from 48 Hz to 50.5 Hz [36].Kr-pr is too large to be unprocurable for such a large frequency variation.In [37], the grid frequency estimated by the PLL is used to adjust the parameters of the PR controller in real time, so as to eliminate difference between the grid frequency and resonant frequency.This control strategy is descripted as the frequency adaptive PR controller.Since the resonant frequency of proposed synchronous frame controller is always in alignment with grid fundamental frequency, a similar control performance as the frequency adaptive PR controller can be achieved by using a simpler approach: As pointed in [35], for a three-phase system, the PI controller in synchronous frame is equivalent to PR controller in stationary frame at fundamental frequency, which has a transfer function as (37).Except for the fundamental frequency, they are not equivalent, and their amplitude characteristics differ greatly in low frequency stage.However, the proposed synchronous frame controller is equivalent to PR controller in stationary frame for all frequency.According to ( 35) and ( 37), the equivalent resonant gain of the proposed controller is only half as high as the one of three-phase system, which is owing to the lack of iβ: As pointed in [35], for a three-phase system, the PI controller in synchronous frame is equivalent to PR controller in stationary frame at fundamental frequency, which has a transfer function as (37).Except for the fundamental frequency, they are not equivalent, and their amplitude characteristics differ greatly in low frequency stage.However, the proposed synchronous frame controller is equivalent to PR controller in stationary frame for all frequency.According to (35) and (37), the equivalent resonant gain of the proposed controller is only half as high as the one of three-phase system, which is owing to the lack of i β : The implementation of the proposed current controller for a single-phase grid-connected inverter with an LCL filter is possible.Figure 10b shows the corresponding control block diagrams.The capacitor current feedback (CCF) active damping method is chosen due to its effective damping performance and simple application [38].A PR controller, instead of the proposed controller, is used to analyze the system stability.The equivalent control block diagrams are presented in Figure 10c, in which the symbols are adjusted in order to be consistent with context above.A delay of λT s (T s is the sampling period, 0 ≤ λ ≤ 1), which is caused by the digitally controlled system, is also included in the control block diagrams [39].Usually, the delay of the PWM module is equal to one sampling period T s (λ = 1).However, by shifting the sampling instant towards the PWM reference update instant, λ can also be a decimal.λT is mainly consist of the analog-to-digital conversion delay and the computation delay.
The PWM is usually modeled as a zero order hold (ZOH), that is: Thus, the delay time of the PWM is equal to 0.5T s , and the total delay time is (λ + 0.5)T s .The time delays have a great influence on the stability of digitally controlled grid-connected inverters with LCL filters.To tune the feedback coefficient K d , an accurate model is presented in Figure 12.
Energies 2017, 10, 389 17 of 30 The implementation of the proposed current controller for a single-phase grid-connected inverter with an LCL filter is possible.Figure 10b shows the corresponding control block diagrams.The capacitor current feedback (CCF) active damping method is chosen due to its effective damping performance and simple application [38].A PR controller, instead of the proposed controller, is used to analyze the system stability.The equivalent control block diagrams are presented in Figure 10c, in which the symbols are adjusted in order to be consistent with context above.A delay of λTs (Ts is the sampling period, 0 ≤ λ ≤ 1), which is caused by the digitally controlled system, is also included in the control block diagrams [39].Usually, the delay of the PWM module is equal to one sampling period Ts (λ = 1).However, by shifting the sampling instant towards the PWM reference update instant, λ can also be a decimal.λTs is mainly consist of the analog-to-digital conversion delay and the computation delay.
The PWM is usually modeled as a zero order hold (ZOH), that is: Thus, the delay time of the PWM is equal to 0.5Ts, and the total delay time is (λ + 0.5)Ts.The time delays have a great influence on the stability of digitally controlled grid-connected inverters with LCL filters.To tune the feedback coefficient Kd, an accurate model is presented in Figure 12.

G1(s) is the transfer function from vinv(s) to ic(s). G2(s) is the transfer function from vinv(s) to ig(s).
G1(s) and G2(s) are given as follows: Applying Z-transform to G1(s) with ZOH, the open-loop transfer function of the inner active damping loop is given by: in (42) can be obtained using the following property [40]: G 1 (s) is the transfer function from v inv (s) to i c (s). G 2 (s) is the transfer function from v inv (s) to i g (s).G 1 (s) and G 2 (s) are given as follows: Applying Z-transform to G 1 (s) with ZOH, the open-loop transfer function of the inner active damping loop is given by: where m = 1 − λ, 0 ≤ m ≤ 1. Z{ G 1 (s) s e mT s s } in (42) can be obtained using the following property [40]: Res zG 1 (s)e mT s s s(z − e T s s ) s=pi (43) where pi (i = 1, 2, ..., n) are the poles of G 1 (s)/s and Res denotes the residue.Thus, (42) can be simplified as: The closed-loop transfer function of the inner active damping loop is expressed as:

System Design
To validate the feasibility of the proposed control scheme, a two-stage single-phase grid-connected PV system has been constructed.As depicted in Figure 13, it consists of two boost converters and a simple full bridge on the second stage.The two boost converters in the first stage have two operation modes.Firstly, they can be connected to different PV arrays and work independently, which enables the circuit to extract the maximum available power from each array independently for partially shaded conditions.Secondly, they can work as a two-phase interleaved boost converter, which is adopted in this paper.Both simulation and experimental tests have been carried out with the parameters given in Table 2.
Energies 2017, 10, 389 18 of 30 ( ) where pi (i = 1, 2, ..., n) are the poles of G1(s)/s and Res denotes the residue.Thus, (42) can be simplified as: The closed-loop transfer function of the inner active damping loop is expressed as:

System Design
To validate the feasibility of the proposed control scheme, a two-stage single-phase grid-connected PV system has been constructed.As depicted in Figure 13, it consists of two boost converters and a simple full bridge on the second stage.The two boost converters in the first stage have two operation modes.Firstly, they can be connected to different PV arrays and work independently, which enables the circuit to extract the maximum available power from each array independently for partially shaded conditions.Secondly, they can work as a two-phase interleaved boost converter, which is adopted in this paper.Both simulation and experimental tests have been carried out with the parameters given in Table 2.For the FIR notch filter inserted bus voltage regulator, the sampling frequency is 400 Hz.The set of gains are K p = 0.17, K i = 5.3.The FIR notch filter is given as G NF (z) = 0.5(1 + z −2 ).By substituting the system parameters shown in Table 2 into  For the FIR notch filter inserted bus voltage regulator, the sampling frequency is 400 Hz.The set of gains are Kp = 0.17, Ki = 5.3.The FIR notch filter is given as GNF(z) = 0.5(1 + z −2 ).By substituting the system parameters shown in Table 2 into  The input power feedforward factor k is equal to 0.9.For the Kalman filter, it is very important to determine the values of the Q and R. The value of Q is determined from the noises generated by the PWM inverter and the DC-bus capacitor.The major sources of noise from the PWM inverter come from the current controller.The current controller is not perfect due to the current ripple and the current measuring error.The capacity of the DC bus capacitor may be not equal to its nominal value.The value of R is determined from the noises generated by the DC bus voltage measuring error and fast oscillations at the input power.Unfortunately, the levels of these noises are not exactly known.So the values are mainly determined from the experimental system and should be adjusted by experiment.Thus, it requires some trial-and-errors.
To analyze the influence of different time delays, the grid current control systems are categorized as three typical cases [41], in which the delay time is 0.5Ts, Ts, 1.5Ts, respectively.Correspondingly, the PWM module of the MCU is configured in shadow mode with double update, and the sampling instant and duty-ratio update instant are placed at the peak and valley the triangle carrier.The values of m are 1, 0.5 and 0. When m = 1, there is no computation delay, which is unprocurable for practical system.The root loci of the active damping closed-loop transfer function Ga-cl(z) are illustrated in Figure 15.For Figure 15a, m is equal to 0.5.With the increase of Kd, a couple of poles move from the boundary of the unit circle into the inside, meaning that the system stability is improved.However, when Kd goes beyond 0.1, they move outside the unit circle, and the system becomes unstable.For Figure 15b, m is equal to 0. There is a couple of poles located outside the unit circle, indicating that the system is definitely unstable.Obviously, the time delays affect the system significantly, and a large delay time will destroy the stability of the CCF active damping loop.
For the current controller, the sampling frequency is equal to the PWM switch frequency.To simplify the design procedure, m = 0.5 is adopted in this paper.The grid current ig and capacitor current ic are sampled at the peak of the PWM carrier, and the PWM reference is updated at the valley.In other words, the analog-to-digital conversion delay and the computation delay should not exceed 0.5Ts.Luckily, 50 μs is enough for a fast digital processor to achieve the control process.The design of the PR regulator as current controller is widely discussed, so as to it is not included in this paper [23].With the compromise of the system stability and resonant damping, Kp-pr, Kr-pr, and Kd are set as 0.026, 20, 0.03, respectively.The input power feedforward factor k is equal to 0.9.For the Kalman filter, it is very important to determine the values of the Q and R. The value of Q is determined from the noises generated by the PWM inverter and the DC-bus capacitor.The major sources of noise from the PWM inverter come from the current controller.The current controller is not perfect due to the current ripple and the current measuring error.The capacity of the DC bus capacitor may be not equal to its nominal value.The value of R is determined from the noises generated by the DC bus voltage measuring error and fast oscillations at the input power.Unfortunately, the levels of these noises are not exactly known.So the values are mainly determined from the experimental system and should be adjusted by experiment.Thus, it requires some trial-and-errors.
To analyze the influence of different time delays, the grid current control systems are categorized as three typical cases [41], in which the delay time is 0.5T s , T s , 1.5T s , respectively.Correspondingly, the PWM module of the MCU is configured in shadow mode with double update, and the sampling instant and duty-ratio update instant are placed at the peak and valley the triangle carrier.The values of m are 1, 0.5 and 0. When m = 1, there is no computation delay, which is unprocurable for practical system.The root loci of the active damping closed-loop transfer function G a-cl (z) are illustrated in Figure 15.For Figure 15a, m is equal to 0.5.With the increase of K d , a couple of poles move from the boundary of the unit circle into the inside, meaning that the system stability is improved.However, when K d goes beyond 0.1, they move outside the unit circle, and the system becomes unstable.For Figure 15b, m is equal to 0. There is a couple of poles located outside the unit circle, indicating that the system is definitely unstable.Obviously, the time delays affect the system significantly, and a large delay time will destroy the stability of the CCF active damping loop.
For the current controller, the sampling frequency is equal to the PWM switch frequency.To simplify the design procedure, m = 0.5 is adopted in this paper.The grid current i g and capacitor current i c are sampled at the peak of the PWM carrier, and the PWM reference is updated at the valley.In other words, the analog-to-digital conversion delay and the computation delay should not exceed 0.5T s .Luckily, 50 µs is enough for a fast digital processor to achieve the control process.The design of Energies 2017, 10, 389 20 of 30 the PR regulator as current controller is widely discussed, so as to it is not included in this paper [23].With the compromise of the system stability and resonant damping, K p-pr , K r-pr , and K d are set as 0.026, 20, 0.03, respectively.

Simulation
The simulation results have been obtained by using Matlab Simulink software.First of all, the current control systems are tested independently.The PR controller and the proposed synchronous frame control scheme are both implemented and tested.The PLL is assumed to be perfect in simulation, and the phase angle is given directly.Figure 16 shows the simulation results for the two control methods when the grid voltage undergoes frequency step changes.In Figure 16a, the PR controller presents zero steady-state error when tracing 50 Hz reference signal.However, when the grid frequency steps, steady-state error can clearly observed.In Figure 16b, the steady error is eliminated for all frequency stage.The output current is highly smooth, meaning that the proposed current controller has an excellent steady-state performance in a single-phase grid-connected inverter with an LCL filter.
The transient response tests are shown in Figure 17.The FIR notch filter inserted bus voltage regulator with the Kalman-Filter-based input power feedforward is used to control the bus voltage.The proposed synchronous frame control scheme with the modulation compensation strategy is implemented as current controller.By changing the operation point of the boost circuit, the input power of the inverter is switched from about 1 kW to 2 kW.Prior to the step, the bus voltage is regulated to its nominal value of 360 V.With a positive power step, the bus capacitor charges.The average bus voltage vbus,avg has a fast response with a reasonable fluctuation of about 10.4 V.The output current maintains high quality (THD is 0.85%).
The performances of the proposed estimator and a full order state observer are presented in Figure 17c,d, respectively.Where ˆdc i is the estimated DC bus input current, ˆdc i Δ is the estimation error.For the Kalman filter, the noise variances are set as Q = 0.01 and R = 0.2.In order to calculate the estimation error, the sampled DC bus input current idc is filtered by a low pass filter.Before the power jump, both the two methods work well and have small estimation errors.As the input power increasing, ˆdc i steps from 2.6 A to 5.4 A in 60 ms, and ˆdc i Δ becomes large for short duration.ˆdc i , which is obtained by using the proposed estimator, is smoother and more accurate than the one using a full order observer.ˆdc i Δ is lower than ±0.25 A at steady-state for proposed method (±0.4A for the full order observer).Clearly, the full order observer is very sensitive to the noises, and the estimation results contain more ripples.The simulation results show that the proposed control scheme has the merits of good dynamic response and low current harmonics.The estimator using Kalman filter exhibits excellent performance for DC bus input current estimation.

Simulation
The simulation results have been obtained by using Matlab Simulink software.First of all, the current control systems are tested independently.The PR controller and the proposed synchronous frame control scheme are both implemented and tested.The PLL is assumed to be perfect in simulation, and the phase angle is given directly.Figure 16 shows the simulation results for the two control methods when the grid voltage undergoes frequency step changes.In Figure 16a, the PR controller presents zero steady-state error when tracing 50 Hz reference signal.However, when the grid frequency steps, steady-state error can be clearly observed.In Figure 16b, the steady error is eliminated for all frequency stage.The output current is highly smooth, meaning that the proposed current controller has an excellent steady-state performance in a single-phase grid-connected inverter with an LCL filter.
The transient response tests are shown in Figure 17.The FIR notch filter inserted bus voltage regulator with the Kalman-Filter-based input power feedforward is used to control the bus voltage.The proposed synchronous frame control scheme with the modulation compensation strategy is implemented as current controller.By changing the operation point of the boost circuit, the input power of the inverter is switched from about 1 kW to 2 kW.Prior to the step, the bus voltage is regulated to its nominal value of 360 V.With a positive power step, the bus capacitor charges.The average bus voltage v bus,avg has a fast response with a reasonable fluctuation of about 10.4 V.The output current maintains high quality (THD is 0.85%).
The performances of the proposed estimator and a full order state observer are presented in Figure 17c,d, respectively.Where îdc is the estimated DC bus input current, ∆ îdc is the estimation error.For the Kalman filter, the noise variances are set as Q = 0.01 and R = 0.2.In order to calculate the estimation error, the sampled DC bus input current i dc is filtered by a low pass filter.Before the power jump, both the two methods work well and have small estimation errors.As the input power increasing, îdc steps from 2.6 A to 5.4 A in 60 ms, and ∆ îdc becomes large for short duration.îdc , which is obtained by using the proposed estimator, is smoother and more accurate than the one using a full order observer.∆ îdc is lower than ±0.25 A at steady-state for proposed method (±0.4A for the full order observer).Clearly, the full order observer is very sensitive to the noises, and the estimation results contain more ripples.The simulation results show that the proposed control scheme has the merits of good dynamic response and low current harmonics.The estimator using Kalman filter exhibits excellent performance for DC bus input current estimation.

Experimental Results
A 2 kW experiment platform has been set up by taking two 32-bit ARM processors (STM32F303RCT6 from STMicroelectronics) as central processing units.One for the DC-DC converter and the other one for the DC-AC inverter.The inverter circuit parameters are the same with the simulation as shown in Table 2.The dead time of PWM is set as 2 μs.The estimated DC bus input current is outputted by the processor's DAC.To sample DC bus voltage vbus, the ground clip of the oscilloscope probe is connected to a reference potential point of 300 V. Thus, the sampled vbus is offset by 300 V, and can been observed more clearly.
The proposed synchronous frame control scheme is implemented as the current controller.Three bus voltage control schemes are implemented and experimentally tested, namely, PI controller, FIR notch filter inserted bus voltage regulator, and FIR notch filter inserted bus voltage regulator with the Kalman-filter-based input power feedforward.To test the transient response, the input power of the inverter is switched from about 1 kW to 2 kW (i.e., from half power to full power), and vice versa.

PI Controller
For the PI controller, two designs are tested.The proportional gains (Kp) are set as 0.22 and 0.015 respectively.The integral gains are equal to 2. The experimental results are shown in Figures 18 and  19.When a high proportional gain is employed, the bus voltage is well regulated during the transient, but the distortion is high (THD is 8.68%).The opposite situation occurs with a low proportional gain.The output current is nearly a pure sinusoid with low distortion (THD is 3.08%).However, the transient in the average bus voltage is unacceptably high, and it takes a very long time to reach steady state.
As pointed in Section 2, the amplitude of the third harmonic current varies with the gain of the bus voltage controller at 2ωg.For the two designs, the theoretical calculated amplitudes of the third harmonic current are 0.99 A and 0.004 A, respectively.However, the experimental results are 1.12A and 0.2 A. Clearly, a lower proportional gain leads to less distortion.The difference between the experimental results and the calculated values mainly due to the additional harmonic sources, which are not included in the calculation, such as PWM dead-time and sensor error.Thus, with a simple PI controller, the tradeoff between low harmonic distortion and high bandwidth seems unsolvable, and the designer must use a large bus capacitor to make the system work.

Experimental Results
A 2 kW experiment platform has been set up by taking two 32-bit ARM processors (STM32F303RCT6 from STMicroelectronics) as central processing units.One for the DC-DC converter and the other one for the DC-AC inverter.The inverter circuit parameters are the same with the simulation as shown in Table 2.The dead time of PWM is set as 2 µs.The estimated DC bus input current is outputted by the processor's DAC.To sample DC bus voltage v bus , the ground clip of the oscilloscope probe is connected to a reference potential point of 300 V. Thus, the sampled v bus is offset by 300 V, and can been observed more clearly.
The proposed synchronous frame control scheme is implemented as the current controller.Three bus voltage control schemes are implemented and experimentally tested, namely, PI controller, FIR notch filter inserted bus voltage regulator, and FIR notch filter inserted bus voltage regulator with the Kalman-filter-based input power feedforward.To test the transient response, the input power of the inverter is switched from about 1 kW to 2 kW (i.e., from half power to full power), and vice versa.

PI Controller
For the PI controller, two designs are tested.The proportional gains (K p ) are set as 0.22 and 0.015 respectively.The integral gains are equal to 2. The experimental results are shown in Figures 18 and 19.When a high proportional gain is employed, the bus voltage is well regulated during the transient, but the distortion is high (THD is 8.68%).The opposite situation occurs with a low proportional gain.The output current is nearly a pure sinusoid with low distortion (THD is 3.08%).However, the transient in the average bus voltage is unacceptably high, and it takes a very long time to reach steady state.
As pointed in Section 2, the amplitude of the third harmonic current varies with the gain of the bus voltage controller at 2ω g .For the two designs, the theoretical calculated amplitudes of the third harmonic current are 0.99 A and 0.004 A, respectively.However, the experimental results are 1.12A and 0.2 A. Clearly, a lower proportional gain leads to less distortion.The difference between the experimental results and the calculated values mainly due to the additional harmonic sources, which are not included in the calculation, such as PWM dead-time and sensor error.Thus, with a simple PI controller, the tradeoff between low harmonic distortion and high bandwidth seems unsolvable, and the designer must use a large bus capacitor to make the system work.

FIR Notch Filter Inserted Bus Voltage Regulator
For the FIR notch filter inserted bus voltage controller, the experimental control parameters are the same as in simulation.The experimental results are shown in Figure 20.The 2-f ripple is rejected by the FIR notch filter, so it doesn't create distortion in the grid current.Moreover, since the FIR notch filter exhibits a gain of unity at the low frequency, the bus voltage regulator is designed with high gain and high bandwidth.Consequently, compared with the PI controller with a low proportional gain, the overshoot and undershoot in the average DC bus voltage are significantly reduced, while the output current maintains high quality.

FIR Notch Filter Inserted Bus Voltage Regulator
For the FIR notch filter inserted bus voltage controller, the experimental control parameters are the same as in simulation.The experimental results are shown in Figure 20.The 2-f ripple is rejected by the FIR notch filter, so it doesn't create distortion in the grid current.Moreover, since the FIR notch filter exhibits a gain of unity at the low frequency, the bus voltage regulator is designed with high gain and high bandwidth.Consequently, compared with the PI controller with a low proportional gain, the overshoot and undershoot in the average DC bus voltage are significantly reduced, while the output current maintains high quality.

FIR Notch Filter Inserted Bus Voltage Regulator with Kalman-Filter-Based Input Power Feedforward
The noise variances of the Kalman filter are determined by experiments.To smoothen the estimated current, a large measurement covariance value is selected, and R is equal to 1.5.The system covariance value (Q) is equal to 0.1.In Figure 21a, after an input power jump, the estimated DC bus input current ˆdc i and bus voltage vbus increase simultaneously.It takes 55 ms for ˆdc i to reach the steady value.ˆdc i is very smooth and quick response to the power jump.In order to compare the performance of proposed estimator, a full order observer is also implemented and tested.The experimental results, which are presented in Figure 22, are well in agreement with simulation results.ˆdc i , which is obtained by using the full order observer, contains more noises and ripples.The proposed estimator using the Kalman filter has excellent performance over the full order observer to identify the input current amplitude in real-time.

FIR Notch Filter Inserted Bus Voltage Regulator with Kalman-Filter-Based Input Power Feedforward
The noise variances of the Kalman filter are determined by experiments.To smoothen the estimated current, a large measurement covariance value is selected, and R is equal to 1.5.The system covariance value (Q) is equal to 0.1.In Figure 21a, after an input power jump, the estimated DC bus input current îdc and bus voltage v bus increase simultaneously.It takes 55 ms for îdc to reach the steady value.îdc is very smooth and quick response to the power jump.In order to compare the performance of proposed estimator, a full order observer is also implemented and tested.The experimental results, which are presented in Figure 22, are well in agreement with simulation results.îdc , which is obtained by using the full order observer, contains more noises and ripples.The proposed estimator using the Kalman filter has excellent performance over the full order observer to identify the input current amplitude in real-time.As the input power feedforward scheme implemented, fast dynamic response is achieved during input power transient.The overshoot and undershoot in average bus voltage are reduced to 59.4% and 60.7% of the original, respectively, without additional equipment.Moreover, the settle time is significantly reduced, and the quality of output current is nearly not affected.Table 3 lists the comparative experimental results of the four bus voltage control schemes.As the input power feedforward scheme implemented, fast dynamic response is achieved during input power transient.The overshoot and undershoot in average bus voltage are reduced to 59.4% and 60.7% of the original, respectively, without additional equipment.Moreover, the settle time is significantly reduced, and the quality of output current is nearly not affected.Table 3 lists the comparative experimental results of the four bus voltage control schemes.As the input power feedforward scheme implemented, fast dynamic response is achieved during input power transient.The overshoot and undershoot in average bus voltage are reduced to 59.4% and 60.7% of the original, respectively, without additional equipment.Moreover, the settle time is significantly reduced, and the quality of output current is nearly not affected.Table 3 lists the comparative experimental results of the four bus voltage control schemes.Figure 23 shows the experimental waveforms of grid voltage and current at full load for the FIR notch filter inserted bus voltage regulator the Kalman-filter-based input power feedforward.Obviously, unity output power factor is achieved.The proposed synchronous frame current control scheme work well in actual system.The total delay time for sampling of the feedback signals and the calculation of the current controller and active damping is about 30 µs, which is less than the allowed 0.5T s .Figure 23 shows the experimental waveforms of grid voltage and current at full load for the FIR notch filter inserted bus voltage regulator with the Kalman-filter-based input power feedforward.Obviously, unity output power factor is achieved.The proposed synchronous frame current control scheme work well in actual system.The total delay time for sampling of the feedback signals and the calculation of the current controller and active damping is about 30 μs, which is less than the allowed 0.5Ts.

Modulation Compensation Strategy for Bus Voltage Ripple
An experiment has also been conducted to illustrate the performance of the modulation compensation strategy.The FIR notch filter inserted bus voltage regulator with input power feedforward is used to control bus voltage.The current loop control parameters are the same as the above experiments.The result is given as Figure 24.The THD value of the compensated system is 2.82% compared to 3.13% of uncompensated system.The third harmonic can be observed reduced significantly by comparing Figure 21d with Figure 24.

Conclusions
Design of a two-stage single-phase grid-connected converter with good dynamic response and low distortion is one of the most important topics in renewable grid-connected applications.Due to the presence of a second harmonic ripple across the DC bus voltage, the PI controller, which is

Modulation Compensation Strategy for Bus Voltage Ripple
An experiment has also been conducted to illustrate the performance of the modulation compensation strategy.The FIR notch filter inserted bus voltage regulator with input power feedforward is used to control bus voltage.The current loop control parameters are the same as the above experiments.The result is given as Figure 24.The THD value of the compensated system is 2.82% compared to 3.13% of uncompensated system.The third harmonic can be observed reduced significantly by comparing Figure 21d with Figure 24.
Energies 2017, 10, 389 26 of 30 Figure 23 shows the experimental waveforms of grid voltage and current at full load for the FIR notch filter inserted bus voltage regulator with the Kalman-filter-based input power feedforward.Obviously, unity output power factor is achieved.The proposed synchronous frame current control scheme work well in actual system.The total delay time for sampling of the feedback signals and the calculation of the current controller and active damping is about 30 μs, which is less than the allowed 0.5Ts.

Modulation Compensation Strategy for Bus Voltage Ripple
An experiment has also been conducted to illustrate the performance of the modulation compensation strategy.The FIR notch filter inserted bus voltage regulator with input power feedforward is used to control bus voltage.The current loop control parameters are the same as the above experiments.The result is given as Figure 24.The THD value of the compensated system is 2.82% compared to 3.13% of uncompensated system.The third harmonic can be observed reduced significantly by comparing Figure 21d with Figure 24.

Conclusions
Design of a two-stage single-phase grid-connected converter with good dynamic response and low distortion is one of the most important topics in renewable grid-connected applications.Due to the presence of a second harmonic ripple across the DC bus voltage, the PI controller, which is

Conclusions
Design of a two-stage single-phase grid-connected converter with good dynamic response and low distortion is one of the most important topics in renewable grid-connected applications.Due to the presence of a second harmonic ripple across the DC bus voltage, the PI controller, which is conventionally used as DC bus voltage regulator, cannot solve the tradeoff between low harmonic distortion and high bandwidth.This paper presents an accurate math model to analyze distortion caused by bus voltage ripple for the PI-based bus voltage controller.
To eliminate the tradeoff, a novel bus voltage control scheme is proposed.A second order FIR notch filter is used in the bus voltage control loop to eliminate the distortion in the reference current.Meanwhile, the Kalman-filter-based input power feedforward scheme is implemented to improve transient response.A modulation compensation strategy is also offered to remove the nonlinearity of grid current control loop, which is brought about by bus voltage ripple.
In addition, a synchronous frame current controller for single-phase systems is introduced.The math model in stationary frame, which is equivalent to a PR controller, is obtained through theoretical derivation.With the help of PLL, this control strategy is not sensitive to the grid fundamental frequency variation, while remaining the advantage of zero steady-state error and fast transient response.The implementation of the current controller for a single-phase grid-connected inverter with an LCL filter is also presented.During the design of inner CCF active damping loop, the influences of different time delays, which are caused by the digitally controlled system, are under consideration.
The results of simulations and experiments are provided to demonstrate that the proposed method can remarkably improve the dynamic performance without sacrificing the quality of the grid current.However, the insufficient of this paper is neglecting the interactions between the bus control loop and the current control loop.Further work will aim to establish an accurate math model.

Figure 1 .
Figure 1.Configuration of a two-stage single-phase grid-connected converter.

Figure 1 .
Figure 1.Configuration of a two-stage single-phase grid-connected converter.

Figure 2 .
Figure 2. (a) Circuit diagram of a single-phase grid-connected inverter with an LCL filter; (b) Control system of the inverter; (c) Simplified model of the bus voltage control system.

Figure 2 .
Figure 2. (a) Circuit diagram of a single-phase grid-connected inverter with an LCL filter; (b) control system of the inverter; and (c) simplified model of the bus voltage control system.

Figure 3 .
Figure 3. Waveforms of a two-stage single-phase gird-connected inverter using a small DC bus capacitor and a PI-based DC bus voltage controller.(a) Input current; (b) Input power; (c) Bus voltage; (d) The amplitude of the reference current; and (e) Grid current.

Figure 4 .
Figure 4. Third harmonic component amplitudes under different system parameters.The input power of the inverter (Pin) is set as 1 kW.For the left diagram, Cbus remains unchanged at 1000 μF.The amplitude of the third harmonic increases significantly with increasing the gain of the bus voltage controller (20log|Gc-bus(j2ωg)|).The gain of the bus voltage controller is kept constant as −20 dB for the right diagram.The harmonic distortion decreases with the increasing of the DC bus capacitor.The simulation results match calculated values very well for Cbus > 250 μF or

Figure 3 .
Figure 3. Waveforms of a two-stage single-phase gird-connected inverter using a small DC bus capacitor and a PI-based DC bus voltage controller.(a) Input current; (b) Input power; (c) Bus voltage; (d) The amplitude of the reference current; and (e) Grid current.

Figure 3 .
Figure 3. Waveforms of a two-stage single-phase gird-connected inverter using a small DC bus capacitor and a PI-based DC bus voltage controller.(a) Input current; (b) Input power; (c) Bus voltage; (d) The amplitude of the reference current; and (e) Grid current.

Figure 4 .
Figure 4. Third harmonic component amplitudes under different system parameters.The input power of the inverter (Pin) is set as 1 kW.For the left diagram, Cbus remains unchanged at 1000 μF.The amplitude of the third harmonic increases significantly with increasing the gain of the bus voltage controller (20log|Gc-bus(j2ωg)|).The gain of the bus voltage controller is kept constant as −20 dB for the right diagram.The harmonic distortion decreases with the increasing of the DC bus capacitor.The simulation results match calculated values very well for Cbus > 250 μF or

Figure 4 .
Figure 4. Third harmonic component amplitudes under different system parameters.

Figure 5 .
Figure 5. (a) Current control scheme considering the DC bus voltage ripple; (b) Simplified discretetime mode.

Figure 5 .
Figure 5. (a) Current control scheme considering the DC bus voltage ripple; (b) Simplified discrete-time mode.

Figure 6 .
Figure 6.(a) FIR notch filter inserted bus voltage regulator; (b) Input power feedforward scheme; (c) Equivalent model for input power feedforward scheme; and (d) FIR notch filter inserted bus voltage regulator with Kalman-filter-based input power feedforward scheme.

Figure 6 .
Figure 6.(a) FIR notch filter inserted bus voltage regulator; (b) Input power feedforward scheme; (c) Equivalent model for input power feedforward scheme; and (d) FIR notch filter inserted bus voltage regulator with Kalman-filter-based input power feedforward scheme.

Figure 7 .
Figure 7. Bode diagrams of the second order FIR notch filters with different sampling frequencies.

Figure 7 .
Figure 7. Bode diagrams of the second order FIR notch filters with different sampling frequencies.

Figure 8 .
Figure 8. Proposed modulation compensation strategy.(a) Current control scheme with the modulation compensation strategy; (b) Equivalent current control scheme.

Figure 8 .
Figure 8. Proposed modulation compensation strategy.(a) Current control scheme with the modulation compensation strategy; (b) Equivalent current control scheme.

Figure 9 .
Figure 9. Virtual vector control for current-regulated single-phase grid-connected inverters.(a) Conventional virtual vector control; (b) Equivalent model.

Figure 9 .
Figure 9. Virtual vector control for current-regulated single-phase grid-connected inverters.(a) Conventional virtual vector control; (b) Equivalent model.

Figure 10 .
Figure 10.(a) Block diagram of the proposed synchronous frame current controller; (b) Implementation of the proposed controller for a single-phase grid-connected inverter with an LCL filter; (c) Equivalent diagram for the current control scheme in stationary frame.

Figure 10 .
Figure 10.(a) Block diagram of the proposed synchronous frame current controller; (b) Implementation of the proposed controller for a single-phase grid-connected inverter with an LCL filter; (c) Equivalent diagram for the current control scheme in stationary frame.

Figure 12 .
Figure 12.Accurate mathematic model of a digitally controlled single-phase grid-connected inverter with a LCL filter.

Figure 12 .
Figure 12.Accurate mathematic model of a digitally controlled single-phase grid-connected inverter with a LCL filter.

Figure 13 .
Figure 13.Simulation and experimental power topology.

Figure 13 .
Figure 13.Simulation and experimental power topology.
(17) the Bode diagram of the bus voltage open-loop transfer function shown in Figure 14 is obtained.The design has a positive phase margin of +52.3 • and a cross-over frequency of 12.7 Hz.Energies 2017, 10, 389 19 of 30

Figure 14 .
Figure 14.Bode plot of the open-loop transfer function for the proposed bus voltage controller.

Figure 14 .
Figure 14.Bode plot of the open-loop transfer function for the proposed bus voltage controller.

Figure 16 .Figure 17 .
Figure 16.Simulation waveforms of PR controller and the proposed controller when grid voltage under goes frequency step changes.(a) PR controller; (b) Proposed synchronous frame controller.

Figure 16 .
Figure 16.Simulation waveforms of PR controller and the proposed controller when grid voltage under goes frequency step changes.(a) PR controller; (b) Proposed synchronous frame controller.

Figure 16 .Figure 17 .
Figure 16.Simulation waveforms of PR controller and the proposed controller when grid voltage under goes frequency step changes.(a) PR controller; (b) Proposed synchronous frame controller.

Figure 17 .
Figure 17.Simulation results of the transient response for a step in input power.(a) Waveforms of the bus voltage and grid current; (b) Main harmonic components; (c) Estimated DC bus input current using the proposed estimator; and (d) Estimated DC bus input current using a full order observer.

Figure 17 .
Figure 17.Simulation results of the transient response for a step in input power.(a) Waveforms of the bus voltage and grid current; (b) Main harmonic components; (c) Estimated DC bus input current using the proposed estimator; and (d) Estimated DC bus input current using a full order observer.

Figure 18 .
Figure 18.Experimental results of the PI controller with a high proportional gain.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 19 .
Figure 19.Experimental results of the PI controller with a low proportional gain.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 18 .Figure 18 .
Figure 18.Experimental results of the PI controller with a high proportional gain.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 19 .
Figure 19.Experimental results of the PI controller with a low proportional gain.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 19 .
Figure 19.Experimental results of the PI controller with a low proportional gain.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 20 .
Figure 20.Experimental results of the FIR notch filter inserted bus voltage regulator.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 20 .
Figure 20.Experimental results of the FIR notch filter inserted bus voltage regulator.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 21 .
Figure 21.Experiment results of the FIR notch filter inserted bus voltage regulator with Kalman-filterbased input power feedforward.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 22 .
Figure 22.Experimental results for the full order observer (a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW.

Figure 21 .Figure 21 .
Figure 21.Experiment results of the FIR filter inserted bus voltage regulator with Kalman-filter-based input power feedforward.(a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW; (c) Steady-state waveforms; and (d) Main harmonic components.

Figure 22 .
Figure 22.Experimental results for the full order observer (a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW.

Figure 22 .
Figure 22.Experimental results for the full order observer (a) Transient response when input power steps up from 1 kW to 2 kW; (b) Transient response when input power steps down from 2 kW to 1 kW.

Figure 23 .
Figure 23.Experimental waveforms of grid voltage and current at full load for the FIR notch filter inserted bus voltage regulator with Kalman-filter-based input power feedforward.

Figure 23 .
Figure 23.Experimental waveforms of grid voltage and current at full load for the FIR notch filter inserted bus voltage regulator with Kalman-filter-based input power feedforward.

Figure 23 .
Figure 23.Experimental waveforms of grid voltage and current at full load for the FIR notch filter inserted bus voltage regulator with Kalman-filter-based input power feedforward.

Figure 24 .
Figure 24.Main harmonic components for compensated system.
s) s e mT s s }

Table 2 .
Simulation and Experimental Parameters.

Table 2 .
Simulation and Experimental Parameters.