An Efficient Phase-Locked Loop for Distorted Three-Phase Systems

This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete Fourier transform (SGDFT) filter-based fundamental positive sequence component separator (FPSCS), the synchronousreference-frame PLL (SRF-PLL) and the secondary control path (SCP). In order to obtain an accurate fundamental positive sequence component, SGDFT filter is introduced as it features better filtering ability at the frequencies that are integer times of fundamental frequency. Meanwhile, the second order Lagrange-interpolation method is employed to approximate the actual sampling number including both integer and fractional parts as grid frequency may deviate from the rated value. Moreover, an improved SCP with single-step comparison filtering algorithm is employed as it updates reference angular frequency according to the FPSC, which promises a zero steady-state error of phase and improves the frequency tracking speed. In this paper, the mathematical model of the proposed PLL is constructed, its stability is analyzed. Also, design procedure of the control parameters is presented. The effectiveness of the proposed PLL is confirmed by experimental results and comparison with advanced pre-filtering PLLs.


Introduction
The information about instantaneous grid voltage phase and frequency are usually obtained via phase lock loop (PLL), which is of vital importance to maintain synchronization and stable operation for grid-connected power electronic devices [1][2][3][4][5].Recently, the presence of DC offsets and harmonics in grid voltages caused by measurement devices, nonlinear loads and grid faults throws down a new challenge to the synchronization technique [6].
Synchronous-reference-frame PLL (SRF-PLL) is probably the most popular synchronization technique under ideal grid condition [7,8].However, the disturbance rejection capability of SRF-PLL is poor for unbalanced voltages, harmonics, step-and ramp-changed frequency and DC offsets.Under unbalanced condition, the fundamental negative sequence component imposes the second harmonic ripple on variables in dq axis.Under polluted condition, the nth order harmonic components of input voltages become (n − 1)th harmonics (if it is a positive sequence harmonic) or (n + 1)th harmonics (if it is a negative sequence harmonic) in dq axis [9].Especially, DC offsets become fundamental component in dq axis.Under step-and ramp-changed frequency, there is an error between the reference angular frequency and the actual one.As a result, the SRF-PLL cannot track phase and frequency precisely.
The other method is the pre-filtering technique which employs various filters to extract FPSC from the non-ideal voltages [15][16][17][18][19][20][21][22][23][24][25][26][27].References [15,16] present a multiple complex-coefficient filter-based (MCCF) synchronization technique with no need of the symmetrical component method and rotating frame transformations.Reference [17] proposes a generalized second-order and third-order complex-vector filter based on reference [15] for better dynamic performance and higher harmonic attenuation, but DC offsets of input signal are not considered.Moreover, as CCF gives relatively limited gains for each order harmonics especially for DC offsets, it cannot maintain tracking precision of grid phase under harmonics and DC offsets.As a representative pre-filtering SRF-PLL, second-order generalized integrator-based (SOGI) PLL is presented in [16] and improved in references [19,20].Dual SOGI in [18] is the building block of the quadrature signal generator (QSG) and offers harmonic blocking capability to the system.References [19,20] make SOGI-PLL frequency adaptive by adding a harmonic decoupling network and an angular frequency feed forward loop, respectively.Consequently, the SOGI-based PLLs exhibit a relatively precise and frequency-adaptive response under unbalanced condition, but they also cannot track the phase precisely under harmonics and DC offsets due to similar filtering characteristics with CCF based PLL.The moving average filter-based (MAF) pre-filtering PLL has precise accuracy under unbalanced and heavily polluted conditions when the filtering window width is integer times of the input AC signal's period [21].The filtering window width in [22,23] is set to one time of the input AC signal's period in dq axis, which can eliminate DC offsets of input signal.But this will give one period delay and increase the response time.References [24] proposes a generalized delay signal cancelation-based (GDSC) pre-filtering PLL, which can eliminate the negative-sequence component and any given harmonics under unbalanced voltages, harmonics and DC offsets.References [25][26][27] focus on the frequency-adaptive scheme of GDSC-PLL.They all track frequency precisely and give an acceptable response time when input frequency varies.However, it bears burdensome digital computation time, as it needs 4 to 5 cascaded DSC modules to suppress all-field harmonics.Furthermore, the aforementioned pre-filtering PLLs give steady-state error on estimated phase when input signal's frequency varies due to the fixed reference angular frequency.Thus, some improved PLLs adopt a secondary control path (SCP) for better tracking accuracy [28,29].But the reference angular frequency is calculated directly from the input signals without pre-filter, which would make the reference angular frequency inaccuracy and consequently mislead the detected frequency under variable frequency.
With the aim of further improvement in tracking accuracy and disturbance rejection capability under unbalanced voltages, harmonics, step-and ramp-changed frequency and DC offsets, an improved PLL based on sliding Goertzel discrete Fourier transform (SGDFT) pre-filter is proposed.The FPSC is extracted by SGDFT pre-filter as it features unit gain on specified frequency and negative infinite gain on other frequencies; Second order Lagrange-interpolation method is used to approximate the actual sample number as grid frequency may deviate from the normal value; In order to obtain an accurate reference angular frequency, the extracted FPSC is adopted as the input of SCP rather than the one without being pre-filtered.Meanwhile, single-step comparison filtering algorithm is proposed according to the SCP characteristics, which gives lower delay and higher accuracy on the calculation of reference angular frequency than traditional low pass filter (LPF).By means of these schemes, zero steady-state error and rapid transient response in phase and frequency are guaranteed under distorted conditions.
The rest of this paper is organized as follows: Section 2 analyzes the SGDFT filter characteristics.Section 3 proposes the new PLL structure and its mathematical model.Section 4 describes the design and implementation method.The comparative experimental results of five PLLs obtained from the prototype comprised of signal generator and digital signal processor (DSP) TMS320F28335 control board are given in Section 5. Finally, the conclusions are drawn in Section 6.

SGDFT Overview
The quadrature signal generator (QSG) is widely used in pre-filtering PLL.However, it has limited performance under polluted condition, since the separated FPSCs still contain harmonics.The SGDFT filter is derived from the standard DFT equation and commonly used to compute DFT spectra [30].Compared with QSG, it has better filtering ability at the frequencies that are integer times of fundamental frequency.The transfer function H SGDFT (z) and the structure of SGDFT filter are shown in Equation ( 1) and Figure 1, respectively.
where k is frequency domain index and N is the sampling number.
Energies 2017, 10, 280 3 of 16 The rest of this paper is organized as follows: Section 2 analyzes the SGDFT filter characteristics.Section 3 proposes the new PLL structure and its mathematical model.Section 4 describes the design and implementation method.The comparative experimental results of five PLLs obtained from the prototype comprised of signal generator and digital signal processor (DSP) TMS320F28335 control board are given in Section 5. Finally, the conclusions are drawn in Section 6.

SGDFT Overview
The quadrature signal generator (QSG) is widely used in pre-filtering PLL.However, it has limited performance under polluted condition, since the separated FPSCs still contain harmonics.The SGDFT filter is derived from the standard DFT equation and commonly used to compute DFT spectra [30].Compared with QSG, it has better filtering ability at the frequencies that are integer times of fundamental frequency.The transfer function HSGDFT(z) and the structure of SGDFT filter are shown in Equation ( 1) and Figure 1, respectively.
where k is frequency domain index and N is the sampling number.Figure 2 shows the frequency response and z-domain zero/pole of SGDFT.As shown in Figure 2a, Hre(z) and Him(z) are the real and imaginary part of HSGDFT(z), while Gd(s) and Gq(s) represent the transfer function of QSG in d and q axis, respectively.The magnitude of the four transfer functions are all 0 dB at the fundamental frequency f0 = 50 Hz.It is shown that the frequency response of SGDFT is same with QSG except at the frequencies that are integer times of f0.Meanwhile, SGDFT has much smaller gain than QSG at the integer multiple of f0, which means that SGDFT has better filtering ability than QSG under polluted condition.In Figure 2b, there are 256 zeros (blue circle) of the transfer function equally spaced around the unit circle on z-domain.Moreover, it has two conjugate poles (red cross) cancelling zeros at z = e ±j2π/256 .Thus, one can conclude that SGDFT can calculate the fundamental coefficient of the input signal precisely.Therefore, SGDFT is introduced to separate the FPSC. Figure 2 shows the frequency response and z-domain zero/pole of SGDFT.As shown in Figure 2a, H re (z) and H im (z) are the real and imaginary part of H SGDFT (z), while G d (s) and G q (s) represent the transfer function of QSG in d and q axis, respectively.The magnitude of the four transfer functions are all 0 dB at the fundamental frequency f 0 = 50 Hz.It is shown that the frequency response of SGDFT is same with QSG except at the frequencies that are integer times of f 0 .Meanwhile, SGDFT has much smaller gain than QSG at the integer multiple of f 0 , which means that SGDFT has better filtering ability than QSG under polluted condition.In Figure 2b, there are 256 zeros (blue circle) of the transfer function equally spaced around the unit circle on z-domain.Moreover, it has two conjugate poles (red cross) cancelling zeros at z = e ±j2π/256 .Thus, one can conclude that SGDFT can calculate the fundamental coefficient of the input signal precisely.Therefore, SGDFT is introduced to separate the FPSC.

The Proposed PLL
The block diagram of the proposed PLL is shown in Figure 3.This PLL structure consists of three main parts: FPSCS, SRF-PLL and SCP.The FPSCS module uses SGDFT filter and the symmetrical component method to separate the FPSC precisely even under distorted conditions.Considering that the practical grid frequency may deviate from the rated value, Lagrange-interpolation method is adopted to approximate the actual sampling number Nr, in order to make the SGDFT filter effective under variable frequency.The SCP module updates reference angular frequency, which improves its tracking performance.

SGDFT-Based FPSCS
The SGDFT structure is shown in Figure 1 In practical power system, the grid frequency f0 is a time-varying parameter.The problem arises when f0 cannot be divisible by the sampling frequency fs, i.e., the order Nr would not be a integer and can be described as Nr = Na + D, where Na = floor (Nr) is the integer and D = Nr − Na (0 ≤ D < 1) is the fractional part.Thus, the delay is given as: z −Nr = z −Na z −D .The Lagrange-interpolation method is introduced because it is an effective way to approximate the fractional delay for FIR filter design [31].The fraction delay z −D can be approximated by:

The Proposed PLL
The block diagram of the proposed PLL is shown in Figure 3.This PLL structure consists of three main parts: FPSCS, SRF-PLL and SCP.The FPSCS module uses SGDFT filter and the symmetrical component method to separate the FPSC precisely even under distorted conditions.Considering that the practical grid frequency may deviate from the rated value, Lagrange-interpolation method is adopted to approximate the actual sampling number N r , in order to make the SGDFT filter effective under variable frequency.The SCP module updates reference angular frequency, which improves its tracking performance.

The Proposed PLL
The block diagram of the proposed PLL is shown in Figure 3.This PLL structure consists of three main parts: FPSCS, SRF-PLL and SCP.The FPSCS module uses SGDFT filter and the symmetrical component method to separate the FPSC precisely even under distorted conditions.Considering that the practical grid frequency may deviate from the rated value, Lagrange-interpolation method is adopted to approximate the actual sampling number Nr, in order to make the SGDFT filter effective under variable frequency.The SCP module updates reference angular frequency, which improves its tracking performance.

SGDFT-Based FPSCS
The SGDFT structure is shown in Figure 1.
In practical power system, the grid frequency f0 is a time-varying parameter.The problem arises when f0 cannot be divisible by the sampling frequency fs, i.e., the order Nr would not be a integer and can be described as Nr = Na + D, where Na = floor (Nr) is the integer and D = Nr − Na (0 ≤ D < 1) is the fractional part.Thus, the delay is given as: z −Nr = z −Na z −D .The Lagrange-interpolation method is introduced because it is an effective way to approximate the fractional delay for FIR filter design [31].The fraction delay z −D can be approximated by: In practical power system, the grid frequency f 0 is a time-varying parameter.The problem arises when f 0 cannot be divisible by the sampling frequency f s , i.e., the order N r would not be a integer and can be described as N r = N a + D, where N a = floor (N r ) is the integer and D = N r − N a (0 ≤ D < 1) is the fractional part.Thus, the delay is given as: z −Nr = z −Na z −D .The Lagrange-interpolation method is introduced because it is an effective way to approximate the fractional delay for FIR filter design [31].The fraction delay z −D can be approximated by: The coefficients H(k) are calculated as: The magnitude of fraction delay with the order n = 3 is close to the case with D = 0 while it exceeds the unit amplitude, which may introduce stability problem.Moreover, the fraction delay with the order n = 3 consumes more addition and multiplication operations than n = 2. Considering these two aspects, n = 2 is chosen to be the Lagrange interpolation order.Hence, the corresponding fractional delay is: Energies 2017, 10, 280 5 of 16 The coefficients H(k) are calculated as: The magnitude of fraction delay with the order n = 3 is close to the case with D = 0 while it exceeds the unit amplitude, which may introduce stability problem.Moreover, the fraction delay with the order n = 3 consumes more addition and multiplication operations than n = 2. Considering these two aspects, n = 2 is chosen to be the Lagrange interpolation order.Hence, the corresponding fractional delay is: Therefore, the structure of SGDFT can be improved, as shown in Figure 5.  Therefore, the structure of SGDFT can be improved, as shown in Figure 5.

Description of SCP
Energies 2017, 10, 280 5 of 16 The coefficients H(k) are calculated as: ( ) Specifically, the case n = 1 corresponds to the linear interpolation and the two coefficients are H(0) = 1 − D and H(1) = D.The magnitude of fraction delay with the order n = 3 is close to the case with D = 0 while it exceeds the unit amplitude, which may introduce stability problem.Moreover, the fraction delay with the order n = 3 consumes more addition and multiplication operations than n = 2. Considering these two aspects, n = 2 is chosen to be the Lagrange interpolation order.Hence, the corresponding fractional delay is: Therefore, the structure of SGDFT can be improved, as shown in Figure 5.  Energies 2017, 10, 280 6 of 16

Description of SCP
The secondary control path is introduced to improve the transient response rate.Moreover, it updates the reference angular frequency to decrease phase error under variable frequency.
In reference [28], the phase θ ∈ [−π/2, π/2] can be deduced as θ = tan −1 (v + β /v + α ).However, arctangent function gives rapid change at ±nπ/2, which results in differential errors in digital implementation.Therefore, this paper uses arcsin function to calculate the phase.Besides, an abs function is adopted to regulate the negative angular frequency.In order to eliminate the digital differential error in the regulated angular frequency, the single-step comparison filter is realized as follows: where k n is the current cycle counter.Both the differential part d/dt and Equation ( 6) need one control period delay, thus its transfer function can be described as G f (s) = 1/(2T s s + 1).As analyzed in Section 2, the model of SGDFT is equivalent to QSG.Thus, the pre-filtering stage small signal model in the proposed PLL can be used as , where ω o equals to 0.707ω r .Therefore, the secondary control path transfer function is Moreover, the introduction of SCP changes the type and pole-zero location of tracking loop [29].Thus, the voltage normalization part is employed to remove this adverse effect.It can be achieved as:

Proposed PLL Model
According to the aforementioned deduction, the small-signal model and equivalent model of the proposed PLL are shown in Figure 6.
Energies 2017, 10, 280 6 of 16 The secondary control path is introduced to improve the transient response rate.Moreover, it updates the reference angular frequency to decrease phase error under variable frequency.
In reference [28], the phase θ ∈ [−π/2, π/2] can be deduced as θ = tan −1 (v + β /v + α ).However, arctangent function gives rapid change at ±nπ/2, which results in differential errors in digital implementation.Therefore, this paper uses arcsin function to calculate the phase.Besides, an abs function is adopted to regulate the negative angular frequency.In order to eliminate the digital differential error in the regulated angular frequency, the single-step comparison filter is realized as follows: where kn is the current cycle counter.Both the differential part d/dt and Equation ( 6) need one control period delay, thus its transfer function can be described as Gf(s) = 1/(2Tss + 1).As analyzed in Section 2, the model of SGDFT is equivalent to QSG.Thus, the pre-filtering stage small signal model in the proposed PLL can be used as Go(s) = ωo/(s + ωo), where ωo equals to 0.707ωr.Therefore, the secondary control path transfer function is ωr(s) = Go(s) × Gf(s) × ω(s).
Moreover, the introduction of SCP changes the type and pole-zero location of tracking loop [29].Thus, the voltage normalization part is employed to remove this adverse effect.It can be achieved as: ( ) ( )

Proposed PLL Model
According to the aforementioned deduction, the small-signal model and equivalent model of the proposed PLL are shown in Figure 6.Then the open-loop transfer function can be obtained as: It can be deduced from Figure 6b as: Then the open-loop transfer function can be obtained as: Energies 2017, 10, 280 The term G o (s) × G f (s) can be replaced by G e (s) = 1/(T e s + 1) because these two terms are small inertial elements, where T e is the equivalent delay that equals to 2T s + 1/ω o .Therefore, the complete open-loop and closed-loop transfer functions are:

Systematic Design Approach
The aim of this section consists of four aspects: parameter design guidelines for the proposed PLL, system stability analysis, study of bandwidth and dynamic responses, and discrete implementation method.

Parameters Design
It can be seen from Equation ( 10) that the open-loop transfer function is a four-order expression.Thus, zero-pole cancellation which is convenient for parameters design is adopted to simplify the system.Suppose that numerator polynomial has three real zeros, and one of them equals to ω o .Thus, the open-loop transfer function would be: It has been proved that the coincident zeros (i.e., ω z1 = ω z2 ) can provide a higher stability margin than the spread ones [32].Thus, combining Equations ( 10), (12) and ω z1 = ω z2 = ω z , Equation (10) can be rewritten as: where k p and k i are the proportional and integral parameters of PI regulator shown in Figure 6.
From Equation (13), the phase margin (PM) and the crossover frequency ω c of the proposed PLL can be determined as: 1 T e sin 2 (tan −1 (h)) (14) where ω c = hω z .Figure 7 illustrates that PM is a function of h.

System Stability
It is known that the introduction of SCP aggravates the stability problem as the voltage amplitude Vm changes the zeros of the open-loop and closed-loop transfer function.Thus, the voltage normalization is utilized to remove this effect.From Equations ( 10) and ( 11), it can be seen that Vm is The PM within the range of 30 • ~60 • is the recommended range for stable operation [32].Generally, PM = 45 • is selected, which corresponds to h = 2.5, as shown in Figure 7.When h = 2.5, it can be derived that ω c = 246.8rad/s, ω z = 98.7 rad/s, k p = 2ω z /(ω o × T e ) = 189.2and k i = ω z 2 = 9746 according to Equations ( 13) and ( 14).

System Stability
It is known that the introduction of SCP aggravates the stability problem as the voltage amplitude V m changes the zeros of the open-loop and closed-loop transfer function.Thus, the voltage normalization is utilized to remove this effect.From Equations ( 10) and ( 11), it can be seen that V m is no longer an influence factor.According to the analysis in Section 4.1, the open-loop bode plots are shown in Figure 8.

System Stability
It is known that the introduction of SCP aggravates the stability problem as the voltage amplitude Vm changes the zeros of the open-loop and closed-loop transfer function.Thus, the voltage normalization is utilized to remove this effect.From Equations ( 10) and ( 11), it can be seen that Vm is no longer an influence factor.According to the analysis in Section 4.1, the open-loop bode plots are shown in Figure 8.It can be observed that the gain margin (GM) is between 8.1 and 16.9 dB within the PM range of 29.1°~60.2°,which are coincide with the aforementioned calculation.Therefore, one can conclude that the design guideline for the proposed PLL gives satisfactory PM and GM.

Bandwidth and Dynamic Response Evaluation
In order to analyze the bandwidth of the proposed PLL, the closed-loop bode plots of SRF-PLL, DSOGI-PLL and the proposed PLL are drawn.From Figure 9, it can be seen that the proposed PLL obtains wider bandwidth than the other two PLLs.It can be observed that the gain margin (GM) is between 8.1 and 16.9 dB within the PM range of 29.1 • ~60.2 • , which are coincide with the aforementioned calculation.Therefore, one can conclude that the design guideline for the proposed PLL gives satisfactory PM and GM.

Bandwidth and Dynamic Response Evaluation
In order to analyze the bandwidth of the proposed PLL, the closed-loop bode plots of SRF-PLL, DSOGI-PLL and the proposed PLL are drawn.From Figure 9, it can be seen that the proposed PLL obtains wider bandwidth than the other two PLLs.The dynamic responses of the proposed PLL are evaluated by the unit step and ramp response.The corresponding transient responses are shown in Figure 10.It can be seen that the settling time are about 2 fundamental periods in these two conditions.Also, the steady-state value of unit step response equals to 1, and ramp response tracks the input ramp function 1/s 2 precisely.These results validate that the proposed PLL obtains good dynamic performance.The dynamic responses of the proposed PLL are evaluated by the unit step and ramp response.The corresponding transient responses are shown in Figure 10.It can be seen that the settling time are about 2 fundamental periods in these two conditions.Also, the steady-state value of unit step response equals to 1, and ramp response tracks the input ramp function 1/s 2 precisely.These results validate that the proposed PLL obtains good dynamic performance.The dynamic responses of the proposed PLL are evaluated by the unit step and ramp response.The corresponding transient responses are shown in Figure 10.It can be seen that the settling time are about 2 fundamental periods in these two conditions.Also, the steady-state value of unit step response equals to 1, and ramp response tracks the input ramp function 1/s 2 precisely.These results validate that the proposed PLL obtains good dynamic performance.

Discrete Implementation of the Proposed PLL
Performance of the proposed PLL highly depends on digital discretization approach.The Tustin with pre-warping method ( T z ) gives better accuracy and frequency characteristics than the forward Euler and the backward Euler methods [33].It is worth noting that SRF-PLL is regulated in q-axis.Therefore, ω1=0 and Tustin with pre-warping method has the same effect as Tustin (trapezoidal) method ( ).The discretization implementations of the proposed PLL are shown in Table 1.It is worth noting that n means the current period and y means α or β.

Discrete Implementation of the Proposed PLL
Performance of the proposed PLL highly depends on digital discretization approach.The Tustin with pre-warping method (s = ω 1 tan(0.5ω 1 T s ) z−1 z+1 ) gives better accuracy and frequency characteristics than the forward Euler and the backward Euler methods [33].It is worth noting that SRF-PLL is regulated in q-axis.Therefore, ω 1 = 0 and Tustin with pre-warping method has the same effect as Tustin (trapezoidal) method (s = 2 ).The discretization implementations of the proposed PLL are shown in Table 1.It is worth noting that n means the current period and y means α or β.

Discretization Expression
Difference Equation Implementations

Experimental Validation
The aim of this section is to evaluate the performance of the proposed PLL by extensive experimental studies under distorted conditions.The experimental setup presented in Figure 11 consists of signal generator and digital signal processor (DSP) TMS320F28335 control board.Throughout the experimental studies, the voltage benchmark is 311 V and the grid fundamental frequency f 0 is 50 Hz.The PI parameters in control loop are: k p = 189.2k i = 9746 and the sampling frequency f s is 12.8 kHz.In addition, three phase DC offsets (0.1 p.u., −0.

Experimental Validation
The aim of this section is to evaluate the performance of the proposed PLL by extensive experimental studies under distorted conditions.The experimental setup presented in Figure 11 consists of signal generator and digital signal processor (DSP) TMS320F28335 control board.Throughout the experimental studies, the voltage benchmark is 311 V and the grid fundamental frequency f0 is 50 Hz.The PI parameters in control loop are: kp = 189.2ki = 9746 and the sampling frequency fs is 12.8 kHz.In addition, three phase DC offsets (0.

Experimental Results of the Proposed PLL under Distorted Conditions
The main variables of the proposed PLL are displayed: three-phase voltage (v abc ); FPSCs in two-phase stationary frame (v + α and v + β ); phase angle of fundamental positive sequence voltages (θ + p ); calculated reference angular frequency (ω r ); detected grid frequency (f m ); estimated phase error (∆θ); detected frequency error (∆f ).The settling time is the time required for the response curve to reach and stay within certain range of 98% steady-state value for ∆θ and ∆f, respectively.Figure 12 shows the experimental results of the proposed PLL performed under voltage sag (condition I), phase jump (condition II), harmonics (condition III), and step-changed frequency (condition IV).
As can be seen in Figure 12, v + α and v + β give same amplitude and π/2 angle difference, which means the FPSCs are extracted accurately under conditions I-IV.As SGDFT needs one cycle to collect data, v + α and v + β become stable after one cycle when disturbances occur at t = 30 ms, t = 40 ms, t = 50 ms and t = 60 ms.Besides, it is worth noticing that θ + p and v + α reach the maximum simultaneously and f m is in accordance with f 0 in steady-state regardless of the distorted conditions.
The performance of the proposed PLL under ramp-changed frequency (condition V) is also evaluated.The corresponding experimental results are shown in Figure 13.It can be observed that f m tracks the ramp change of f 0 with a small error.In addition, f m gives obvious overshoot at the start and end of ramp change, as SGDFT cannot give correct reference during its settling process.The detailed steady-state and dynamic performance indexes under conditions I-V are shown in the next section.
phase stationary frame (v + α and v + β ); phase angle of fundamental positive sequence voltages (θ + p ); calculated reference angular frequency (ωr); detected grid frequency (fm); estimated phase error (Δθ); detected frequency error (Δf).The settling time is the time required for the response curve to reach and stay within certain range of 98% steady-state value for Δθ and Δf, respectively.Figure 12 shows the experimental results of the proposed PLL performed under voltage sag (condition I), phase jump (condition II), harmonics (condition III), and step-changed frequency (condition IV).As can be seen in Figure 12, v + α and v + β give same amplitude and π/2 angle difference, which means the FPSCs are extracted accurately under conditions I-IV.As SGDFT needs one cycle to collect data, v + α and v + β become stable after one cycle when disturbances occur at t = 30 ms, t = 40 ms, t = 50 ms and t = 60 ms.Besides, it is worth noticing that θ + p and v + α reach the maximum simultaneously and fm is in accordance with f0 in steady-state regardless of the distorted conditions.
The performance of the proposed PLL under ramp-changed frequency (condition V) is also evaluated.The corresponding experimental results are shown in Figure 13.It can be observed that fm tracks the ramp change of f0 with a small error.In addition, fm gives obvious overshoot at the start and end of ramp change, as SGDFT cannot give correct reference during its settling process.The detailed steady-state and dynamic performance indexes under conditions I-V are shown in the next section.

Experimental Results Compared with Other Pre-Filtered PLLs
The effectiveness of the proposed PLL is further confirmed by comparing its performance with MCCF-PLL, DSOGI-PLL, PMAF-PLL and GDSC-PLL in [15,18,21,24], respectively.In order to allow a fair evaluation, the PI parameters of the above four PLLs are regulated according to the tunning methods in the corresponding articles.The PI parameters of the above four PLLs are: kp1 = 141.1 ki1 = 9952, kp2 = 222 ki2 = 6169, kp3 = 390 ki3 = 40,426, and kp4 = 266 ki4 = 35,530, respectively.The comparative tracking performance under conditions I-V are shown in Figures 14 and 15.Besides, the relevant data are summarized in Table 2.
It can be seen from Figure 14 that only MCCF-PLL and DSOGI-PLL contain obvious fundamental component in Δθ and Δf as their pre-filters are not effective for DC offsets.Also, it is clear that Δθ and Δf of MCCF-PLL and DSOGI-PLL are strongly distorted under heavily polluted condition due to their limited filtering characteristic for harmonics.As shown in Figure 14a-c

Experimental Results Compared with Other Pre-Filtered PLLs
The effectiveness of the proposed PLL is further confirmed by comparing its performance with MCCF-PLL, DSOGI-PLL, PMAF-PLL and GDSC-PLL in [15,18,21,24], respectively.In order to allow a fair evaluation, the PI parameters of the above four PLLs are regulated according to the tunning methods in the corresponding articles.The PI parameters of the above four PLLs are: k p1 = 141.1 k i1 = 9952, k p2 = 222 k i2 = 6169, k p3 = 390 k i3 = 40,426, and k p4 = 266 k i4 = 35,530, respectively.The comparative tracking performance under conditions I-V are shown in Figures 14 and 15.Besides, the relevant data are summarized in Table 2.     MCCF-PLL and DSOGI-PLL have obvious fundamental components of Δθ and Δf under steadystate condition, while the other three PLLs can obtain zero steady-state error of Δθ and Δf under conditions I-IV except for Δθ of PMAF-PLL and GDSC-PLL under condition IV.Moreover, the proposed PLL gives the smallest steady-state values of Δθ and Δf.
We can conclude from the experimental results in Figures 12-15 and Table 2 that, (1) Like PMAF-PLL and GDSC-PLL, the proposed PLL has good disturbance rejection capability of DC offsets; (2) Only the proposed PLL can solve the ramp-changed frequency problem due to its improved SCP; (3) The proposed PLL can obtain the least settling time of phase and frequency under conditions I-IV; (4) The proposed PLL gives the least overshoot of phase and the third small overshoot of frequency under conditions I-IV; (5) The proposed PLL almost obtains zero stead-state error of phase and frequency.

Conclusions
This paper presents an efficient PLL based on SGDFT filter and the improved SCP.SGDFT filter is employed to enhance separation accuracy of FPSC under distorted conditions.Lagrangeinterpolation method is applied to remove the adverse effect of the fractional delay when the sampling number is not integer.The improved SCP is employed to promise precise phase estimation  It can be seen from Figure 14 that only MCCF-PLL and DSOGI-PLL contain obvious fundamental component in ∆θ and ∆f as their pre-filters are not effective for DC offsets.Also, it is clear that ∆θ and ∆f of MCCF-PLL and DSOGI-PLL are strongly distorted under heavily polluted condition due to their limited filtering characteristic for harmonics.As shown in Figure 14a-c, PMAF-PLL, GDSC-PLL and the proposed PLL have satisfactory disturbance rejection ability for DC offsets, voltage sag, phase jump and harmonics.However, PMAF-PLL and GDSC-PLL give obvious ∆θ steady-state errors in Figure 14d.Moreover, in Figure 15 MCCF-PLL, DSOGI-PLL, PMAF-PLL and GDSC-PLL cannot track ramp-changed frequency accurately as their reference angular frequency is not updated with input signal's frequency.It is clear that the proposed PLL is effective under DC offsets, voltage sag, phase jump, harmonics, step-and ramp-changed frequency.
In Table 2, the performance indexes of the first four PLLs under condition V is not provided as they cannot track the ramp-changed frequency stably.Moreover, the steady-state values of MCCF-PLL and DSOGI-PLL refer to the peak value because they both contain fundamental components.
As summarized in Table 2, DSOGI-PLL gives the maximal settling time overall.The settling time of PMAF-PLL and GDSC-PLL are almost same.They are slightly smaller than DSOGI-PLL.MCCF-PLL tracks relatively faster than the previous PLLs.The proposed PLL gives the least settling time of ∆θ

Conclusions
This paper presents an efficient PLL based on SGDFT filter and the improved SCP.SGDFT filter is employed to enhance separation accuracy of FPSC under distorted conditions.Lagrange-interpolation method is applied to remove the adverse effect of the fractional delay when the sampling number is not integer.The improved SCP is employed to promise precise phase estimation and enables the PLL tracking reference frequency rapidly.Comparative experimental results demonstrate that the proposed PLL can achieve zero steady-state error in phase and frequency with a rapid speed compared with the other four PLLs.Meanwhile, it has satisfactory disturbance rejection capability under unbalanced voltages, harmonics, step-and ramp-changed frequency and DC offsets.

Figure 3 .
Figure 3. Block diagram of the proposed PLL.

Figure 3 .
Figure 3. Block diagram of the proposed PLL.
vα and vβ are input signals in two-phase stationary frame.v ′ α and qv ′ α are the filtered direct and quadrature parameters of vα.v ′ β and qv ′ β are the filtered direct and quadrature parameters of vβ.v + α and v + β are FPSC in two-phase stationary frame, v + α1 and v + β1 are normalized FPSC.The FPSC v + α and v + β in αβ axis are obtained by:

Figure 3 .
Figure 3. Block diagram of the proposed PLL.

3. 1 .
SGDFT-Based FPSCSThe SGDFT structure is shown in Figure1.v α and v β are input signals in two-phase stationary frame.v α and qv α are the filtered direct and quadrature parameters of v α .v β and qv β are the filtered direct and quadrature parameters of v β .v + α and v + β are FPSC in two-phase stationary frame, v + α1 and v + β1 are normalized FPSC.The FPSC v + α and v + β in αβ axis are obtained by: Specifically, the case n = 1 corresponds to the linear interpolation and the two coefficients are H(0) = 1 − D and H(1) = D. Figure 4 shows the frequency responses of Lagrange-interpolating fraction delay z −D at different D values.In Figure 4, the fractional D are 0.3 (red line), 0.5 (green line) and 0.75 (blue line) for validation.It shows that the magnitude of fraction delay with n = 2 (dashed line) is closer to the case with D = 0 (the real value), meanwhile the phase has smaller change at different D values than n = 1 (solid line).
4) Specifically, the case n = 1 corresponds to the linear interpolation and the two coefficients are H(0) = 1 − D and H(1) = D. Figure 4 shows the frequency responses of Lagrange-interpolating fraction delay z −D at different D values.In Figure 4, the fractional D are 0.3 (red line), 0.5 (green line) and 0.75 (blue line) for validation.It shows that the magnitude of fraction delay with n = 2 (dashed line) is closer to the case with D = 0 (the real value), meanwhile the phase has smaller change at different D values than n = 1 (solid line).
Figure 4 shows the frequency responses of Lagrange-interpolating fraction delay z −D at different D values.In Figure 4, the fractional D are 0.3 (red line), 0.5 (green line) and 0.75 (blue line) for validation.It shows that the magnitude of fraction delay with n = 2 (dashed line) is closer to the case with D = 0 (the real value), meanwhile the phase has smaller change at different D values than n = 1 (solid line).

Figure 6 .
Figure 6.Small-signal model of the proposed PLL.(a) Original model; (b) Equivalent model.It can be deduced from Figure6bas:

Figure 6 .
Figure 6.Small-signal model of the proposed PLL.(a) Original model; (b) Equivalent model.

Figure 7 .
Figure 7. PM is a function of h.

Figure 7 .
Figure 7. PM is a function of h.

Figure 8 .
Figure 8. Open-loop bode plots of the proposed PLL.

Figure 8 .
Figure 8. Open-loop bode plots of the proposed PLL.

Figure 9 .
Figure 9. Closed-loop Bode plots of three kinds of PLL for h = 2.5.

Figure 9 .
Figure 9. Closed-loop Bode plots of three kinds of PLL for h = 2.5.

Figure 10 .
Figure 10.Transient response of closed-loop transfer function for h = 2.5.(a) The unit step response; (b) The unit impulse response.

Figure 10 .
Figure 10.Transient response of closed-loop transfer function for h = 2.5.(a) The unit step response; (b) The unit impulse response.
1 p.u. and 0.1 p.u.) caused by measurement devices are considered all the time in the rest experiments.The detailed distorted conditions performed in experiments are summarized as follows: Condition I: An asymmetric voltage sags (0.1, 0.2 and 0.3 p.u.) at t = 30 ms.Condition II: An asymmetric phase jumps (10 • , 20 • , and 30 • ) at t = 40 ms.Condition III: 5th and 7th order harmonics (0.2 and 0.1 p.u.) emerge at t = 50 ms.Condition IV: Grid frequency jumps from 50 to 55 Hz at t = 60 ms.Condition V: Grid frequency ramp change occurs at t = 100 ms with ramp rate of 20 Hz/s.SCP ( ) ( 1 p.u., −0.1 p.u. and 0.1 p.u.) caused by measurement devices are considered all the time in the rest experiments.The detailed distorted conditions performed in experiments are summarized as follows: Condition I: An asymmetric voltage sags (0.1, 0.2 and 0.3 p.u.) at t = 30 ms.Condition II: An asymmetric phase jumps (10°, 20°, and 30°) at t = 40 ms.Condition III: 5th and 7th order harmonics (0.2 and 0.1 p.u.) emerge at t = 50 ms.Condition IV: Grid frequency jumps from 50 to 55 Hz at t = 60 ms.Condition V: Grid frequency ramp change occurs at t = 100 ms with ramp rate of 20 Hz/s.

Figure 13 .
Figure 13.The experimental results under ramp-changed frequency.

Figure 15 .
Figure 15.The comparative experimental results under ramp-changed frequency.

Figure 15 .
Figure 15.The comparative experimental results under ramp-changed frequency.

. vα and vβ are input signals in two-phase stationary
frame.v ′ α and qv ′ α are the filtered direct and quadrature parameters of vα.v ′ β and qv ′ β are the filtered direct and quadrature parameters of vβ.v + α and v + β are FPSC in two-phase stationary frame, v + α1 and v + β1 are normalized FPSC.The FPSC v + α and v + β in αβ axis are obtained by:

Table 1 .
The digital implementation.

Table 2 .
Dynamic performance index.

Table 2 .
Dynamic performance index.

PLL DSOGI-PLL PMAF-PLL GDSC-PLL Proposed PLL
DC offsets are considered in all conditions in Table2.