Evaluation and Reliability Assessment of Gan-on-si Mis-hemt for Power Switching Applications

This paper reports an extensive analysis of the physical mechanisms responsible for the failure of GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (HEMTs). When stressed under high applied electric fields, the traps at the dielectric/III-N barrier interface and inside the III-N barrier cause an increase in dynamic on-resistance and a shift of threshold voltage, which might affect the long term stability of these devices. More detailed investigations are needed to identify epitaxy-or process-related degradation mechanisms and to understand their impact on electrical properties. The present paper proposes a suitable methodology to characterize the degradation and failure mechanisms of GaN MIS-HEMTs subjected to stress under various off-state conditions. There are three major stress conditions that include: V DS = 0 V, off, and off (cascode-connection) states. Changes of direct current (DC) figures of merit in voltage step-stress experiments are measured, statistics are studied, and correlations are investigated. Hot electron stress produces permanent change which can be attributed to charge trapping phenomena and the generation of deep levels or interface states. The simultaneous generation of interface (and/or bulk) and buffer traps can account for the observed degradation modes and mechanisms. These findings provide several critical characteristics to evaluate the electrical reliability of GaN MIS-HEMTs which are borne out by step-stress experiments.


Introduction
AlGaN/GaN high electron mobility transistors (HEMTs) have attracted a lot of attention for both switching and radio frequency (RF) power applications [1][2][3].The Schottky-gate-controlled heterojunction two-dimensional electron gas (2DEG) channel, which is widely used for high-frequency RF applications [4] is not desirable for next generation power electronics for the following reasons.Firstly, HEMTs are struggling to achieve high breakdown voltage, low on-state resistance and fast switching at the same time.Since the Schottky barrier layer suffers from possible damage in the subsequent processing steps, the large gate leakage current increases the off-state loss and reduces power supply efficiency [5,6].Secondly, the 2DEG of conventional HEMT structures cannot be easily depleted under the gate for normally-off (E-mode) operation [7,8].E-mode field-effect transistors (FETs) are essential in power electronics applications for avoiding circuit burnout and realizing great   Device's on-resistance.Defined as the inverse of IDlin.

Device Structure and Experimental Setup
A schematic of the AlGaN/GaN MIS-HEMT is shown in Figure 2.This device was fabricated using a complete complementary metal oxide semiconductor (CMOS)-compatible process for GaN-based MIS-HEMTs on Silicon.The AlGaN/GaN heterostructure epilayer was grown on a silicon substrate (thickness, 900 μm) by metalorganic chemical vapour deposition (MOCVD).The epitaxial structure consisted of a 3.9 μm-thick GaN/AlGaN buffer layer, on which was deposited a 2.1 μm-thick GaN layer, a 20 nm-thick Al0.23Ga0.77Nbarrier layer and, finally, a 4 nm-thick GaN capping layer.
To fabricate this device, Mesa isolation was performed with an ICP-RIE system with Cl2 as the etching gas.Source/drain Ohmic contacts were formed with e-beam evaporation and lift-off of Ti/Al/Ni/Au (20 nm/120 nm/25 nm/100 nm) metal stack, followed by rapid thermal annealing at 800 °C in N2 for 60 s.After removing the photoresist and carrying out a surface cleaning process to remove impurities and reduce surface dangling bonds, a 50 nm-thick Si3N4 film was immediately grown by plasma-enhanced chemical vapor deposition (PECVD) and deployed as the gate insulator.The gate electrode was formed with Ni/Au (50 nm/450 nm) deposited upon the top of the dielectric

Parameters Definition
Drain leakage current.Measured at V GS = −20 V and V DS = 0 V.I Soff Source leakage current.Measured at V GS = −20 V and V DS = 0 V.

I G_stress
Gate stress current.Measured at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain).

I D_stress
Drain stress current.Measured at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain).

I S_stress
Source stress current.Measured at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain).

I Dlin
Linear-regime drain current.Measured at V GS = 0 V and V DS = 1 V.I Dmax Maximum drain current.Measured at V GS = 0 V and V DS = 10 V. V th Threshold voltage.Defined as V GS at I DS = 1 mA/mm for V DS = 1 V. R on Device's on-resistance.Defined as the inverse of I Dlin .

Device Structure and Experimental Setup
A schematic of the AlGaN/GaN MIS-HEMT is shown in Figure 2.This device was fabricated using a complete complementary metal oxide semiconductor (CMOS)-compatible process for GaN-based MIS-HEMTs on Silicon.The AlGaN/GaN heterostructure epilayer was grown on a silicon substrate (thickness, 900 µm) by metalorganic chemical vapour deposition (MOCVD).The epitaxial structure consisted of a 3.9 µm-thick GaN/AlGaN buffer layer, on which was deposited a 2.1 µm-thick GaN layer, a 20 nm-thick Al 0.23 Ga 0.77 N barrier layer and, finally, a 4 nm-thick GaN capping layer.
To fabricate this device, Mesa isolation was performed with an ICP-RIE system with Cl 2 as the etching gas.Source/drain Ohmic contacts were formed with e-beam evaporation and lift-off of Ti/Al/Ni/Au (20 nm/120 nm/25 nm/100 nm) metal stack, followed by rapid thermal annealing at 800 • C in N 2 for 60 s.After removing the photoresist and carrying out a surface cleaning process to remove impurities and reduce surface dangling bonds, a 50 nm-thick Si 3 N 4 film was immediately grown by plasma-enhanced chemical vapor deposition (PECVD) and deployed as the gate insulator.
The gate electrode was formed with Ni/Au (50 nm/450 nm) deposited upon the top of the dielectric stack.Finally, the device was covered with a 450 nm-thick PECVD Si 3 N 4 film.The device geometry consists of L GD = 16 µm, L GS = 3 µm, gate length = 1 µm and gate width = 50 µm.Before starting with the step-stress experiments, the various static characteristics (Figure 3) such as I DS -V DS , I DS -V GS , G m -V GS , and leakage current for both the devices were evaluated and sorted to obtain well matched degradation characteristics; we verified that devices belonging to the same wafer presented consistent and reproducible behavior.The devices belonging to the center region of a wafer were cut out and divided into three groups (n = 10/group) for this study; a total of approximately 40 devices were tested [28].
Energies 2017, 10, 233 4 of 12 stack.Finally, the device was covered with a 450 nm-thick PECVD Si3N4 film.The device geometry consists of LGD = 16 μm, LGS = 3 μm, gate length = 1 μm and gate width = 50 μm.Before starting with the step-stress experiments, the various static characteristics (Figure 3) such as IDS-VDS, IDS-VGS, Gm-VGS, and leakage current for both the devices were evaluated and sorted to obtain well matched degradation characteristics; we verified that devices belonging to the same wafer presented consistent and reproducible behavior.The devices belonging to the center region of a wafer were cut out and divided into three groups (n = 10/group) for this study; a total of approximately 40 devices were tested [28].stack.Finally, the device was covered with a 450 nm-thick PECVD Si3N4 film.The device geometry consists of LGD = 16 μm, LGS = 3 μm, gate length = 1 μm and gate width = 50 μm.Before starting with the step-stress experiments, the various static characteristics (Figure 3) such as IDS-VDS, IDS-VGS, Gm-VGS, and leakage current for both the devices were evaluated and sorted to obtain well matched degradation characteristics; we verified that devices belonging to the same wafer presented consistent and reproducible behavior.The devices belonging to the center region of a wafer were cut out and divided into three groups (n = 10/group) for this study; a total of approximately 40 devices were tested [28].The devices are mounted on AlN substrate (180 W/m•K) to ensure that no electrons diffuse into channels.All the experiments are performed in a probe station with a thermally controlled stage, and Fluorinert™ (FC-40) is applied on the device surface to avoid arcing and water-assisted electrochemical reactions caused by environmental conditions.For devices that are soldered into the substrate, a thin attachment layer of sintered nano-silver is applied to the bottom of the substrate to ensure that the least amount of contact resistance exists between the substrate and the lead-frame.Thermal grease is also used at the interface between the ceramic-attached lead-frame and the stage.
This study focuses on the impact of gate leakage current in reverse bias I Goff , the degradation of the on-resistance R on , the bias gate current I G_stress obtained at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain) for each stress cycle, and the shift in threshold voltage V th .However, the degradation in I Dmax is found to be recoverable and related to thermally-assisted electron de-trapping.This has been suggested to be resulting from the device reaching a new steady-state as trapping and de-trapping reach equilibrium.Using step-stress methods of the terminals of gate, drain and source terminal; a detailed study is performed to observe device degradation that limits safe operation in the off-state.

Short-Term Step-Stress Experiment
Under high reverse gate bias conditions, crystallographic defects and even cracking occur as a result of the inverse piezoelectric effect [29,30].The presence of a strong electric field in the piezoelectric GaN and AlGaN leads to additional mechanical stress that is concentrated at the gate edge across the AlGaN barrier [31].The change in AlGaN elastic energy can produce dislocations (extended defects).By inserting an insulator under the gate metal such as ALD Al 2 O 3 and PECVD Si 3 N 4 , MIS-gate HEMTs are highly preferred over Schottky-gate HEMTs for high-voltage power switches.The MIS-gate structure is effective for suppressing the gate leakage current and thus improving long-term reliability.However, this MIS-gate technology still remains challenging in terms of obtaining low and stable gate leakage characteristics and achieving sufficient long-term robustness simultaneously.
To study the impact of negative gate-bias (V GS ) stress on the performance of Si 3 N 4 gate dielectric, the device is step-stressed at V DS = 0 V (shorted source and drain) with increasing values of |V GS | from 25 V to 135 V for harsh bias condition, as shown in Figure 4a.At each step, the device is stressed for 30 s.Since the voltage across the drain and source is constant throughout the experiment, both the drain and source sides of the gate are stressed with increasing electric fields over time.
Energies 2017, 10, 233 5 of 12 The devices are mounted on AlN substrate (180 W/m•K) to ensure that no electrons diffuse into channels.All the experiments are performed in a probe station with a thermally controlled stage, and Fluorinert™ (FC-40) is applied on the device surface to avoid arcing and water-assisted electrochemical reactions caused by environmental conditions.For devices that are soldered into the substrate, a thin attachment layer of sintered nano-silver is applied to the bottom of the substrate to ensure that the least amount of contact resistance exists between the substrate and the lead-frame.Thermal grease is also used at the interface between the ceramic-attached lead-frame and the stage.
This study focuses on the impact of gate leakage current in reverse bias IGoff, the degradation of the on-resistance Ron, the bias gate current IG_stress obtained at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain) for each stress cycle, and the shift in threshold voltage Vth.However, the degradation in IDmax is found to be recoverable and related to thermally-assisted electron de-trapping.This has been suggested to be resulting from the device reaching a new steady-state as trapping and de-trapping reach equilibrium.Using step-stress methods of the terminals of gate, drain and source terminal; a detailed study is performed to observe device degradation that limits safe operation in the off-state.

Short-Term Step-Stress Experiment
Under high reverse gate bias conditions, crystallographic defects and even cracking occur as a result of the inverse piezoelectric effect [29,30].The presence of a strong electric field in the piezoelectric GaN and AlGaN leads to additional mechanical stress that is concentrated at the gate edge across the AlGaN barrier [31].The change in AlGaN elastic energy can produce dislocations (extended defects).By inserting an insulator under the gate metal such as ALD Al2O3 and PECVD Si3N4, MIS-gate HEMTs are highly preferred over Schottky-gate HEMTs for high-voltage power switches.The MIS-gate structure is effective for suppressing the gate leakage current and thus improving long-term reliability.However, this MIS-gate technology still remains challenging in terms of obtaining low and stable gate leakage characteristics and achieving sufficient long-term robustness simultaneously.
To study the impact of negative gate-bias (VGS) stress on the performance of Si3N4 gate dielectric, the device is step-stressed at VDS = 0 V (shorted source and drain) with increasing values of |VGS| from 25 V to 135 V for harsh bias condition, as shown in Figure 4a.At each step, the device is stressed for 30 s.Since the voltage across the drain and source is constant throughout the experiment, both the drain and source sides of the gate are stressed with increasing electric fields over time.Figure 4b-d shows a positive shift in threshold voltage Vth (up to 30%), a corresponding increase in dynamic Ron (up to 200%), and an increase in gate current (IG_stress, and IGoff) observed in a representative sample during the step-stress experiment with VDS = 0 V. Starting with the step at 116 V, a sudden increase in IG_stress is observed, as well as a permanent increase in both gate currents several orders of magnitude at the end of the 118 V step (burnout failure).Gate current (IG_stress) first increases, following the increase in IGoff, and then increases due to the creation of gate-edge degradation.In an experiment of this kind, the evolution of IGoff during stress reveals that for low values of |VGS|, IGoff tends to drop with a given stress step.This can be attributed to trapping associated with defects at the gate edges, where the electric field is highest [32].The defects promote the injection of electrons from the gate into the Si3N4 insulating layer and at the Si3N4/GaN interface.In the degraded device where localized vertical leakage paths exist under the gate electrode, a significant number of electrons is injected from the gate electrode to the Si3N4 insulating layer and the insulating layer is eventually driven into breakdown (from |VGS| = 65 V), due to tunneling and subsequent trapping within the dielectric over layer.
It is interesting to see evidence of stress-induced gate current (IG_stress and IGoff) at high gate voltage and a critical gate voltage (|VGS| = 65 V) beyond which IGoff degrades suddenly.Figure 5 shows the trapping and degradation mechanisms in GaN-Based MIS-HEMTs [33].The injection of electrons towards the AlGaN layer under the gate electrode induces an increase in Ron and a positive shift in threshold voltage Vth until the critical voltage is reached.The accumulation of negative charge in the AlGaN layer forms a virtual gate that depletes part of the channel.During the stress period (from |VGS|= 25 to 65 V), ∆Vth increases with |VGS| and eventually saturates.Stressing beyond the critical gate voltage creates interface traps at the SiN/AlGaN interface in the gate-source access region, while no significant changes are observed for both drain currents (IDoff and ID_stres), as shown in Figure 4c,d.The injection of electrons induces an increase in Ron and no obvious change in threshold voltage Vth.These traps become a pathway for electrons to flow from the gate to the source.During stress, when electrons refill the interface traps, both IGoff and IG_stress sharply increase.This indicated that the traps are mainly located at the SiN/AlGaN interface.Figure 4b-d shows a positive shift in threshold voltage V th (up to 30%), a corresponding increase in dynamic R on (up to 200%), and an increase in gate current (I G_stress, and I Goff ) observed in a representative sample during the step-stress experiment with V DS = 0 V. Starting with the step at 116 V, a sudden increase in I G_stress is observed, as well as a permanent increase in both gate currents several orders of magnitude at the end of the 118 V step (burnout failure).Gate current (I G_stress ) first increases, following the increase in I Goff , and then increases due to the creation of gate-edge degradation.In an experiment of this kind, the evolution of I Goff during stress reveals that for low values of |V GS |, I Goff tends to drop with a given stress step.This can be attributed to trapping associated with defects at the gate edges, where the electric field is highest [32].The defects promote the injection of electrons from the gate into the Si 3 N 4 insulating layer and at the Si 3 N 4 /GaN interface.In the degraded device where localized vertical leakage paths exist under the gate electrode, a significant number of electrons is injected from the gate electrode to the Si 3 N 4 insulating layer and the insulating layer is eventually driven into breakdown (from |V GS | = 65 V), due to tunneling and subsequent trapping within the dielectric over layer.
It is interesting to see evidence of stress-induced gate current (I G_stress and I Goff ) at high gate voltage and a critical gate voltage (|V GS | = 65 V) beyond which I Goff degrades suddenly.Figure 5 shows the trapping and degradation mechanisms in GaN-Based MIS-HEMTs [33].The injection of electrons towards the AlGaN layer under the gate electrode induces an increase in R on and a positive shift in threshold voltage V th until the critical voltage is reached.The accumulation of negative charge in the AlGaN layer forms a virtual gate that depletes part of the channel.During the stress period (from |V GS |= 25 to 65 V), ∆V th increases with |V GS | and eventually saturates.Stressing beyond the critical gate voltage creates interface traps at the SiN/AlGaN interface in the gate-source access region, while no significant changes are observed for both drain currents (I Doff and I D_stres ), as shown in Figure 4c,d.The injection of electrons induces an increase in R on and no obvious change in threshold voltage V th .These traps become a pathway for electrons to flow from the gate to the source.During stress, when electrons refill the interface traps, both I Goff and I G_stress sharply increase.This indicated that the traps are mainly located at the SiN/AlGaN interface.Also of interest is the fact that IG_stress exhibits different degradation behavior before and after biasing to the critical gate voltage.To verify the origin of the observed degradation caused by high electric field, two possible off-state failure mechanisms are investigated.One is a vertical injection of electrons from the gate into the Si3N4 insulating layer, due to trap assisted tunneling, and the other is a lateral component, also due to tunneling, which involves injecting electrons directly into trap states at the SiN/AlGaN interface.The injection of electrons from the gate electrode into interface states present in the gate-source region extends laterally toward the source contact with increasing gate voltage.Degradation is detected as a non-recoverable increase in the gate current (step at |VGS| = 116 V and beyond).These results also indicated that electrons injected into surface states near the gate terminal form an extended virtual gate near the gate terminal edge extending the depletion region of the device channel.This is consistent with the positive Vth shift and corresponding increase in Ron.
Figure 6a shows the off-state step-stress experiments carried out under normal use conditions.Identical devices are also step-stressed at VGS = −20 V (off-state) with increasing values of VDS from 1 to 150 V, with a step size of 1 V (3 min at each step).To obtain enough degradation for a reasonable analysis of device reliability, limited by the instrument's capabilities (voltage rating V), accelerated life testing involves applying the VDS bias stress for an extended period of time (3 min).In this approach, the voltage across the gate and source (VGS) is constant throughout the experiment and a high electric field peak appears at the drain side edge of the gate with the field penetrating deeply into the buffer.
Referring to Figure 6b, significant degradation takes place in Vth and Ron while a minor increase in IG_stress is observed until the applied bias voltage (VDS) exceeds 114 V.As the drain bias voltage (VDS) increases, a significant increase of Vth and RON indicates that the applied electric field increases the probability for the trapped electrons both at the surface (high electric field between gate and drain) and in the buffer (high vertical field from the drain directed towards the substrate); these trap effects are due to the increased injection of electrons from the gate electrode toward the gate-drain surface (lateral trapping) and from the substrate to the buffer (vertical trapping) simultaneously [34].In-situ passivation combined with buffer optimization is a necessary step toward the reduction of off-state stress-induced change in Vth and RON ratio.There is a significant degradation up to around VDS = 114 V.At this critical degradation voltage, change in all figures of merit starts sharply and degradation increases as the stress experiment proceeds.Similar to a degradation mechanism in traditional Schottky gate HEMTs, a sharp increase of IG_stress and IGoff at a certain voltage has been observed in MIS-HEMTs.Also of interest is the fact that I G_stress exhibits different degradation behavior before and after biasing to the critical gate voltage.To verify the origin of the observed degradation caused by high electric field, two possible off-state failure mechanisms are investigated.One is a vertical injection of electrons from the gate into the Si 3 N 4 insulating layer, due to trap assisted tunneling, and the other is a lateral component, also due to tunneling, which involves injecting electrons directly into trap states at the SiN/AlGaN interface.The injection of electrons from the gate electrode into interface states present in the gate-source region extends laterally toward the source contact with increasing gate voltage.Degradation is detected as a non-recoverable increase in the gate current (step at |V GS | = 116 V and beyond).These results also indicated that electrons injected into surface states near the gate terminal form an extended virtual gate near the gate terminal edge extending the depletion region of the device channel.This is consistent with the positive V th shift and corresponding increase in R on .

SiN
Figure 6a shows the off-state step-stress experiments carried out under normal use conditions.Identical devices are also step-stressed at V GS = −20 V (off-state) with increasing values of V DS from 1 to 150 V, with a step size of 1 V (3 min at each step).To obtain enough degradation for a reasonable analysis of device reliability, limited by the instrument's capabilities (voltage rating 200 V), accelerated life testing involves applying the V DS bias stress for an extended period of time (3 min).In this approach, the voltage across the gate and source (V GS ) is constant throughout the experiment and a high electric field peak appears at the drain side edge of the gate with the field penetrating deeply into the buffer.
Referring to Figure 6b, significant degradation takes place in V th and R on while a minor increase in I G_stress is observed until the applied bias voltage (V DS ) exceeds 114 V.As the drain bias voltage (V DS ) increases, a significant increase of V th and R ON indicates that the applied electric field increases the probability for the trapped electrons both at the surface (high electric field between gate and drain) and in the buffer (high vertical field from the drain directed towards the substrate); these trap effects are due to the increased injection of electrons from the gate electrode toward the gate-drain surface (lateral trapping) and from the substrate to the buffer (vertical trapping) simultaneously [34].In-situ passivation combined with buffer optimization is a necessary step toward the reduction of off-state stress-induced change in V th and R ON ratio.There is a significant degradation up to around V DS = 114 V.At this critical degradation voltage, change in all figures of merit starts sharply and degradation increases as the stress experiment proceeds.Similar to a degradation mechanism in traditional Schottky gate HEMTs, a sharp increase of I G_stress and I Goff at a certain voltage has been observed in MIS-HEMTs.
The previous measurements were carried out starting from a negative gate voltage or from a high V DG quiescent point; thus, it is possible to induce strong trapping both under the gate and in the gate-drain access region, observing the onset of electric field-induced degradation of selected DC figures of merit.Also of interest is the behavior of the GaN cascoded structure which needs to be considered during the high current turn-off condition.With this configuration, the gate-to-source Energies 2017, 10, 233 8 of 12 voltage of GaN MIS-HEMT is equal to the source-to-drain voltage of Si MOSFET.The interaction between the two discrete devices (Si MOSFET and GaN MIS-HEMT) may result in instability due to the unavoidable package parasitic inductance.The package influence during high current turn-off could be a significant internal parasitic ringing which may cause GaN device failure [35].The gate isolation barrier of GaN MIS-HEMT will usually break before Si MOSFET reaches avalanche.This leads to an immediate damage of the GaN cascode.Considering the dynamic avalanche generation, the gate isolation barrier will easily break due to high voltage peaks on the GaN source-gate access region.The issue of avalanche robustness deserves special mention.The previous measurements were carried out starting from a negative gate voltage or from a high VDG quiescent point; thus, it is possible to induce strong trapping both under the gate and in the gate-drain access region, observing the onset of electric field-induced degradation of selected DC figures of merit.Also of interest is the behavior of the GaN cascoded structure which needs to be considered during the high current turn-off condition.With this configuration, the gate-to-source voltage of GaN MIS-HEMT is equal to the source-to-drain voltage of Si MOSFET.The interaction between the two discrete devices (Si MOSFET and GaN MIS-HEMT) may result in instability due to the unavoidable package parasitic inductance.The package influence during high current turn-off could be a significant internal parasitic ringing which may cause GaN device failure [35].The gate isolation barrier of GaN MIS-HEMT will usually break before Si MOSFET reaches avalanche.This leads to an immediate damage of the GaN cascode.Considering the dynamic avalanche generation, the gate isolation barrier will easily break due to high voltage peaks on the GaN source-gate access In this work, a novel step-stress methodology is presented to study the potential failure mode of the cascode GaN device as shown in Figure 7a.To show that the gate degradation occurs solely in regions with high electric field, the devices are stressed by reversing the source/drain terminals.The gate terminal is grounded in this configuration.In this experiment, the V SG is stepped in 0.5 V increments for 30 s per step from 22 V to 122 V while keeping V DG = 20 V under pinched-off condition.In Figure 7b, failure occurred at a low voltage of 105 V. MIS devices are functional throughout the stress.At V SG = 105 V, the I G_stress and I Goff suddenly increase and V th rapidly becomes more negative causing the device to turn-on.The V th shift changes from positive to negative direction with off-state stress beyond a certain critical voltage of V SG = 63 V.
regions with high electric field, the devices are stressed by reversing the source/drain terminals.The gate terminal is grounded in this configuration.In this experiment, the VSG is stepped in 0.5 V increments for 30 s per step from 22 V to 122 V while keeping VDG = 20 V under pinched-off condition.In Figure 7b, failure occurred at a low voltage of 105 V. MIS devices are functional throughout the stress.At VSG = 105 V, the IG_stress and IGoff suddenly increase and Vth rapidly becomes more negative causing the device to turn-on.The Vth shift changes from positive to negative direction with off-state stress beyond a certain critical voltage of VSG = 63 V. Figure 7c shows the degradation evolution of 3-terminal I-V characteristics of ID_stress, IG_stress, and IS_stress during this stress experiment.It is interesting to show that both ID_stress and IS_stress exhibit a sharp rise around the same critical voltage denoted in Figure 7b, while IG_stress presents a negligible change.This phenomenon implies that degradation takes place at dielectric/III-N barrier interface in the access region between the gate and source.Furthermore, 3-terminal I-V characteristics (IDoff, IGoff, and ISoff), described in Figure 7d, show negligible change, which suggest SiN/AlGaN interface state generation early in the stress experiment in addition to electron trapping in the SiN passivation or the AlGaN barrier.The findings may explain by potential failure modes of the cascode GaN-based switch from internal parasitic ringing under hard-switching turn-off condition.Short-term stress is enough to produce significant structural degradation if the stress voltage (VSG) is higher than the critical voltage (VCRI).This reliability issue needs to be taken into consideration while D-mode MIS HEMTs are used in cascode-switch application.Figure 7c shows the degradation evolution of 3-terminal I-V characteristics of I D_stress , I G_stress , and I S_stress during this stress experiment.It is interesting to show that both I D_stress and I S_stress exhibit a sharp rise around the same critical voltage denoted in Figure 7b, while I G_stress presents a negligible change.This phenomenon implies that degradation takes place at dielectric/III-N barrier interface in the access region between the gate and source.Furthermore, 3-terminal I-V characteristics (I Doff , I Goff, and I Soff ), described in Figure 7d, show negligible change, which suggest SiN/AlGaN interface state generation early in the stress experiment in addition to electron trapping in the SiN passivation or the AlGaN barrier.The findings may explain by potential failure modes of the cascode GaN-based switch from internal parasitic ringing under hard-switching turn-off condition.Short-term stress is enough to produce significant structural degradation if the stress voltage (V SG ) is higher than the critical voltage (V CRI ).This reliability issue needs to be taken into consideration while D-mode MIS HEMTs are used in cascode-switch application.

Conclusions
Leakage-current reduction and breakdown voltage increase in GaN HEMTs are achieved by the incorporation of a suitable SiN gate dielectric layer.This paper reports on an extensive analysis of the reliability of experimental MIS-HEMTs submitted to off-state stress.A synchronized stress-characterization technique has been developed to investigate the degradation modes and mechanisms under three off-state quiescent voltage stress conditions.Results provide information on the origin of the changes in key figures of merit occurring during stress time and on the critical stress voltage for the onset of prominent degradation, which is ascribed to a defect percolation process.The step-stress strategies provide some valuable insights for future design optimization of both depletion-mode and cascode configuration GaN-based power switches.A comprehensive investigation on the origin and underlying physical mechanisms of bulk and interface traps needs to be further carried out.

Figure 1 .
Figure 1.(a) Control voltages for step-stress experiments performed in this study.The device is stressed for a length of time: step-stress on gate and source (30 s) and step-stress on drain (3 min); bias is repeatedly switched to the ON-state for short intervals to evaluate the change in DC figures of merit induced by the OFF-state bias; (b) flow chart of a typical experiment.The device is stressed and regularly characterized in the process.The measurement loop is executed before reaching the critical voltage (key event), wherein irreversible damage to the device occurs.
. Measured at VGS = −20 V and VDS = 0 V. IDoff Drain leakage current.Measured at VGS = −20 V and VDS = 0 V. ISoff Source leakage current.Measured at VGS = −20 V and VDS = 0 V. IG_stress Gate stress current.Measured at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain).ID_stress Drain stress current.Measured at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain).IS_stress Source stress current.Measured at the 29th second (step-stress on gate and source) or 179th second (step-stress on drain).IDlin Linear-regime drain current.Measured at VGS = 0 V and VDS = 1 V. IDmax Maximum drain current.Measured at VGS = 0 V and VDS = 10 V. Vth Threshold voltage.Defined as VGS at IDS = 1 mA/mm for VDS = 1 V. Ron

Figure 1 .
Figure 1.(a) Control voltages for step-stress experiments performed in this study.The device is stressed for a length of time: step-stress on gate and source (30 s) and step-stress on drain (3 min); bias is repeatedly switched to the ON-state for short intervals to evaluate the change in DC figures of merit induced by the OFF-state bias; (b) flow chart of a typical experiment.The device is stressed and regularly characterized in the process.The measurement loop is executed before reaching the critical voltage (key event), wherein irreversible damage to the device occurs.

Figure 4 .
Figure 4. (a) Sketch of MIS-HEMT under step-stress of the gate reverse bias at V DS = 0 V from |V GS | = 25 to 135 V in 0.5 V.A high-field appears at the gate edges on both the drain and source sides; (b) Electrical figures of merit as a function of |V GS |: percent increase in dynamic R on (drain current degradation) and percent positive shift in V th (left scale).The inset in (b) depicts that a large positive V th shift is induced during stress, changing it from −18.95 to −12.45 V; (c) 2-terminals I-V characteristics acquired during stress.A sudden increase of gate current (I G_stress ) is measured at |V GS | = 65 V; (d) 2-terminals leakage currents acquired after stress.

Figure 5 .
Figure 5. Schematic diagram of a device illustrates possible electron trapping that mainly depletes 2DEG in the channel under high voltage off-state gate stress and causes Ron degradation.

5 .
Schematic diagram of a device illustrates possible electron trapping that mainly depletes 2DEG in the channel under high voltage off-state gate stress and causes R on degradation.

Figure 6 .
Figure 6.(a) Sketch of MIS-HEMT under drain voltage step-stress at off-state from VDS = 1 V to 150 V in 1 V step (3 min per step).A high-field appears at the drain-side edge of the gate electrode; (b) Change in normalized Ron, Vth, IG_stress, and IGoff as a function of stress voltage.There is a negligible degradation up to around VDS = 114 V.At this critical voltage, degradation in all figures of merit starts sharply and increases as the stress experiment proceeds.

9 Figure 6 .
Figure 6.(a) Sketch of MIS-HEMT under drain voltage step-stress at off-state from V DS = 1 V to 150 V in 1 V step (3 min per step).A high-field appears at the drain-side edge of the gate electrode; (b) Change in normalized R on , V th , I G_stress , and I Goff as a function of stress voltage.There is a negligible degradation up to around V DS = 114 V.At this critical voltage, degradation in all figures of merit starts sharply and increases as the stress experiment proceeds.

Figure 7 .
Figure 7. (a) Sketch of MIS-HEMTs under source voltage step-stressing at off-state from VSG = 22 V to 122 V in 0.5 V step (measured at VDG = 20 V); (b) Normalized Vth, Ron (left axis), IG_stress and IGoff (right axis) as a function of VSG in a VDG = 20 V step-stress experiment; (c) 3-terminals I-V characteristics acquired during stress.A sudden increase of drain (ID_stress) and source (IS_stress) current is measured at VSG = 67 V; (d) 3-terminals leakage currents acquired after stress.

9 Figure 7 .
Figure 7. (a) Sketch of MIS-HEMTs under source voltage step-stressing at off-state from V SG = 22 V to 122 V in 0.5 V step (measured at V DG = 20 V); (b) Normalized V th , R on (left axis), I G_stress and I Goff (right axis) as a function of V SG in a V DG = 20 V step-stress experiment; (c) 3-terminals I-V characteristics acquired during stress.A sudden increase of drain (I D_stress ) and source (I S_stress ) current is measured at V SG = 67 V; (d) 3-terminals leakage currents acquired after stress.

Table 1 .
Device electrical parameters monitored during characterization.

Table 1 .
Device electrical parameters monitored during characterization.