1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.


Introduction
In the last decade, more and more attention has been paid to the current-mode technique in electronic circuit design.This technique can offer advantages in certain applications in terms of high-speed operation, bandwidth, accuracy, and simplified signal processing.Arithmetic operations, such as the addition, subtraction, and multiplication of signals in current forms are simpler compared to voltage-mode circuits.In other words, the addition and subtraction of signals in voltage forms based on operational amplifiers (op-amps) suffer from many passive resistors [1].Moreover, current-mode circuits can be designed almost exclusively using current-mode devices because they do not need high current gain or high-precision passive elements.For example, an op-amp-based inverting amplifier offers a high-precision transfer function when there is high voltage gain (infinite for the ideal case) and high-precision passive elements are available [1].
Nowadays, CMOS active devices operating with low supply voltage and power consumption are of interest because they are required for applications in portable electronics, sensors, and biomedical systems.Power consumption is also a key parameter for researchers in the design of conventional electronic circuits.Focusing on current conveyors, low-voltage and low-power current conveyors are available according to the open literature, i.e., CCII in [18][19][20], DDCC in [21,22], FDCCII in [23][24][25], and FBCCII in [26][27][28].
Therefore, this paper presents low-voltage low-power current conveyors that offer current gain between the x-and z-terminals.The electronically tunable current conveyors have been designed using low-voltage, low-power, multiple-input OTAs (MI-OTAs).The current gain of the proposed electronically tunable current conveyor can be controlled by adjusting the ratio of transconductances of the current conveyors.The MI-OTA is realized using the multiple-input bulk-driven MOS transistor (MIBD-MOST) technique to obtain minimum voltage supply and power consumption [48].Recently, multiple-input OTAs have been utilized in many interesting applications that exhibit a minimal number of active elements, power supply, and reduced complexity [48,49].By using a MI-OTA-based electronically tunable current conveyor, we can obtain an electronically tunable differential difference current conveyor (EDDCC) and an electronically tunable second-generation current conveyor (ECCII).The EDDCC has been used to realize the voltage-to-current (V-to-I) converter and current-mode universal filter.The performances of the proposed current conveyors and their applications were evaluated in the Cadence environment using 0.18 µm CMOS technology from TSMC.The proposed current conveyors use ±0.5 V of power supply and consume 90 µW of power.The EDDCC has also been implemented in the form of a breadboard connection in order to perform experimental measurements.The proposed EDDCC can be used for voltage-and current-mode sensor applications or as a conditioning circuit for processing biological signals that require low supply voltages and reduced power consumption.
The paper is organized as follows: Section 2 describes the structure of the MI-OTA and the proposed EDDCC.The applications of the EDDCC as a V-to-I converter and currentmode universal filter are shown in Section 3. The simulation results of the proposed ECCII, the V-to-I converter, and the universal filter are shown in Section 4. Section 5 describes the experimental measurement results of the EDDCC.Finally, Section 6 concludes the paper.

The Multiple-Input Operational Transconductance Amplifier
The symbol and the CMOS realization of the multiple-input OTA proposed in this work are shown in Figure 1a and 1b, respectively.The output current I out can be described by the following equation: where g m is the small-signal transconductance.
conditioning circuit for processing biological signals that require low supply voltages a reduced power consumption.The paper is organized as follows: Section 2 describes the structure of the MI-OT and the proposed EDDCC.The applications of the EDDCC as a V-to-I converter and cu rent-mode universal filter are shown in Section 3. The simulation results of the propos ECCII, the V-to-I converter, and the universal filter are shown in Section 4. Section 5 d scribes the experimental measurement results of the EDDCC.Finally, Section 6 conclud the paper.

The Multiple-Input Operational Transconductance Amplifier
The symbol and the CMOS realization of the multiple-input OTA proposed in th work are shown in Figure 1a and 1b, respectively.The output current Iout can be describ by the following equation: The practical realization of multiple-input devices is shown in Figure 2. Note th multiple inputs were realized using a capacitive voltage divider/analog summer, co posed of the capacitors CBi.The large resistors RMOSi, connected in parallel to the capacito are used to properly bias the bulk terminal of the transistor for DC.They are realized an anti-parallel connection of two minimum-size MOS transistors operating in the cutregion.Due to their high resistances, their impact on the voltage transfer function of t input divider can be neglected for working frequencies of ω > 1/CBiRMOSi.In such a ca the AC voltage at the bulk terminal of the device can be expressed as follows: Overall, the circuit can be considered as a folded cascode OTA, with the input bulkdriven differential pair M 1 , M 2 linearized using the triode region transistors M 1s and M 2s .A similar linearization technique was proposed by Krummenacher and Joehl [50] for a gate-driven transconductor operating in the strong inversion region.Figure 1 presents a BD counterpart of the circuit, operating in weak inversion, and with the input transistors replaced by multiple-input devices.Such a version of the input stage was first proposed and verified experimentally in [49].
The practical realization of multiple-input devices is shown in Figure 2. Note that multiple inputs were realized using a capacitive voltage divider/analog summer, composed of the capacitors C Bi .The large resistors R MOSi , connected in parallel to the capacitors, are used to properly bias the bulk terminal of the transistor for DC.They are realized as an anti-parallel connection of two minimum-size MOS transistors operating in the cut-off region.Due to their high resistances, their impact on the voltage transfer function of the input divider can be neglected for working frequencies of ω > 1/C Bi R MOSi .In such a case, the AC voltage at the bulk terminal of the device can be expressed as follows: where n is the number of inputs and β i is the voltage gain of the input capacitive divider from ith input.Neglecting second-order effects, β i can be expressed as follows: Note that with identical C Bi , β i = 1/n for i = 1, . .., n.
where n is the number of inputs and βi is the voltage gain of the input capacitive divider from ith input.Neglecting second-order effects, βi can be expressed as follows: Note that with identical CBi, βi = 1/n for i = 1, ..., n.
The MOS transistor with a capacitive input divider can be seen as a new active device called a bulk-driven multiple-input MOS transistor [48].The use of such devices enables the realization of input signal summation (see Equation ( 1)) without the need for a second input stage, thus simplifying the overall structure and saving dissipated power.
Regarding the input stage of the OTA, its linearity depends on the parameter k, which is defined as follows: The best linearity of the input stage is achieved for k = 0.5 [49], i.e., the same value as for its GD counterpart operating in weak inversion [51].This result does not depend on the value of the biasing current Iset if the operation in weak inversion is provided.
The rest of the OTA structure is rather conventional, with its cascode output stage M5-M12.The transistors M13-M18 are used for biasing purposes.All the transistors in the OTA circuit, except M1s and M2s, should operate in the penthode region.
The small-signal transconductance of the OTA can be expressed as follows [49]: where η = gmb1,2/gm1,2 is the bulk-to-gate transconductance ratio of the input pair at the operating point, np is the subthreshold slope factor for p-channel devices, UT is the thermal potential, and the other symbols are explained earlier.
As can be concluded from (5), the resulting transconductance is attenuated by the input capacitive divider and by the application of bulk-driven devices (note that both the capacitive divider gain β and the bulk-to-gate transconductance ratio η are less than unity).The transconductance is proportional to the biasing current Iset, and thus can be linearly regulated by this current.
The relatively low value of the overall transconductance also decreases the voltage gain of the OTA.However, thanks to the high-resistance cascode output stage, the DC voltage gain of the OTA is maintained at a sufficient level as follows: The input capacitive divider, as well as the bulk-driven technique, extend the linear range of the OTA 1/(βη) times.However, the input-referred noise is increased in the same proportion; thus, the dynamic range of the circuit remains unchanged as compared to its The MOS transistor with a capacitive input divider can be seen as a new active device called a bulk-driven multiple-input MOS transistor [48].The use of such devices enables the realization of input signal summation (see Equation ( 1)) without the need for a second input stage, thus simplifying the overall structure and saving dissipated power.
Regarding the input stage of the OTA, its linearity depends on the parameter k, which is defined as follows: The best linearity of the input stage is achieved for k = 0.5 [49], i.e., the same value as for its GD counterpart operating in weak inversion [51].This result does not depend on the value of the biasing current I set if the operation in weak inversion is provided.
The rest of the OTA structure is rather conventional, with its cascode output stage M 5 -M 12 .The transistors M 13 -M 18 are used for biasing purposes.All the transistors in the OTA circuit, except M 1s and M 2s , should operate in the penthode region.
The small-signal transconductance of the OTA can be expressed as follows [49]: where η = g mb1,2 /g m1,2 is the bulk-to-gate transconductance ratio of the input pair at the operating point, n p is the subthreshold slope factor for p-channel devices, U T is the thermal potential, and the other symbols are explained earlier.
As can be concluded from (5), the resulting transconductance is attenuated by the input capacitive divider and by the application of bulk-driven devices (note that both the capacitive divider gain β and the bulk-to-gate transconductance ratio η are less than unity).The transconductance is proportional to the biasing current I set , and thus can be linearly regulated by this current.
The relatively low value of the overall transconductance also decreases the voltage gain of the OTA.However, thanks to the high-resistance cascode output stage, the DC voltage gain of the OTA is maintained at a sufficient level as follows: The input capacitive divider, as well as the bulk-driven technique, extend the linear range of the OTA 1/(βη) times.However, the input-referred noise is increased in the same proportion; thus, the dynamic range of the circuit remains unchanged as compared to its GD counterpart.Nevertheless, application of the bulk-driven technique, combined with an additional capacitive divider, simplifies the design of analog blocks in an ultra-low-voltage environment and avoids hard nonlinearities for a relatively large input voltage swing.

Proposed Electronically Tunable Current Conveyors
Figure 3a shows the symbol of the electronically tunable second-generation current conveyor (ECCII) and Figure 3b shows the electrical symbol of the electronically tunable differential difference current conveyor (EDDCC).The port characteristics of the ECCII and EDDCC can be expressed, respectively, as follows: The characteristics of the ECCII and EDDCC are similar to the conventional CCII [2] and DDCC [14], except for the current gain between the x-and z-terminals, which can be given by k.Thus, the current gain of EDDCC can be varied by adjusting the ratio of Gmset3/Gmset2 (Gmset3/Gmset2 = k).

V-to-I Converter Using EDDCC
Voltage-to-current (V-to-I) converters, the so-called transconductors, are useful basic building blocks for realizing analog filters, oscillators, gyrators, and instrumentation amplifiers; for examples see [52][53][54][55][56].In this work, the proposed EDDCC has been used to realize the V-to-I converter as shown in Figure 5.The voltage input ( =  −  ) is converted to the output current ( ) by R1 and the current gain can also be adjusted by the current gain k of the EDDCC.The circuit can work as a single-ended V-to-I converter (non-inverting or inverting input) and a differential V-to-I converter.Using (8), the output current of the circuit in Figure 5 can be expressed as follows:   Thus, the current gain of EDDCC can be varied by adjusting the ratio of Gmset3/Gmset2 (Gmset3/Gmset2 = k).

V-to-I Converter Using EDDCC
Voltage-to-current (V-to-I) converters, the so-called transconductors, are useful basic building blocks for realizing analog filters, oscillators, gyrators, and instrumentation amplifiers; for examples see [52][53][54][55][56].In this work, the proposed EDDCC has been used to realize the V-to-I converter as shown in Figure 5.The voltage input ( =  −  ) is converted to the output current ( ) by R1 and the current gain can also be adjusted by the current gain k of the EDDCC.The circuit can work as a single-ended V-to-I converter (non-inverting or inverting input) and a differential V-to-I converter.Using ( 8), the output current of the circuit in Figure 5 can be expressed as follows: To explain the operation of the proposed EDDCC, it is assumed that all OTAs are identical.Using (1), the currents I 1 , I 2 , and I 3 in Figure 4 can be expressed as follows: The OTA 2 of G mset2 is connected as a negative-feedback-like voltage follower (VF) circuit.Thus, V a = V x and this voltage (i.e., V a = V x ) is fed to the inverting input terminal of OTA 1 (G mset1 ).Therefore, this OTA 1 is also operated as a VF.The voltage relationship of the EDDCC in Figure 4 can be given as follows: The addition and subtraction voltage properties of the EDDCC can be obtained.By substituting (10) into (11), the relationship of the currents I x and I z can be expressed as follows: Thus, the current gain of EDDCC can be varied by adjusting the ratio of

Applications of the EDDCC 3.1. V-to-I Converter Using EDDCC
Voltage-to-current (V-to-I) converters, the so-called transconductors, are useful basic building blocks for realizing analog filters, oscillators, gyrators, and instrumentation amplifiers; for examples see [52][53][54][55][56].In this work, the proposed EDDCC has been used to realize the V-to-I converter as shown in Figure 5.The voltage input (V ind = V in+ − V in− ) is converted to the output current (I out ) by R 1 and the current gain can also be adjusted by the current gain k of the EDDCC.The circuit can work as a single-ended V-to-I converter (non-inverting or inverting input) and a differential V-to-I converter.Using ( 8), the output current of the circuit in Figure 5 can be expressed as follows: where k = G mset3 /G mset2 and V ind = V in+ − V in− .Thus, the current gain of EDDCC can be varied by adjusting the ratio of Gmset3/Gmset2 (Gmset3/Gmset2 = k).

V-to-I Converter Using EDDCC
Voltage-to-current (V-to-I) converters, the so-called transconductors, are useful basic building blocks for realizing analog filters, oscillators, gyrators, and instrumentation amplifiers; for examples see [52][53][54][55][56].In this work, the proposed EDDCC has been used to realize the V-to-I converter as shown in Figure 5.The voltage input ( =  −  ) is converted to the output current ( ) by R1 and the current gain can also be adjusted by the current gain k of the EDDCC.The circuit can work as a single-ended V-to-I converter (non-inverting or inverting input) and a differential V-to-I converter.Using (8), the output current of the circuit in Figure 5 can be expressed as follows:

Current-Mode Universal Filter Using EDDCCs
To show the advantages of the current gain of the EDDCC, the EDDCC has been used to realize a current-mode universal filter as shown in Figure 6.The filter employs five EDDCCs, four resistors, and two capacitors.The output terminals possess a high impedance level, and the circuit uses grounded capacitors, which is convenient for the implementation of integrated circuits.The filtering functions can be achieved through the appropriate use of input signals and appropriate selection of output signals.
Using (8) and nodal analysis, the output currents I o1 and I o2 can be expressed as follows: where

Current-Mode Universal Filter Using EDDCCs
To show the advantages of the current gain of the EDDCC, the EDDCC has been used to realize a current-mode universal filter as shown in Figure 6.The filter employs five EDDCCs, four resistors, and two capacitors.The output terminals possess a high impedance level, and the circuit uses grounded capacitors, which is convenient for the implementation of integrated circuits.The filtering functions can be achieved through the appropriate use of input signals and appropriate selection of output signals.Using ( 8) and nodal analysis, the output currents Io1 and Io2 can be expressed as follows: where  =  =  =  .The variants of the current-mode universal filter's filtering functions are shown in Table 1.The proposed filter offers five standard filtering functions.Moreover, the current gains of LP and BP filters can be adjusted by k4 and k5 of EDDCC4 and EDDCC5.
The natural frequency ( ) and quality factor () can be expressed as follows: The variants of the current-mode universal filter's filtering functions are shown in Table 1.The proposed filter offers five standard filtering functions.Moreover, the current gains of LP and BP filters can be adjusted by k 4 and k 5 of EDDCC 4 and EDDCC 5 .Non-Inverting Non-inverting The natural frequency (ω o ) and quality factor (Q) can be expressed as follows: The natural frequency can be given by R T and R 3 (i.e., R T = R 3 ) and the quality factor can be controlled independently and electronically by k 1 of EDDCC 1 .The current gains of LP outputs I o1 and I o2 can be controlled by k 5 and k 4 , respectively.In the case of tuning Q of the BP, the current gain will be equal to 1 if k 1 = k 4 for output I o2 or k 1 = k 5 for output I o1 .The current gain of BP can be obtained if k 4 > k 1 (or k 5 > k 1 ).

Non-Ideal Analysis
Taking into account the non-idealities of the EDDCC, the relationship of the terminal voltages and currents can be rewritten as follows: where α j1 = 1 − ε j1v and ε j1v (|ε k1v | « 1) denotes the voltage-tracking error from V y1 to V x of the jth EDDCC, α j2 = 1 − ε j2v and ε j2v (|ε j2v | « 1) denotes the voltage-tracking error from V y2 to V x of the jth EDDCC, α j3 = 1 − ε j3v and ε j3v (|ε j3v | « 1) denotes the voltage-tracking error from V y3 to V x of the jth EDDCC, and β j = 1 − ε i and ε i (ε i « 1) denotes the output current-tracking error of the jth EDDCC.Using (20), the denominator of the proposed filter becomes as follows: The natural frequency and quality factor become as follows: It follows from ( 22) and ( 23) that tracking errors change the natural frequency and the quality factor.However, it should be noted that the natural frequency can be easily compensated by adjusting k 2 and k 3 and the quality factor can be compensated by adjusting k 1 .
With respect to the parasitic parameters of the EDDCC on the current-mode universal filter, the parasitic impedances R z and C z at the z-terminal [5] are considered.From Figure 6, it can be seen that capacitor C 1 is in parallel with parasitic capacitances C z1 , C z3 and parasitic resistances R z1 , R z3 while capacitor C 2 is in parallel with parasitic capacitance C z2 and parasitic resistances R z2 .The parasitic effects on the pole frequency of the filter can be avoided by choosing

Simulation Results
The proposed EDDCC and its applications were simulated in the Cadence Virtuoso System Design Platform using 0.18µm CMOS technology from TSMC (Taiwan Semiconductor Manufacturing Company, Hsinchu Science Park, Taiwan).The aspect ratios of all MOS transistors of the MI-OTA in Figure 1 are listed in Table 2.The initial values of I set1 = I set2 = 5 µA, while the values of I set3 were changed to adjust the current gain k of the EDDCC.For the EDDCC in Figure 3b, the supply voltage was chosen to be V DD = -V SS = 0.5 V, with the setting currents I set1 = I set2 = I set3 = 5 µA.The power consumption of the EDDCC was 90 µW.show the simulation results of the EDDCC.Figure 7 shows the ideal and simulated DC voltage characteristics V x versus V y1 (V y2 and V y3 are grounded) and V x versus V y2 (V y1 and V y3 are grounded) when V y1 and V y2 were swept from −0.5 V to 0.5 V.A good linearity is evident for V X /V Y1 and V X /V Y2 with the input voltage range ±0.3 V. VB1 = −300 mV, VB2 = 200 mV For the EDDCC in Figure 3b, the supply voltage was chosen to be VDD = -VSS = 0.5 V, with the setting currents Iset1 = Iset2 = Iset3 = 5 µA.The power consumption of the EDDCC was 90 µW.Figures 7-12 show the simulation results of the EDDCC.Figure 7 shows the ideal and simulated DC voltage characteristics Vx versus Vy1 (Vy2 and Vy3 are grounded) and Vx versus Vy2 (Vy1 and Vy3 are grounded) when Vy1 and Vy2 were swept from −0.5 V to 0.5 V.A good linearity is evident for VX/VY1 and VX/VY2 with the input voltage range ±0.3 V.
Figure 8a shows the ideal and simulated DC current characteristics Iz versus Ix (with k = 1) when IX was swept from −10 µA to +10 µA.The curves overlap in the range of ±9 µA. Figure 8b shows the Iz versus Ix for different k with a constant Iset1,2= 5 µA and varied Iset3= (1.25, 2.5, 5, 10, 20, 40) µA.The wide turnability of Iz versus Ix is evident.For the EDDCC in Figure 3b, the supply voltage was chosen to be VDD = -VSS = 0.5 V, with the setting currents Iset1 = Iset2 = Iset3 = 5 µA.The power consumption of the EDDCC was 90 µW.Figures 7-12 show the simulation results of the EDDCC.Figure 7 shows the ideal and simulated DC voltage characteristics Vx versus Vy1 (Vy2 and Vy3 are grounded) and Vx versus Vy2 (Vy1 and Vy3 are grounded) when Vy1 and Vy2 were swept from −0.5 V to 0.5 V.A good linearity is evident for VX/VY1 and VX/VY2 with the input voltage range ±0.3 V.
Figure 8a shows the ideal and simulated DC current characteristics Iz versus Ix (with k = 1) when IX was swept from −10 µA to +10 µA.The curves overlap in the range of ±9 µA. Figure 8b shows the Iz versus Ix for different k with a constant Iset1,2= 5 µA and varied Iset3= (1.25, 2.5, 5, 10, 20, 40) µA.The wide turnability of Iz versus Ix is evident.- - The simulated frequency responses of the voltage gain Vx/Vy1 and the current gain Iz/Ix are shown in Figure 9.The −3 dB bandwidths were 2.81 MHz and 1.58 MHz, and the low-frequency gains were −33.6 mdB and −76 µdB for the voltage Vx/Vy1 and current Iz/Ix gains, respectively.It is worth noting here that a compensation capacitor of 2 pF was connected between the input of Gmset2 to obtain a flat magnitude response of the current gain.Without this compensation capacitor, the peak is around 6 dB.
Process, voltage, temperature (PVT) corners were used to confirm the robustness of the design.The process transistor corners were fast-fast, fast-slow, slow-fast, and slowslow; the process MIM capacitor corners were fast-fast and slow-slow; the voltage supply corners were = ±10% (VDD-VSS); and the temperature corners were −20 °C and 60 °C.The results for the frequency responses of the voltage gain Vx/Vy1 and current gain Iz/Ix are shown in Figure 10.The −3 dB bandwidths were in range of (2.66 to 3) MHz and (1.49 to 1.72) MHz, and the low-frequency gains were in range of (−62.8 to 21.2) mdB and (−124.6 to 79.9) µdB for the voltage Vx/Vy1 and current Iz/Ix gains, respectively.As is evident, the variations are within the acceptable range.
Monte Carlo (MC) analysis was used to perform the statistical analysis to estimate parametric yield and generate information about the performance characteristic of the frequency voltage gain Vx/Vy1 and current gain Iz/Ix of the EDDCC.Figure 11 shows the his- Figure 8a shows the ideal and simulated DC current characteristics I z versus I x (with k = 1) when I X was swept from −10 µA to +10 µA.The curves overlap in the range of ±9 µA. Figure 8b shows the I z versus I x for different k with a constant I set1,2 = 5 µA and varied I set3 = (1.25, 2.5, 5, 10, 20, 40) µA.The wide turnability of I z versus I x is evident.
The simulated frequency responses of the voltage gain V x /V y1 and the current gain I z /I x are shown in Figure 9.The −3 dB bandwidths were 2.81 MHz and 1.58 MHz, and the low-frequency gains were −33.6 mdB and −76 µdB for the voltage V x /V y1 and current I z /I x gains, respectively.It is worth noting here that a compensation capacitor of 2 pF was connected between the input of G mset2 to obtain a flat magnitude response of the current gain.Without this compensation capacitor, the peak is around 6 dB.
Process, voltage, temperature (PVT) corners were used to confirm the robustness of the design.The process transistor corners were fast-fast, fast-slow, slow-fast, and slow-slow; the process MIM capacitor corners were fast-fast and slow-slow; the voltage supply corners were = ±10% (V DD -V SS ); and the temperature corners were −20 • C and 60 • C. The results for the frequency responses of the voltage gain V x /V y1 and current gain I z /I x are shown in Figure 10.The −3 dB bandwidths were in range of (2.66 to 3) MHz and (1.49 to 1.72) MHz, and the low-frequency gains were in range of (−62.8 to 21.2) mdB and (−124.6 to 79.9) µdB for the voltage V x /V y1 and current I z /I x gains, respectively.As is evident, the variations are within the acceptable range.
Monte Carlo (MC) analysis was used to perform the statistical analysis to estimate parametric yield and generate information about the performance characteristic of the frequency voltage gain V x /V y1 and current gain I z /I x of the EDDCC.Figure 11 shows the histogram of a 1000 run MC analysis, showing the mean value to be −187 mdB and −3 mdB, and the standard deviation to be 364 mdB and 434 mdB for the voltage and current gains, respectively.
The simulated frequency response of the current gain I z /I x with a constant I set1,2 = 5 µA and varied I set3 = (1.25, 2.5, 5, 10, 20, 40) µA is shown in Figure 12.The simulated current gain k was varied to (−9.3, −4.48, 0, 4.13, 8.1, 14.22) dB, respectively.This result confirms that the proposed EDDCC can provide the current gain I z /I x .
The simulated frequency dependence of the parasitic impedances of the z-and xterminals is shown in Figure 13.The resistance of the z-terminal is 32.5 MΩ and the resistance of the x-terminal is 284 Ω for I set1,2,3 = 5 µA.
The simulated frequency responses of the voltage gain Vx/Vy1 and the current gain Iz/Ix are shown in Figure 9.The −3 dB bandwidths were 2.81 MHz and 1.58 MHz, and the low-frequency gains were −33.6 mdB and −76 µdB for the voltage Vx/Vy1 and current Iz/Ix gains, respectively.It is worth noting here that a compensation capacitor of 2 pF was connected between the input of Gmset2 to obtain a flat magnitude response of the current gain.Without this compensation capacitor, the peak is around 6 dB.
Process, voltage, temperature (PVT) corners were used to confirm the robustness of the design.The process transistor corners were fast-fast, fast-slow, slow-fast, and slowslow; the process MIM capacitor corners were fast-fast and slow-slow; the voltage supply corners were = ±10% (VDD-VSS); and the temperature corners were −20 °C and 60 °C.The results for the frequency responses of the voltage gain Vx/Vy1 and current gain Iz/Ix are shown in Figure 10.The −3 dB bandwidths were in range of (2.66 to 3) MHz and (1.49 to 1.72) MHz, and the low-frequency gains were in range of (−62.8 to 21.2) mdB and (−124.6 to 79.9) µdB for the voltage Vx/Vy1 and current Iz/Ix gains, respectively.As is evident, the variations are within the acceptable range.
Monte Carlo (MC) analysis was used to perform the statistical analysis to estimate parametric yield and generate information about the performance characteristic of the frequency voltage gain Vx/Vy1 and current gain Iz/Ix of the EDDCC.Figure 11 shows the histogram of a 1000 run MC analysis, showing the mean value to be −187 mdB and −3 mdB, and the standard deviation to be 364 mdB and 434 mdB for the voltage and current gains, respectively.
The simulated frequency dependence of the parasitic impedances of the z-and xterminals is shown in Figure 13.The resistance of the z-terminal is 32.5 MΩ and the resistance of the x-terminal is 284 Ω for Iset1,2,3 = 5 µA.For simulation of the current-mode universal filter shown in Figure 6, the parameters C1 = C2 = 100 pF and R1-4 = 200 kΩ were chosen.The gain k1-5 = 1 was set by choosing the setting current of all EDDCC1-5 to be Iset = 5 µA.However, for the APF, the current of the EDDCC4 was set to Iset3 = 13 µA in order to obtain k = 2.The gain and phase frequency characteristics are shown in Figure 15.The cut-off frequency was 7.9 kHz.For simulation of the current-mode universal filter shown in Figure 6, the parameters C 1 = C 2 = 100 pF and R 1-4 = 200 kΩ were chosen.The gain k 1-5 = 1 was set by choosing the setting current of all EDDCC 1-5 to be I set = 5 µA.However, for the APF, the current of the EDDCC 4 was set to I set3 = 13 µA in order to obtain k = 2.The gain and phase frequency characteristics are shown in Figure 15.The cut-off frequency was 7.9 kHz.For simulation of the current-mode universal filter shown in Figure 6, the parameters C1 = C2 = 100 pF and R1-4 = 200 kΩ were chosen.The gain k1-5 = 1 was set by choosing the setting current of all EDDCC1-5 to be Iset = 5 µA.However, for the APF, the current of the EDDCC4 was set to Iset3 = 13 µA in order to obtain k = 2.The gain and phase frequency characteristics are shown in Figure 15.The cut-off frequency was 7.9 kHz. Figure 16 shows the tuning capability of the gain for the LPF and BPF.The setting current of all EDDCC1-4 was set to be Iset = 5 µA while the k of EDDCC5 was changed by its Iset3 = (5,10,20,40) µA.The low-frequency gain of the LPF was around (0.1, 4, 8, 14) dB and for BPF, it was (0.02, 4.1, 8.1, 14.2) dB.
Figure 17 shows the transient response of the LPF's output (a) and the total harmonic distortion (b) when an input signal at 1 kHz and different amplitudes (0.2, 0.4, 0.6, 0.8, 1, 1.2) µA were applied to the input of the filter.The gain was set to be k = 1.The THD of the output signal was below 1.2% for an input amplitude of 1.2 µA. Figure 16 shows the tuning capability of the gain for the LPF and BPF.The setting current of all EDDCC 1-4 was set to be I set = 5 µA while the k of EDDCC 5 was changed by its I set3 = (5,10,20,40) µA.The low-frequency gain of the LPF was around (0.1, 4, 8, 14) dB and for BPF, it was (0.02, 4.1, 8.1, 14.2) dB.
Figure 17 shows the transient response of the LPF's output (a) and the total harmonic distortion (b) when an input signal at 1 kHz and different amplitudes (0.2, 0.4, 0.6, 0.8, 1, 1.2) µA were applied to the input of the filter.The gain was set to be k = 1.The THD of the output signal was below 1.2% for an input amplitude of 1.2 µA.its Iset3 = (5,10,20,40) µA.The low-frequency gain of the LPF was around (0.1, 4, 8, 14) dB and for BPF, it was (0.02, 4.1, 8.1, 14.2) dB.
Figure 17 shows the transient response of the LPF's output (a) and the total harmonic distortion (b) when an input signal at 1 kHz and different amplitudes (0.2, 0.4, 0.6, 0.8, 1, 1.2) µA were applied to the input of the filter.The gain was set to be k = 1.The THD of the output signal was below 1.2% for an input amplitude of 1.2 µA.current of all EDDCC1-4 was set to be Iset = 5 µA while the k of EDDCC5 was changed by its Iset3 = (5,10,20,40) µA.The low-frequency gain of the LPF was around (0.1, 4, 8, 14) dB and for BPF, it was (0.02, 4.1, 8.1, 14.2) dB.
Figure 17 shows the transient response of the LPF's output (a) and the total harmonic distortion (b) when an input signal at 1 kHz and different amplitudes (0.2, 0.4, 0.6, 0.8, 1, 1.2) µA were applied to the input of the filter.The gain was set to be k = 1.The THD of the output signal was below 1.2% for an input amplitude of 1.2 µA. Figure 18a shows the transient response of the LPF when a sine wave I in = 0.1 µA@1kHz is applied to the input of the filter with k 1-4 = 1 (I set = 5 µA) while the gain k 5 of the EDDCC 5 is varied by its I set3 = (0.5, 10, 15) µA.The output signal of the LPF is inverted and amplified as expected.The THD is shown in Figure 18b, where the 0.19% THD is shown for a 0.4 µA amplitude output signal.
Sensors 2024, 24, x FOR PEER REVIEW 14 of 22 Figure 18a shows the transient response of the LPF when a sine wave Iin = 0.1 µA@1kHz is applied to the input of the filter with k1-4 = 1 (Iset = 5 µA) while the gain k5 of the EDDCC5 is varied by its Iset3 = (0.5, 10, 15) µA.The output signal of the LPF is inverted and amplified as expected.The THD is shown in Figure 18b, where the 0.19% THD is shown for a 0.4 µA amplitude output signal.The PVT corners analysis was also used to confirm the robustness of the filter design.The results for the gains frequency responses of the LPF, HPF, BPF, BSF, and APF with PVT are shown in Figure 19.The curves of each filter response overlap, which confirms the robustness of the filter design.The PVT corners analysis was also used to confirm the robustness of the filter design.The results for the gains frequency responses of the LPF, HPF, BPF, BSF, and APF with PVT are shown in Figure 19.The curves of each filter response overlap, which confirms the robustness of the filter design.The PVT corners analysis was also used to confirm the robustness of the filter design.The results for the gains frequency responses of the LPF, HPF, BPF, BSF, and APF with PVT are shown in Figure 19.The curves of each filter response overlap, which confirms the robustness of the filter design.The proposed EDDCC was compared with previous current conveyors in [18,21,23,33,41], as shown in Table 3.Current conveyors using nonconventional techniques, i.e., the bulk-driven CCII [18], bulk-driven DDCC [21], floating-gate FDCCII [23], and current conveyors providing current gain [33,41] have been selected for comparison.Compared with the current conveyors in [18,21,23], the proposed EDDCC offers current gain between z-and x-terminals.Compared with the ECCIIs in [33,41], the proposed ED-DCC has much lower power consumption and lower supply voltage.It is worth noting that the bandwidth of the proposed EDDCC is sufficient for many applications like sensors and biomedical systems.The proposed EDDCC was compared with previous current conveyors in [18,21,23,33,41], as shown in Table 3.Current conveyors using nonconventional techniques, i.e., the bulkdriven CCII [18], bulk-driven DDCC [21], floating-gate FDCCII [23], and current conveyors providing current gain [33,41] have been selected for comparison.Compared with the current conveyors in [18,21,23], the proposed EDDCC offers current gain between z-and x-terminals.Compared with the ECCIIs in [33,41], the proposed EDDCC has much lower power consumption and lower supply voltage.It is worth noting that the bandwidth of the proposed EDDCC is sufficient for many applications like sensors and biomedical systems.Note: V x /V y1 = V x /V y3 of CCII, GD = gate driven, BD = bulk driven, FG = floating gate.

Experimental Measurements
The proposed EDDCC was implemented using a commercially available LM13700 device (Texas Instruments, Dallas, TX, USA) [57].The LM13700 IC uses a ± 15 V supply voltage and its transconductance is controlled by DC current.Since the EDDCC requires an OTA with four inputs (see Figure 4) and the LM13700 device has two inputs, the EDDCC has been implemented using four LM13700 (see Figure 20), where one provides inputs y 1 and y 2 and another provides input y 3 (the positive input of the LM13700 is y 3 , while the negative input is connected to node x).Therefore, G mset1 transfer has been divided into G mset1a and G mset1b while these transfers are set to an identical value, thus, G mset1a = G mset1b = G mset1 .The output currents of these two OTAs are then summed in node V a .The control of the transconductances of the LM13700 devices, in this particular implementation, is performed by the control DC voltage V set (the control DC current setting transconductances is controlled by these voltages while the value of the resistor R is kept constant (32 kΩ)).The measurement has been performed using a network analyzer Agilent E5061B, generator Keysight 33500B, and oscilloscope Keysight CX3324A with a current probe CX1101A (Keysight, Santa Rosa, CA, USA). Figure 21a represents a block diagram of the used measurement setup while using the network analyzer.A simple I/V converter (shown in Figure 21b) based on a commercially available OPA860 IC (Texas Instruments) [58] has been used.Its function is as follows: the OPA860 serves as a current follower, the output current is transferred into voltage by the resistor R, and the node with the resistor R is separated from the converter output by a buffer (included in the OPA860 IC) for better impedance properties.The converter uses a supply voltage of ±5 V.A photo of the measuring workplace is depicted in Figure 22.The default values for the measurement were selected as follows: R x = 1 kΩ, V set1 = V set2 = −10 V, and V set3 = 0 V.This way, the transconductance of the EDDCC is approximately 1 mS, corresponding to the resistor (1 kΩ) used in the I/V converter for the conversion of the current from the EDDCC back to voltage, which is then fed back to the network analyzer.Note that the resulting voltage transfer corresponds to I z /I x transfer when taking the transfer of the I/V converter as a constant.Figure 23 shows the measured current gain I z /I x for the default setting.The measurement has been performed in band from 10 Hz up to 30 MHz (the analyzer bandwidth range).The −3 dB bandwidth was measured at 1.91 MHz.The gain is −0.53 dB (note that the resulting gain is given by how accurately the transfer of the EDDCC compensates the transfer of the I/V converter).The possibility to change the current gain I z /I x by varying V set3 = (−12.5,−10, −7.5, −5, −2.5, 0, 2.5, 5, 7.5, 10, 12.5) V is shown in Figure 24.The obtained current gain was (−21.11,−11.92, −7.50, −4.57, −2.37, −0.53, 0.86, 2.18, 3.11, 4,18, 5.05) dB, respectively.Figure 25 depicts the dependency of the current gain I z /I x on the control voltage V set3 .It shows a logarithmic dependency of the current gain on the control voltage based on this particular implementation.

Conclusions
In this paper, a new low-voltage low-power electronically tunable current conveyor has been proposed.Unlike previous current conveyors, the current gain of the proposed current conveyor can be controlled electronically.The proposed current conveyor can work as an electronically tunable DDCC (EDDCC) and an electronically tunable CCII (ECCII).To show the advantages of the current gain of the proposed current conveyors, the V-to-I converter and current-mode universal filter were presented, and the simulation results confirm the functionality of the proposed circuits.The proposed EDDCC uses ±0.5 V power supply, consumes 90 µW of power, and has a ±200 mV DC voltage range, ±10 µA DC current range, and 90 µV voltage offset.The proposed circuit can also offer a 2.81 MHz bandwidth of the voltage gain V x /V y , a 1.58 MHz bandwidth of the current gain I z /I x , and a current gain of −9.3 to 14.22 dB when the bias current is varied from 1.25 µA to 40 µA.In addition, the experimental measurements of the EDDCC further support the concept and its functionality.

Figure 4 22 Figure 3 .
Figure4shows the proposed EDDCC using MI-OTAs.This circuit can also work as an ECCII if the y 1 -terminal is the input and the y 2 -and y 3 -terminals are connected to ground.It can further work as an inverting ECCII if the y 2 -terminal is the input and the y 1 -and y 3 -terminals are connected to ground.

Figure 5 .
Figure 5. Applications of the EDDCC to V-to-I converter.

Figure 5 .
Figure 5. Applications of the EDDCC to V-to-I converter.

Figure 6 .
Figure 6.The proposed current-mode universal filter.

Figure 6 .
Figure 6.The proposed current-mode universal filter.

Figure 10 .Figure 9 .Figure 10 .Figure 11 .
Figure 10.Frequency responses of (a) voltage gain V x /V y1 and (b) current gain I z /I x with PVT analysis.

Figure 11 . 22 Figure 12 .
Figure 11.The histogram of the low-frequency (a) voltage gain V x /V y1 and (b) current gain I z /I x with 1000 runs MC analysis.Sensors 2024, 24, x FOR PEER REVIEW 11 of 22

12 .
Frequency response of the current gain I z /I x with different gain k.

Figure 13 .
Figure 13.Frequency dependence of the parasitic impedances of x-and z-terminals.

Figure 18 .
Figure 18.Transient response (a) and THD (b) of the LPF with a 0.1 µA @1 kHz input signal and various k5.

Figure 18 .
Figure 18.Transient response (a) and THD (b) of the LPF with a 0.1 µA @1 kHz input signal and various k 5 .

Figure 19 .
Figure 19.Gain frequency responses of the current-mode filter with PVT corners.

Figure 19 .
Figure 19.Gain frequency responses of the current-mode filter with PVT corners.

Sensors 2024 ,
24,  x FOR PEER REVIEW 16 of 22 the transfer of the I/V converter as a constant.Figure23shows the measured current gain Iz/Ix for the default setting.The measurement has been performed in band from 10 Hz up to 30 MHz (the analyzer bandwidth range).The −3 dB bandwidth was measured at 1.91 MHz.The gain is −0.53 dB (note that the resulting gain is given by how accurately the transfer of the EDDCC compensates the transfer of the I/V converter).

1 Figure 21 .
Figure 21.Block diagram of the measurement setup (a) and the used I/V converter (b).

Figure 23 .
Figure 23.Measured frequency response of the current gain Iz/Ix.

Figure 23 .
Figure 23.Measured frequency response of the current gain Iz/Ix.

Figure 23 .
Figure 23.Measured frequency response of the current gain I z /I x .

Table 1 .
Obtaining variant filtering functions of the current-mode universal filter.

Table 1 .
Obtaining variant filtering functions of the current-mode universal filter.

Table 2 .
Parameters of the components of the MI-OTA.

Table 3 .
Properties comparison of this work with those of previously published ECCIIs.

Table 3 .
Properties comparison of this work with those of previously published ECCIIs.