Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively.

Sensors are used to measure a physical quantity by a transduction mechanism that outputs an electrical quantity (such as resistance, capacitance, inductance, voltage, or current).Such electrical output is usually converted to an analog voltage and acquired by the sensor system with an Analog-to-Digital Converter (ADC).To guarantee high accuracy in the measured analog voltage, the ADC must be carefully calibrated and a front-end analog interface must be designed for signal conditioning.Xie and Wang, in 2023, presented a digital calibration method for a 10 bit successive approximation register (SAR) ADC that achieves a SNR of 66.9 dB, a power consumption of 70 µW, and a sampling rate of 50 kHz [21].An ultrafast and low-cost pipelined ADC testing and calibration method was proposed by Chen et al. in 2019 [22].The proposed technique was implemented on a chip fabricated in 40 nm technology with a power consumption of 10.71 mW and a sampling rate of 125 MHz.Li et al., in 2019, presented a linearity test and calibration method that can be applied to all types of ADCs [23].A self-testing platform with digital calibration technique for SAR ADCs was proposed by Juan et al. in 2016 that improves SNR with a sampling frequency of 18.75 kHz [24].Hernández-Gutiérrez et al., in 2023, presented a low-cost embedded system for high-energy radiation detection applications that is able to detect alfa particles and send the nuclear detection events to a server in the cloud [25].The system is based on an ARM Cortex M4 microcontroller (STM32F407, ST Microelectronics, Geneva, Switzerland) and features an analog circuit for the amplification of the detected photocurrent.A delta-sigma ADC for signal conditioning of automotive piezo-resistive pressure sensors was proposed by Rikan et al. in 2018 [26].A chip was fabricated through a 0.18 µm CMOS process and achieved over 80 dB SNR with a 2.5 MHz sampling frequency and a power consumption of 646 µW.
A research line in the field of sensor data acquisition is devoted to the study of techniques to directly interface the sensor with the digital port of a microcontroller or FPGA without the use of an ADC.These techniques exploit the fact that the digital input pins of a microcontroller or FPGA integrate a Schmitt trigger circuit to remove the noise present on the input signals, thus the sensor can be interfaced to the digital input port using only a few passive components, without the use of an ADC and analog components for signal processing and filtering.This provides advantages in terms of lower cost, area occupation, and power consumption that are of major interest in the case of battery-operated sensor nodes.Many works from literature cover the case of interfacing with resistive, capacitive, and inductive sensors.Reverter, in 2020, proposed a microcontroller-based interface circuit for non-linear resistive sensors [27].The same author, in 2022, proposed a direct approach to connect three-wire [28] and four-wire [29] resistive sensors to the digital port of a microcontroller.A technique to directly connect a capacitively coupled resistive sensor with a microcontroller was presented by Areekath et al. in 2020 [30].Measurement methods for capacitive sensors [31] and lossy capacitive relative humidity sensors [32] based on a direct sensor-to-microcontroller interface circuit were proposed by Czaja in 2020 and 2021.A new type of direct interface circuit for capacitive sensors that is simple in terms of hardware was presented by Hidalgo-López and Castellanos-Ramos in 2022 [33].A microcontroller-based interface circuit for inductive sensors with variable self-inductance was presented by Kokolanski et al. in 2015 [34].The same research group, in 2019, proposed a direct interface circuit for differential inductive sensors achieving nonlinearity errors smaller than 1% and an overall measuring time of a few milliseconds [35].A resolution enhancement method for direct interfacing of inductive sensors was proposed by Asif et al. in 2018 [36].
In the case of sensors featuring an analog output voltage, works from the literature also present the sensor direct interface.Peter et al. in 1998 presented a technique to measure an analog voltage with a microcontroller without an integrated ADC [37].The proposed method requires the presence of an analog comparator (either integrated in the microcontroller or external) and was validated on a Microchip PIC16 microcontroller featuring an integrated analog comparator.This technique was implemented in different microcontrollers and FPGAs.Soldera et al., in 2005, presented the implementation on the HC9S08Rx microcontroller family (NXP Semiconductors, Eindhoven, Netherlands) of a 10 bit first-order continuous-time delta-sigma ADC using an integrated analog comparator [38].Weber and Windish, in 2007, presented the implementation on a MSP430 microcontroller (Texas Instruments, Dallas, TX, USA) for the measurement of an analog voltage for industrial applications using an external delta-sigma modulator AD7400 (Analog Devices, Wilmington, MA, USA) [39].In 2011, the technique was implemented on a Altera Cyclone IV FPGA device with an integrated analog comparator and support for low voltage differential signals (LVDSs) [40].A significant improvement over the previous designs was proposed by Bengtsson in 2012 [41].In this case, the property in which digital Sensors 2024, 24, 873 3 of 24 input pins of a microcontroller or FPGA behave like a Schmitt trigger circuit was exploited to remove the need for an analog comparator.The proposed technique was tested on a Microchip PIC18F458 microcontroller (Microchip Technology, Chandler, AZ, USA), and the results showed that an analog voltage can be determined with a resolution equivalent to a 12 bit ADC and a sampling rate of 65 Hz.The main drawbacks of the proposed method are the limited bandwidth and the high cost in terms of memory occupation.In fact, before the measurement, the capacitor must be charged to the analog voltage to be estimated, and this requires a significant amount of time, with a negative impact on the sampling rate.Moreover, the characteristic exploited to estimate the analog voltage is significantly non-linear.Thus, to guarantee the 12 bit ADC accuracy, a look-up table (LUT) must be used to map the analog voltage values to the measurements carried out with the microcontroller counter, and this results in high memory occupation that can be unacceptable, in particular in the case of a low-cost device featuring small on-chip memory.
In this paper, a technique is presented for the measurement of an analog voltage without an ADC that can be implemented on low-cost microcontrollers and FPGAs.While most microcontrollers, nowadays, integrate an internal ADC, some devices feature a low number of ADC channels.For example, the RP2040 is a 32 bit dual ARM Cortex-M0+ microcontroller present in the Raspberry Pi Pico development board that features only a four-channel 12 bit ADC [42].In such situations, the proposed technique can be used if the project needs a number of ADC channels higher than that available.In the case of FPGAs, some low-cost devices do not even feature an integrated ADC.The proposed technique uses the same external circuit of the work of Bengtsson [41] but improves it by providing a much more linear characteristic to estimate the analog voltage and removing the initial capacitance charge step that negatively affects the sampling rate.The feasibility and performance of the proposed technique were evaluated by means of LTSpice simulations and tested on a low-cost commercial FPGA.In Section 2, the working principle of the proposed technique is discussed.In Section 3, the results of LTSpice simulations are presented to validate the feasibility of the proposed technique and estimate the maximum performance in terms of accuracy and sampling rate.In Section 4, the implementation of the proposed technique on a commercial low-cost FPGA device is presented, and in Section 5, the results of measurements obtained with the FPGA device are discussed.In Section 6, the performance of the proposed technique is compared with similar techniques from literature and a 12 bit ADC integrated within a low-cost microcontroller.Finally, concluding remarks are presented in Section 7.

Measurement Technique
A measurement technique to estimate an analog voltage without the use of an ADC is presented.First, in Section 2.1, the working principle of the proposed technique is discussed.Then, in Section 2.2, the parameters of the digital interface are measured and presented for different commercial devices (microcontrollers and FPGAs).Finally, in Section 2.3, circuits are presented that can be used to change the values of the digital interface parameters.

Working Principle
The schematic of the circuit used to implement the proposed technique is shown in Figure 1, where V an represents the analog voltage to be measured.The circuit is composed of three passive components, two resistances, R 1 and R 2 , a capacitance, C, and a computing device (microcontroller or FPGA).The Schmitt trigger circuit (with thresholds V H and V L ) and the digital not gate (implemented in the programmable logic in a FPGA or in software in a microcontroller) are both integrated into the computing device.The working principle of the circuit presented in Figure 1 is shown in Figure 2, where the waveforms of the voltages V 1 and V 2 are plotted vs time.The circuit works as an astable multivibrator: when the voltage V 1 increases over V H , the output voltage V 2 switches from V DD to 0 and the capacitance C discharges; thus, V 1 decreases with time.When the voltage V 1 decreases under V L , the output voltage V 2 switches from 0 to V DD and the capacitance C charges; thus, V 1 increases with time.The output voltage V 2 is a pulse width modulated (PWM) signal, with t H being the time when V 2 = V DD and t L being the time when V 2 = 0.When V1 increases over VH and V2 switches from VDD to 0, the circuit is modeled with the following equations:   When V1 increases over VH and V2 switches from VDD to 0, the circuit is modeled with the following equations:  When V 1 increases over V H and V 2 switches from V DD to 0, the circuit is modeled with the following equations: Assuming the analog voltage V an is constant during the measurement, the differential Equation ( 1) can be integrated with the initial condition V 1 (0) = V H , and V 1 (t) can be calculated as Sensors 2024, 24, 873 5 of 24 Now, imposing the condition V 1 (t L ) = V L , the time interval t L can be calculated as As can be seen in Equation ( 2), the voltage V 1 is V H at the beginning of the capacitor discharge, and it asymptotically converges to V an •R 1 /(R 1 + R 2 ) as time → +∞.Thus, the following constraint must be valid: This constraint must be valid for all analog voltages V an in the range 0-V DD , and thus, When V 1 decreases under V L and V 2 switches from 0 to V DD , the circuit is modeled with the following equations: Assuming the analog voltage V an is constant during the measurement, the differential Equation ( 6) can be integrated with the initial condition V 1 (0) = V L , and V 1 (t) can be calculated as Now, imposing the condition V 1 (t H ) = V H , the time interval t H can be calculated as As can be seen in Equation (7), the voltage V 1 is V L at the beginning of the capacitor charge and it asymptotically converges to Thus, the following constraint must be valid: This constraint must be valid for all analog voltages V an in the range 0-V DD , and thus, As can be seen from Equations (3) and ( 8), the time intervals t L and t H are non-linear functions of the analog voltage V an , the digital interface parameters V L and V H , and the circuit components (R 1 , R 2 and C).Moreover, since the circuit of Figure 1 must work as an astable multivibrator, the conditions defined in Equations ( 5) and (10) must be valid.

Digital Interface Parameters in Commercial Devices
Since the time intervals t L and t H are functions of the digital interface parameters V L and V H , the values of such parameters were measured for different commercial microcontrollers and FPGAs.The measurements were carried out using a Nucleo L073RZ development board (ST Microelectronics, Geneva, Switzerland) that embeds on board the STM32L073RZT6 microcontroller with an integrated 12 bit DAC (measurement unit, MU).The microcontroller was programmed to generate a triangular voltage signal on the DAC output (0-3.3V, with steps of 0.806 mV and an inter-steps delay of 100 ms), and this voltage signal was provided to the digital input pin of the device under testing (DUT).The digital value read by the DUT is replicated on a digital output pin that is given as input to a digital input pin of the MU.For each DAC voltage step, the value of the analog voltage and the digital value read by the MU are sent to a laptop PC using UART, and the values of the digital interface parameters are calculated.For each DUT, five different digital input pins were tested and each measurement was carried out in triplicate.
The measured values of V L and V H for different microcontrollers and FPGAs are reported in Table 1.For each device, the reported data are the average values of V H and V L , and the coefficient of variation of ∆V (CV ∆V ) is defined as the ratio between the standard deviation and the mean value of ∆V.The results of Table 1 show that the digital interface parameters are strongly dependent on the technology, with different devices characterized by significantly different values of V L and V H . Regarding the intra-device variability of the digital interface parameters, the results have shown that the parameters V L and V H for different input pins of the same device follow a Gaussian distribution with differences that can be up to 7.5% of the average values of the interface parameters.Thus, for accurate measurements, the selected pin must be calibrated by measuring the specific values of the parameters V L and V H . From preliminary simulations, it was also assessed that the interface parameters are affected by the power supply voltage and temperature.Then, the system must feature voltage regulators to provide a stable power supply and capacitors close to the power supply pins to decouple the high-frequency noise generated by the internal circuitry.Regarding the variation with temperature, V L and V H decreases linearly with increasing temperature values, with an average change rate of 1.24 mV/ • C in the case of V H and 0.36 mV/ • C in the case of V L .Thus, if measurements are carried out in the presence of significant temperature fluctuations (>5 • C), a temperature sensor can be used to compensate for the variation of the interface parameters with temperature.

Circuits to Change the Digital Interface Parameters
The data reported in Table 1 show that different devices are characterized by different values for the digital interface parameters.In particular, the FPGA from the Basys 3 development board [45] is characterized by a small value of ∆V (about 52 mV) that cannot be compatible with accurate V an measurements if the signal-to-noise ratio (SNR) is not sufficiently high.Similarly, the parameter V t can assume values significantly different from V DD /2 = 1.65 V, and this, as will be explained in Section 3, results in lower accuracy of the measured V an value.To solve these problems, a couple of circuits were proposed that can change the values of parameters V t and ∆V at the cost of a limited increase of the interface circuit complexity.
The first circuit, presented in Figure 3, can be used to change the digital interface parameters in the case the value of V t is lower than V DD /2.The operational amplifier working in voltage follower mode is used to provide a high input impedance for the voltage signal V 1 .Indicating that when V L and V H are the digital interface parameters of the device (at node 3) and when V L * and V H * are the digital interface parameters at node 1, it is interface circuit complexity.
The first circuit, presented in Figure 3, can be used to change the digital interface parameters in the case the value of Vt is lower than VDD/2.The operational amplifier working in voltage follower mode is used to provide a high input impedance for the voltage signal V1.Indicating that when VL and VH are the digital interface parameters of the device (at node 3) and when VL* and VH* are the digital interface parameters at node 1, it is Thus, the values of Vt* and ΔV* can be calculated as Thus, the values of V t * and ∆V* can be calculated as By choosing appropriate values of R A , R B , and R C , the selected values of V L *, V H *, V t *, and ∆V* can be obtained.
Similarly, in the case of a device characterized by V t > V DD /2, the digital interface parameters can be changed using the circuit of Figure 4. Indicating that when V L and V H are the digital interface parameters of the device (at node 3) and when V L * and V H * are the digital interface parameters at node 1, they are: Thus, the values of V t * and ∆V* can be calculated as: Sensors 2024, 24, 873 Additionally, in this case, by choosing appropriate values of R A , R B , and R C , the selected values of V L *, V H *, V t *, and ∆V* can be obtained.
Additionally, in this case, by choosing appropriate values of RA, RB, and RC, the selected values of VL*, VH*, Vt*, and ΔV* can be obtained.Simulations were carried out to evaluate the impact of the accuracy of the resistors R A , R B , and R C on the accuracy of the parameters V L * and V H *. The results have shown that, in the presence of 10% variations in R A , R B , and R C , the corresponding variations in V L * and V H * are 2.72% and 4.44% for variations in R A , 2.11% and 0.7% for variations in R B , 4.71% and 3.52% for variations in R C .

Circuit Simulations
To test the feasibility and performance of the proposed technique to estimate the value of analog voltages without an ADC, circuit simulations were carried out using the software LTSpice XVII (Analog Devices, Wilmington, MA, USA) [48].The circuit presented in Figure 1 was simulated by modeling the digital interface of the DUT using a Schmitt trigger circuit with suitable values of V L and V H . Initially, the case study of a digital interface characterized by V t = 1.65 V, ∆V = 0.5 V, V L = 1.4 V, and V H = 1.9 V is considered, and the results are presented in Section 3.1.Next, the case study of digital interfaces characterized by V t = 1.65 V and multiple values of ∆V is considered and the results are presented in Section 3.2.Then, the case study of digital interfaces characterized by ∆V = 0.5 V and multiple values of V t is considered, and the results are presented in Section 3.3.Finally, the maximum performance and accuracy of the proposed technique are estimated in Section 3.4.

Digital
Interface with V t = 1.65 V and ∆V = 0.5 V In this section, the circuit of Figure 1 is simulated in the case where the digital interface is characterized by the parameters V t = 1.65 V, ∆V = 0.5 V, V L = 1.4 V, and V H = 1.9 V. Four different parameters of the output signal V 2 are considered: the period T = t H + t L , the time interval t H when V 2 = V DD , the time interval t L when V 2 = 0, and the duty cycle (DC), defined as Simulations were carried out with V DD = 3.3 V, R 1 = 10 kΩ, and different values of the capacitance C (320 nF, 150 nF, 60 nF, 47 nF, 32 nF, 20 nF, 14 nF, 9 nF, 5 nF, 2 nF, and 1 nF).Since the value of the capacitance C affects the switching frequency of the signal V 2 but does not affect the linearity of the achieved characteristics, the results of the simulations are reported for the case C = 60 nF.Under these conditions, the resistance R 2 must comply with the constraints defined by Equations ( 5) and (10), and thus, Since V t = V DD /2 = 1.65 V, Equations ( 20) and ( 21) provide the same constraint R 2 > 13.57kΩ.Simulations were carried out for different values of R 2 , and the results are reported in Figure 5.As can be seen, the period of V 2 , shown in Figure 5a, is a nonmonotonous function of V an , and thus, it cannot be used to estimate the value of the analog voltage.The time intervals t H and t L , shown in Figure 5b and c, respectively, are monotonous with V an but, as also presented in Equations ( 3) and ( 8), are nonlinear functions of V an .The exploitation of t H and t L to estimate V an , albeit feasible, must use a look-up table to map the values of V an to the measured values of t H and t L with significant use of the device memory.Moreover, the resolution of the estimated V an is not uniform in the analog voltage range (0-3.3V) but is higher for low values of V an in the case of t H and high values of V an in the case of t L .In the case of the duty cycle, shown in Figure 5d, the value is decreasing with V an , and the relation between the duty cycle and V an is linear; thus, the analog voltage V an can be estimated from the measured duty cycle without the need to use a look-up table to map the values of V an to the duty cycle.Moreover, the duty-cycle range increases for decreasing values of R 2 .This is clearly shown in Figure 6, where the maximum and minimum values of the duty cycle (achieved for V an = 0 and V an = 3.3 V, respectively) are plotted vs. R 2 .The maximum duty cycle increases and the minimum duty cycle decreases, in particular, when R 2 approaches the lower limit defined by the constraints of Equations ( 20) and (21).The relation between the duty cycle and R 2 for different values of V an can be explained by considering the charging and discharging times of the capacitor C, as shown in Figure 7.
Sensors 2024, 24, x FOR PEER REVIEW 10 range increases for decreasing values of R2.This is clearly shown in Figure 6, wher maximum and minimum values of the duty cycle (achieved for Van = 0 and Van = 3 respectively) are plotted vs. R2.The maximum duty cycle increases and the mini duty cycle decreases, in particular, when R2 approaches the lower limit defined b constraints of Equations ( 20) and (21).The relation between the duty cycle and R different values of Van can be explained by considering the charging and dischar times of the capacitor C, as shown in Figure 7.In Figure 7a, the voltage V 1 is plotted vs. time in the case V an = 0 for four different values of R 2 ; while the discharging time t L is marginally affected by R 2 , the charging time t H strongly increases with the decrease of R 2 (thus increasing the maximum value of the duty cycle).In Figure 7b, the voltage V 1 is plotted vs. time in the case V an = V DD /2 = 1.65 V for four different values of R 2 ; in this case, both the charging time t H and the discharging time t L are marginally affected by R 2 and the value of the duty cycle is close to 50%.In Figure 7c, the voltage V 1 is plotted vs. time in the case V an = V DD = 3.3 V for four different values of R 2 ; while the charging time t H is marginally affected by R 2 , the discharging time t L strongly increases with the decrease of R 2 (thus decreasing the minimum value of the duty cycle).
While the duty-cycle range (and thus the sensitivity of V an ) increases for lower values of R 2 , the linearity of the relation between the duty cycle and V an decreases as well.This is shown in Figure 8, where the absolute value of the error in the estimated V an (|∆V an,lin |), the difference between V an and the value estimated from the duty cycle using the linear regression line, is plotted vs. V an for different values of the resistance R 2 .As can be seen, the increased linearity achieved for higher values of R 2 results in a lower error in the estimated value of V an .In particular, for R 2 = 120 kΩ, the estimated error |∆V an,lin | is lower than 1 mV and comparable to the resolution of a 12 bit ADC with a 0-3.3 V input range.

Digital Interface with V t = 1.65 V and ∆V Variable
In this section, the circuit of Figure 1 is simulated in the case where the digital interface is characterized by the parameters V t = 1.65 V and four different values of ∆V (0.5 V, 1.2 V, 2.0 V, 2.8 V).The simulations were carried out with values of R 2 that results in comparable values of the duty-cycle range for V an values in the range 0-3.3 V.In particular, R 2 = 20 kΩ in the case ∆V = 0.5 V (DC min = 23.7%,DC max = 76.3%),R 2 = 26 kΩ in the case ∆V = 1.2 V (DC min = 24.8%,DC max = 75.1%),R 2 = 43 kΩ in the case ∆V = 2.0 V (DC min = 24.6%,DC max = 75.4%),and R 2 = 123 kΩ in the case ∆V = 2.8 V (DC min = 25.5%,DC max = 74.5%).The results of the simulations are presented in Figure 9, where the duty cycle is plotted vs. V an .As can be seen, in the cases ∆V = 0.5 V and ∆V = 1.2 V the duty cycle is a quasi-linear function of the analog voltage V an , while for higher values of ∆V, significant deviation from the linear response is present.The analog voltage V an was estimated from the value of the duty cycle using the linear regression line fitting the curves presented in Figure 9, and the absolute value of the error in the estimated V an (|∆V an,lin |) is plotted vs. V an for the four different values of ∆V.In Figure 7a, the voltage V1 is plotted vs. time in the case Van = 0 for four different values of R2; while the discharging time tL is marginally affected by R2, the charging time tH strongly increases with the decrease of R2 (thus increasing the maximum value of the duty cycle).In Figure 7b, the voltage V1 is plotted vs. time in the case Van = VDD/2 = 1.65 V for four different values of R2; in this case, both the charging time tH and the discharging time tL are marginally affected by R2 and the value of the duty cycle is close to 50%.In Figure 7c, the voltage V1 is plotted vs. time in the case Van = VDD = 3.3 V for four different values of R2; while the charging time tH is marginally affected by R2, the discharging time tL strongly increases with the decrease of R2 (thus decreasing the minimum value of the duty cycle).The results, presented in Figure 10, show how smaller values of ∆V are characterized by a better linear response of the relation between the duty cycle and V an and lower values of |∆V an,lin |.Thus, to achieve good accuracy in the estimation of V an , a suitable value of ∆V must be considered that must be not too high to provide a quasi-linear response but also not too low to guarantee a reliable operation of the circuit depending on the signal-to-noise ratio (SNR).
shown in Figure 8, where the absolute value of the error in the estimated Van (|ΔVan,lin|), the difference between Van and the value estimated from the duty cycle using the linear regression line, is plotted vs. Van for different values of the resistance R2.As can be seen, the increased linearity achieved for higher values of R2 results in a lower error in the estimated value of Van.In particular, for R2 = 120 kΩ, the estimated error |ΔVan,lin| is lower than 1 mV and comparable to the resolution of a 12 bit ADC with a 0-3.3 V input range.

Digital Interface with Vt = 1.65 V and ΔV Variable
In this section, the circuit of Figure 1   The results, presented in Figure 10, show how smaller values of ΔV are characterized by a better linear response of the relation between the duty cycle and Van and lower values of |ΔVan,lin|.Thus, to achieve good accuracy in the estimation of Van, a suitable value of ΔV must be considered that must be not too high to provide a quasi-linear response but also not too low to guarantee a reliable operation of the circuit depending on the signal-to-noise ratio (SNR).3.3.Digital Interface with V t Variable and ∆V = 0.5 V In this section, the circuit of Figure 1 is simulated in the case where the digital interface is characterized by five different values of V t (1.15 V, 1.40 V, 1.65 V, 1.90 V, and 2.15 V) and ∆V = 0.5 V.The digital interface parameters are, respectively, V L = 0.90 V and V H = 1.40 V for V t = 1.15 V, V L = 1.15 V, and V H = 1.65 V for V t = 1.40 V, V L = 1.40 V, and V H = 1.90 V for V t = 1.65 V, V L = 1.65 V, and V H = 2.15 V for V t = 1.90 V, V L = 1.90 V, and V H = 2.40 V for V t = 2.15 V.The simulations were carried out with R 2 = 20 kΩ for V t = 1.65 V, R 2 = 28 kΩ for V t = 1.40 V and V t = 1.90 V, and R 2 = 40 kΩ for V t = 1.15 V and V t = 2.15 V.The results of the simulations are presented in Figure 11.As can be seen, the case V t = 1.65 V is characterized by the highest range of the duty cycle and, thus, the highest sensitivity in the estimation of V an .The reason for such behavior can be explained by considering the constraint conditions defined by Equations ( 5) and (10): it is V L,inf = 1.1 V and V H,sup = 2.2 V for R 2 = 20 kΩ, V L,inf = 0.87 V and V H,sup = 2.43 V for R 2 = 28 kΩ, and V L,inf = 0.66 V and V H,sup = 2.64 V for R 2 = 40 kΩ.In the case of V t = V DD /2 = 1.65 V, the digital interface parameters are symmetrical about V DD /2, that is, V L − V L,inf = V H,sup − V H = 0.3 V.This results in a wide range of the duty cycle that is symmetrical about 50%.In the case of V t = 1.15 V, instead, it is V L − V L,inf = 0.24 V and V H,sup − V H = 1.24V, thus the duty-cycle minimum value is comparable to the case V t = 1.65 V, while the duty-cycle maximum value is much lower, resulting in a reduced duty-cycle range.Similarly, in the case of V t = 2.15 V, instead, it is V L − V L,inf = 1.24V and V H,sup − V H = 0.24 V; thus, the duty-cycle maximum value is comparable to the case V t = 1.65 V, while the duty-cycle minimum value is much higher, resulting in a reduced duty-cycle range.The results, presented in Figure 10, show how smaller values of ΔV are characterized by a better linear response of the relation between the duty cycle and Van and lower values of |ΔVan,lin|.Thus, to achieve good accuracy in the estimation of Van, a suitable value of ΔV must be considered that must be not too high to provide a quasi-linear response but also not too low to guarantee a reliable operation of the circuit depending on the signal-to-noise ratio (SNR).The analog voltage V an was estimated from the value of the duty cycle using the linear regression line fitting the curves presented in Figure 11, and the absolute value of the error in the estimated V an (|∆V an,lin |) is plotted vs. V an for the five different values of V t .The Sensors 2024, 24, 873 14 of 24 results presented in Figure 12 show that the case V t = 1.65 V is characterized by a higher duty-cycle range and better linear response of the relation between the duty cycle and V an , thus resulting in a lower error in the estimated value of V an .This shows how V t = V DD /2 is the best condition that results in the maximization of the accuracy in the estimated analog voltage V an .

Maximum Performance of the Proposed Method
In this section, the maximum performance of the proposed technique to estimate an analog voltage Van without the use of an ADC was evaluated.The performance was calculated in the ideal case of absence of noise, considering only the uncertainty in tH and tL due to the finite clock frequency.A case study is considered where the clock frequency of the device that implements the technique is set to 27 MHz (i.e., period of T = 37.037 ns) and tH and tL are measured using a 16 bit counter (i.e., maximum time interval 2.427 ms).Indicating that when NH and NL are the number of clock counts to measure tH and tL, respectively, the duty cycle of the signal V2 can be expressed as Considering the error propagation in a quotient, the error in the measured duty cycle is Since, in absence of noise, it is ΔNH = ΔNL = 1 and Δ(NH + NL) = ΔNH + ΔNL = 2, the worst case (maximum ΔDC) is obtained when NH ≈ NH + NL (high values of duty cycle).It is where fclock is the frequency of the clock signal (27 MHz) and fPWM is the frequency of the signal V2.The maximum error of the measured duty cycle (ΔDCmax) was calculated using Equation ( 24) and the error of Van due to the limited clock frequency and counter resolution (|ΔVan,clock|) estimated by considering the relation between the duty cycle and Van presented in Figure 5d, thus not considering the uncertainty due to the deviation of the characteristic from the regression line.The results are presented in Table 2 for different values of the resistance R2 and the capacitance C. In Table 3, the maximum sampling rate

Maximum Performance of the Proposed Method
In this section, the maximum performance of the proposed technique to estimate an analog voltage V an without the use of an ADC was evaluated.The performance was calculated in the ideal case of absence of noise, considering only the uncertainty in t H and t L due to the finite clock frequency.A case study is considered where the clock frequency of the device that implements the technique is set to 27 MHz (i.e., period of T = 37.037 ns) and t H and t L are measured using a 16 bit counter (i.e., maximum time interval 2.427 ms).Indicating that when N H and N L are the number of clock counts to measure t H and t L , respectively, the duty cycle of the signal V 2 can be expressed as Considering the error propagation in a quotient, the error in the measured duty cycle is Since, in absence of noise, it is where f clock is the frequency of the clock signal (27 MHz) and f PWM is the frequency of the signal V 2 .The maximum error of the measured duty cycle (∆DC max ) was calculated using Equation ( 24) and the error of V an due to the limited clock frequency and counter resolution (|∆V an,clock |) estimated by considering the relation between the duty cycle and V an presented in Figure 5d, thus not considering the uncertainty due to the deviation of the characteristic from the regression line.The results are presented in Table 2 for different values of the resistance R 2 and the capacitance C. In Table 3, the maximum sampling rate is presented for the same values of the resistance R 2 and the capacitance C. As can be seen, the maximum error |∆V an,clock | decreases with the increase of C, since higher values of the capacitance result in longer measured times, thus higher resolution due to the counter, and with the decrease of R 2 , since this results in a higher range of the duty cycle and, thus, higher resolution of the measured duty cycle.At the same time, however, lower values of the capacitance C allow a much higher sampling frequency.Thus, in a noisy environment, with low SNR values, taking measurements with a low value of C allows to take advantage of the higher sampling frequency by averaging the measurements on a large number of samples, thus reducing the uncertainty due to noise.By neglecting the error of V an due to the nonlinearity of the relation between V an and the duty cycle, for example, by mapping the values using a LUT on the device memory, an error for V an of approximately 0.67 mV (lower than a 12 bit ADC) can be achieved with a maximum sampling frequency of 863 Hz that is more than 10 times higher than the sample frequency reported in [41] (65 Hz).The maximum error for V an accounting also the error from linear modeling is obtained by adding |∆V an,clock | with the error for V an due to modeling with the linear regression line (|∆V an,lin |, i.e., data presented in Figure 8) and the results are presented in Table 4.In this case the value of V an is estimated from the measured duty cycle using a linear function, thus without a LUT to map the values of V an to the values of duty cycle.The minimum error for V an that can be achieved is 1.33 mV (close to the resolution of a 12 bit ADC) with a sampling frequency of 497 Hz.

Implementation in a FPGA Device
The proposed technique to estimate an analog voltage without the use of an ADC was implemented in a commercial FPGA, Gowin GW1NR-9 (Gowin Semiconductor, Guangzhou, China), integrated on a Tang nano 9k development board (Sipeed, Shenzhen, China) [47].The Gowin GW1NR-9 is a low-cost FPGA that does not integrate an internal ADC for analog voltage measurements.
The schematic of the digital circuit, designed in Verilog and implemented in the FPGA, is presented in Figure 13.The digital input V 1 and digital output V 2 are interfaced with the RC circuit as presented in Figure 1 to the values of duty cycle.The minimum error for Van that can be achieved is 1.33 mV (close to the resolution of a 12 bit ADC) with a sampling frequency of 497 Hz.

Implementation in a FPGA Device
The proposed technique to estimate an analog voltage without the use of an ADC was implemented in a commercial FPGA, Gowin GW1NR-9 (Gowin Semiconductor, Guangzhou, China), integrated on a Tang nano 9k development board (Sipeed, Shenzhen, China) [47].The Gowin GW1NR-9 is a low-cost FPGA that does not integrate an internal ADC for analog voltage measurements.
The schematic of the digital circuit, designed in Verilog and implemented in the FPGA, is presented in Figure 13.The digital input V1 and digital output V2 are interfaced with the RC circuit as presented in Figure 1   The working principle of the designed digital circuit is defined by the following steps: Sensors 2024, 24, 873 17 of 24 (1) An 8 bit command is sent from the PC to the FPGA using UART to request the value of the duty cycle of signal V 2 .(2) The FPGA module 'count periods' calculates the length of time signal V 2 is high (t H ) and low (t L ) and stores these data in two 16 bit registers.(3) The FPGA module 'division calculation' calculates the duty cycle of signal V 2 from the 16 bit registers thigh and tlow and stores the result in the 32 bit register division_result.(4) The measured duty cycle is sent from the FPGA to the PC using UART with four 8 bit data transfers.
Simulations of the Verilog code were carried out using the Icarus Verilog simulator [49] under Windows in the case of a V 2 signal of frequency 1 kHz and a duty cycle of 30%.The waveforms of the signals are presented in Figure 14.The time intervals when V 2 = V DD (t H ) and V 2 = 0 (t L ) are measured by the 'count periods' module using a 16 bit counter and stored inside two 16 bit registers (thigh and tlow).After the two time intervals are measured, a pulse is generated on the start_division_signal to trigger the duty-cycle calculation.This is carried out by the 'division calculation' module that accepts as input the 16 bit data thigh and tlow and generates a 32 bit signal division_result that is proportional to the duty cycle.In particular, division_result is calculated as the binary division between two 32 bit registers: A, with the most significant 16 bits equal to thigh and the least significant 16 bits equal to 0, and B, with the most significant 16 bits equal to 0 and the least significant 16 bits equal to thigh + tlow.After the binary division, carried out using the Verilog implementation presented in [50], the division result is stored in the 32 bit register division_result, a pulse is generated on the signal division_completed, and the duty cycle can be calculated using the formula The 'UART controller', 'UART TX', and 'UART RX' modules are used for the communication between the PC and the FPGA device.When the 8 bit decimal code 10 is received, the 32 bit register division_result is transferred to the PC with four 8 bit data transfer.The Verilog code of the proposed implementation on FPGA is available in the Supplementary Materials.
The working principle of the designed digital circuit is defined by the following steps: (1) An 8 bit command is sent from the PC to the FPGA using UART to request the value of the duty cycle of signal V2.(2) The FPGA module 'count periods' calculates the length of time signal V2 is high (tH) and low (tL) and stores these data in two 16 bit registers.(3) The FPGA module 'division calculation' calculates the duty cycle of signal V2 from the 16 bit registers thigh and tlow and stores the result in the 32 bit register divi-sion_result.(4) The measured duty cycle is sent from the FPGA to the PC using UART with four 8 bit data transfers.
Simulations of the Verilog code were carried out using the Icarus Verilog simulator [49] under Windows in the case of a V2 signal of frequency 1 kHz and a duty cycle of 30%.The waveforms of the signals are presented in Figure 14.The time intervals when V2 = VDD (tH) and V2 = 0 (tL) are measured by the 'count periods' module using a 16 bit counter and stored inside two 16 bit registers (thigh and tlow).After the two time intervals are measured, a pulse is generated on the start_division_signal to trigger the duty-cycle calculation.This is carried out by the 'division calculation' module that accepts as input the 16 bit data thigh and tlow and generates a 32 bit signal division_result that is proportional to the duty cycle.In particular, division_result is calculated as the binary division between two 32 bit registers: A, with the most significant 16 bits equal to thigh and the least significant 16 bits equal to 0, and B, with the most significant 16 bits equal to 0 and the least significant 16 bits equal to thigh + tlow.After the binary division, carried out using the Verilog implementation presented in [50], the division result is stored in the 32 bit register division_result, a pulse is generated on the signal division_completed, and the duty cycle can be calculated using the formula The 'UART controller', 'UART TX', and 'UART RX' modules are used for the communication between the PC and the FPGA device.When the 8 bit decimal code 10 is received, the 32 bit register division_result is transferred to the PC with four 8 bit data transfer.The Verilog code of the proposed implementation on FPGA is available in the Supplementary Materials.

Experimental Results
The measurement technique, implemented on the Gowin GW1NR-9 FPGA device [51] integrated in the Tang Nano 9k development board [47], was tested using the measurement setup shown in Figure 15.After the place-and-route step, the FPGA resources used were 498/8640 of the programmable LUTs and ALUs (5%), 369/6693 of the

Experimental Results
The measurement technique, implemented on the Gowin GW1NR-9 FPGA device [51] integrated in the Tang Nano 9k development board [47], was tested using the measurement setup shown in Figure 15.After the place-and-route step, the FPGA resources used were 498/8640 of the programmable LUTs and ALUs (5%), 369/6693 of the registers (5%), 329/4320 of the configurable logic slice (7%), and 5 I/O ports.The analog voltage V an to be measured is generated using the 12 bit DAC integrated in the STM32 microcontroller present on the Nucleo-L073RZ development board.A Laptop PC is used to communicate with the microcontroller board and the FPGA board using the USB-UART interface.The PC sends a control message to the Nucleo-L073RZ board to set the value of the analog voltage V an at the output of the 12 bit DAC.Similarly, the PC sends a control message to the FPGA board (Tang nano 9k) to request the measured value of the duty cycle of the signal V 2 .The circuit composed of the resistances R 1 and R 2 and the capacitance C was implemented using discrete components mounted on a solderless breadboard.
to communicate with the microcontroller board and the FPGA board using the USB-UART interface.The PC sends a control message to the Nucleo-L073RZ board to set the value of the analog voltage Van at the output of the 12 bit DAC.Similarly, the PC sends a control message to the FPGA board (Tang nano 9k) to request the measured value of the duty cycle of the signal V2.The circuit composed of the resistances R1 and R2 and the capacitance C was implemented using discrete components mounted on a solderless breadboard.
First of all, the noise level of the circuit was evaluated by measuring the analog voltage Van using the 12 bit ADC integrated in the STM32 microcontroller.Seven different Van values were set with the 12-bit DAC: 0.419 V, 0.832 V, 1.244 V, 1.656 V, 2.068 V, 2.481 V, and 2.894 V.For each Van value, 10,000 acquisitions were made using the 12 bit ADC and the statistical distribution of the acquired analog voltages evaluated.The average standard deviation (σ) of the analog voltage distribution was 4.442 mV.Thus, considering an uncertainty of ±2σ, the maximum error in the acquired analog voltage was 17.768 mV (confidence level 95%).This is significantly higher than the 12 bit ADC resolution (0.806 mV).The accuracy of the measured analog voltage Van can be increased by averaging different measurements.Indicating that when N is the number of measurements used to estimate Van, the standard deviation of the distribution of the analog voltage with N measurements is To obtain the reading uncertainty typical of a 12 bit ADC (0.806 mV), it should be σN = 0.2015 mV and, given σ = 4.442 mV, the number of measurements N should be 486.Thus, under the current noise level, the original 1 MHz ADC sampling rate must be reduced to approximately 2057 Hz to guarantee a measurement uncertainty of 0.806 mV for the analog voltage Van.First of all, the noise level of the circuit was evaluated by measuring the analog voltage V an using the 12 bit ADC integrated in the STM32 microcontroller.Seven different V an values were set with the 12-bit DAC: 0.419 V, 0.832 V, 1.244 V, 1.656 V, 2.068 V, 2.481 V, and 2.894 V.
For each V an value, 10,000 acquisitions were made using the 12 bit ADC and the statistical distribution of the acquired analog voltages evaluated.The average standard deviation (σ) of the analog voltage distribution was 4.442 mV.Thus, considering an uncertainty of ±2σ, the maximum error in the acquired analog voltage was 17.768 mV (confidence level 95%).This is significantly higher than the 12 bit ADC resolution (0.806 mV).The accuracy of the measured analog voltage V an can be increased by averaging different measurements.Indicating that when N is the number of measurements used to estimate V an , the standard deviation of the distribution of the analog voltage with N measurements is To obtain the reading uncertainty typical of a 12 bit ADC (0.806 mV), it should be σ N = 0.2015 mV and, given σ = 4.442 mV, the number of measurements N should be 486.Thus, under the current noise level, the original 1 MHz ADC sampling rate must be reduced to approximately 2057 Hz to guarantee a measurement uncertainty of 0.806 mV for the analog voltage V an .
Using the measurement setup presented in Figure 15, the resistance R 1 was set to 10 kΩ and 10 different values of the resistance R 2 were tested (15 kΩ, 16.3 kΩ, 18 kΩ, 22 kΩ, 27 kΩ, 32 kΩ, 38.8 kΩ, 47 kΩ, 67.8 kΩ, and 81.7 kΩ).For each value of the resistance R 2 , 10 different values of the capacitance C were tested (1 nF, 2 nF, 4.9 nF, 9 nF, 14 nF, 20 nF, 32 nF, 47 nF, 62 nF, 106 nF).Each measurement was carried out on 83 different V an values distributed on the 0-3.3 V range (steps of 39.759 mV), and, for each V an value, 1000 acquisitions were carried out to evaluate the average value and the standard deviation of the estimated V an .The results showed no significant difference in the standard deviation of the estimated V an for different values of the capacitance C.This can be explained by the high levels of noise introduced by the circuit implementation on a solderless breadboard with fly wires.Thus, in the following, the experiments are presented for the capacitance C = 1 nF since this results in the highest sampling rate and allows averaging of the measured signal on a larger number of samples to reduce the error.In Figure 16, the measured duty cycle plotted vs. the analog voltage V an is presented for different values of R 2 and C = 1 nF.
kΩ and 10 different values of the resistance R2 were tested (15 kΩ, 16.3 kΩ, 18 kΩ, 22 kΩ, 27 kΩ, 32 kΩ, 38.8 kΩ, 47 kΩ, 67.8 kΩ, and 81.7 kΩ).For each value of the resistance R2, 10 different values of the capacitance C were tested (1 nF, 2 nF, 4.9 nF, 9 nF, 14 nF, 20 nF, 32 nF, 47 nF, 62 nF, 106 nF).Each measurement was carried out on 83 different Van values distributed on the 0-3.3 V range (steps of 39.759 mV), and, for each Van value, 1000 acquisitions were carried out to evaluate the average value and the standard deviation of the estimated Van.The results showed no significant difference in the standard deviation of the estimated Van for different values of the capacitance C.This can be explained by the high levels of noise introduced by the circuit implementation on a solderless breadboard with fly wires.Thus, in the following, the experiments are presented for the capacitance C = 1 nF since this results in the highest sampling rate and allows averaging of the measured signal on a larger number of samples to reduce the error.In Figure 16  As can be seen, the duty cycle presents a very good linear relationship with the analog voltage Van in the range 0.12-3.22V.The saturation of the characteristic outside this range was observed also in the measurements of Van using the microcontroller integrated 12 bit ADC and can be explained by a saturation of the output of the 12 bit DAC used to generate Van.Thus, in the following, the performance of the technique deployed on the FPGA device was evaluated in the Van range 0.12-3.22V.For each value of the resistance R2, the linear regression equation that best fits the characteristic duty cycle Van was calculated offline using a PC.The calculated slope and offset of the linear regression line were stored in the FPGA memory and used to estimate the value of the analog voltage Van.The maximum deviation to the real value of Van (|ΔVan|) was also evaluated.The measured standard deviation (σ) of the estimated Van was considered for the determination of the number of measurements (N) needed to obtain the reported accuracy in the Van estimation, and this value was used to calculate the maximum sampling rate (SRmax).The results are reported in Table 5.As can be seen, the uncertainty in the analog voltage estimation (|ΔVan|) presents a minimum for R2 = 32 kΩ.This is the result of two different effects: a) lower values of R2 are characterized by a higher range of the duty cycle and, thus, higher sensitivity in the Van estimation (this is confirmed by the higher standard deviation σ in the case of higher values of R2) and b) higher values of R2 result in stronger linearity of the duty-cycle Van characteristic, thus lower error in the estimation of Van using As can be seen, the duty cycle presents a very good linear relationship with the analog voltage V an in the range 0.12-3.22V.The saturation of the characteristic outside this range was observed also in the measurements of V an using the microcontroller integrated 12 bit ADC and can be explained by a saturation of the output of the 12 bit DAC used to generate V an .Thus, in the following, the performance of the technique deployed on the FPGA device was evaluated in the V an range 0.12-3.22V.For each value of the resistance R 2 , the linear regression equation that best fits the characteristic duty cycle V an was calculated offline using a PC.The calculated slope and offset of the linear regression line were stored in the FPGA memory and used to estimate the value of the analog voltage V an .The maximum deviation to the real value of V an (|∆V an |) was also evaluated.The measured standard deviation (σ) of the estimated V an was considered for the determination of the number of measurements (N) needed to obtain the reported accuracy in the V an estimation, and this value was used to calculate the maximum sampling rate (SR max ).The results are reported in Table 5.As can be seen, the uncertainty in the analog voltage estimation (|∆V an |) presents a minimum for R 2 = 32 kΩ.This is the result of two different effects: (a) lower values of R 2 are characterized by a higher range of the duty cycle and, thus, higher sensitivity in the V an estimation (this is confirmed by the higher standard deviation σ in the case of higher values of R 2 ) and (b) higher values of R 2 result in stronger linearity of the duty-cycle V an characteristic, thus lower error in the estimation of V an using the linear regression line.In the end, the highest accuracy in the V an estimation (1.09 mV) is obtained for R 2 = 32 kΩ with a maximum sampling rate of 9.75 Hz.Under these conditions, the analog voltage is measured with an effective number of bits ENOB = 10.82, a signal-to-noise ratio SNR = 66.9 dB, a differential nonlinearity DNL = 0.12 LSB, and an integral nonlinearity INL = 0.72 LSB.The maximum sampling rate can be increased to 31.35Hz and 128.31Hz with a limited reduction in the estimated V an accuracy (maximum errors of 1.61 mV and 2.68 mV, respectively).This was achieved using a solderless breadboard implementation with fly wires.The implementation on a custom designed electronic board integrating the FPGA and the measurement circuit is expected to significantly reduce the noise level and thus improve the measurement accuracy.

Comparison with the State of the Art
The performance of the proposed technique for analog voltage measurement without an ADC was compared to similar techniques from the literature, as well as a 12 bit ADC integrated in a low-cost microcontroller, and the results are presented in Table 6.The Nucleo-L073RZ is a development platform with onboard the microcontroller STM32L073RZT6 by ST-Microelectronics that integrates a 12 bit ADC [43].This is a very popular platform for the development of portable battery-operated sensor systems due to the low power consumption.The internal 12 bit ADC works in the range 0-3.3 V with a maximum error (in the ideal case of absence of noise) of 0.806 mV and a sampling rate of 1 MHz.
The technique proposed by Peter et al. in 1998, implemented on the PIC16C6XX series of microcontrollers, presents a 10 bit delta-sigma ADC using the analog comparator integrated in the microcontroller and a digital filter [37].The measured analog voltages are in the range 0-5 V, the reported effective resolution is 8 bit (maximum error 19.53 mV), and a single measurement takes 20.48 ms (maximum sample rate 48.83 Hz).
The work by Soldera et al. also implements a 10 bit delta-sigma ADC on the HC9S08Rx family of microcontrollers working at 8 MHz and exploits the analog comparator integrated in the microcontroller for the analog voltage measurements in the range 0-3.3 V [38].The reported maximum error is 3.22 mV with a sampling rate of 125 Hz.
The technique presented by Weber and Windish in 2007 implements an analog voltage measurement without an ADC using the microcontroller MSP430F2274 (Texas Instruments) [39].The proposed implementation is suited for the measurement of control signals in an industrial environment (0-10 V, 0-20 mA) and uses an external AD7400 delta-sigma modulator (Analog Devices).No data are reported about the measurement accuracy and sampling rate.
A delta-sigma modulator for analog voltage measurements was also proposed in 2011 with an implementation on an Altera Cyclone IV FPGA device [40].The reported sampling rate is very high (500 kHz), with a maximum error for the measured voltage of 3.22 mV.However, the proposed technique exploits the Low Voltage Differential Signaling (LVDS) receiver integrated in the FPGA and, thus, can be implemented only on devices with this feature.
Another delta-sigma modulator on FPGA is presented by Lattice Semiconductor and implemented using a LVDS receiver or an external analog comparator for the FPGA devices that lack this feature [52].The range of the analog voltage is 0-3.3V, and the reported maximum error is 12.88 mV with a sampling rate of 7.63 kHz.
Differently from the previous implementations presented in [37][38][39][40]52] that use an analog comparator, either integrated in the device or external, the works proposed by Bengtsson in 2012 exploit the Schmitt trigger circuit of the digital input port of a PIC18F458 microcontroller for the voltage measurements [41].The measurement range is 0-5 V, with a reported maximum error of 1.22 mV and a sampling frequency of 65 Hz.To achieve this measurement accuracy, a LUT, stored in the microcontroller memory, is used to map the time periods measured with the internal counter to the analog voltage values.
The presented work implements an analog voltage measurement without an ADC in a low-cost FPGA device (Gowin GW1NR-9).The novelty of the proposed solution lies in the exploitation of the Schmitt trigger circuit of the digital input pin of a microcontroller or FPGA combined with the estimation of the analog voltage from the duty cycle of a squarewave signal.The exploitation of the Schmitt trigger circuit of the digital input pin allows avoidance of the use of an analog comparator while the property of the duty cycle of the monitored waveform signal to feature a good linear correlation with the analog voltage is exploited to avoid the use of a LUT, with benefits in terms of lower memory occupation.The works in [37][38][39][40]52] propose delta-sigma ADCs implemented in different microcontrollers and FPGAs that make use of an analog comparator and a reference voltage.The works in [40,52] remove the need for an analog comparator by the use of a LVDS receiver, but this high-speed differential signal technology is generally not integrated in microcontrollers and low-cost FPGAs.The work of Bengtsson [41], instead, exploits the Schmitt trigger property of the digital input pin of a microcontroller like the proposed solution, but estimates the analog voltage with a nonlinear characteristic and using a LUT to map the measured counter time to the analog voltage, with increased cost in terms of memory occupation.The proposed solution features a maximum error in absence of noise of 1.33 mV with a sampling frequency of 497 Hz.The results from experimental measurements in a noisy environment show that an accuracy close to a 12 bit ADC can be achieved with a sampling frequency of 9.75 Hz or, alternatively, a maximum error of 1.61 mV or 2.68 mV for a sampling frequency of 31.35Hz and 128.31Hz, respectively.

Conclusions
A novel technique was presented to implement a direct interface between a sensor with analog output voltage and the digital input ports of a microcontroller or Field-Programmable Gate Array (FPGA).The proposed method requires, in its simplest implementation, only a few discrete passive components (two resistors and a capacitor) and estimates the analog voltage from the duty cycle of a square-wave digital signal using a quasi-linear characteristic.Simulations using LTSpice have shown that, using a 16 bit counter, a resolution of 1.33 mV can be achieved with a maximum sampling rate of 497 Hz and without the use of look-up tables to map the analog voltages to the duty-cycle values, thus with significant reduction in memory occupation.The proposed technique was implemented in a low-cost commercial FPGA using a solderless breadboard with fly wires, and the test results showed a maximum error of 1.09 mV with a sampling rate of 9.75 Hz.The sampling rate can be increased with a limited reduction in the analog voltage estimation accuracy (31.35 Hz for a maximum error of 1.61 mV and 128.31Hz for a maximum error of 2.68 mV).A potential issue that can impact the accuracy of the proposed technique is the variation of the interface parameters with environmental conditions (temperature and humidity) and power supply, as well as with the aging of the device.Future investigations in this research line will be aimed at evaluating these effects and proposing countermeasures to mitigate the impact on the measurement accuracy.

Sensors 2024 ,
24, x FOR PEER REVIEW 4 of 25 forms of the voltages V1 and V2 are plotted vs time.The circuit works as an astable multivibrator: when the voltage V1 increases over VH, the output voltage V2 switches from VDD to 0 and the capacitance C discharges; thus, V1 decreases with time.When the voltage V1 decreases under VL, the output voltage V2 switches from 0 to VDD and the capacitance C charges; thus, V1 increases with time.The output voltage V2 is a pulse width modulated (PWM) signal, with tH being the time when V2 = VDD and tL being the time when V2 = 0.

Figure 1 .
Figure 1.Schematic of the circuit used to implement the proposed technique for analog voltage measurements without an ADC.

Figure 2 .
Figure 2. Waveforms of the voltage signals for the circuit presented in Figure 1.

Figure 1 .
Figure 1.Schematic of the circuit used to implement the proposed technique for analog voltage measurements without an ADC.

Figure 1 .
Figure 1.Schematic of the circuit used to implement the proposed technique for analog voltage measurements without an ADC.

Figure 2 .
Figure 2. Waveforms of the voltage signals for the circuit presented in Figure 1.Figure 2. Waveforms of the voltage signals for the circuit presented in Figure 1.

Figure 2 .
Figure 2. Waveforms of the voltage signals for the circuit presented in Figure 1.Figure 2. Waveforms of the voltage signals for the circuit presented in Figure 1.

Figure 3 .
Figure 3. Circuit for the modulation of digital interface parameters in the case of a DUT with Vt < VDD/2.

Figure 3 .
Figure 3. Circuit for the modulation of digital interface parameters in the case of a DUT with V t < V DD /2.

Figure 4 .
Figure 4. Circuit for the modulation of digital interface parameters in the case of a DUT with Vt > VDD/2.Simulations were carried out to evaluate the impact of the accuracy of the resistors RA, RB, and RC on the accuracy of the parameters VL* and VH*.The results have shown that, in the presence of 10% variations in RA, RB, and RC, the corresponding variations in

Figure 4 .
Figure 4. Circuit for the modulation of digital interface parameters in the case of a DUT with V t > V DD /2.

Figure 5 .
Figure 5. Simulated values of period (a), tH (b), tL (c), and duty cycle (d) of the output sign plotted vs. the analog voltage Van for R1 = 10 kΩ, C = 60 nF, and different values of R2.Figure 5. Simulated values of period (a), t H (b), t L (c), and duty cycle (d) of the output signal V 2 plotted vs. the analog voltage V an for R 1 = 10 kΩ, C = 60 nF, and different values of R 2 .

Figure 5 .
Figure 5. Simulated values of period (a), tH (b), tL (c), and duty cycle (d) of the output sign plotted vs. the analog voltage Van for R1 = 10 kΩ, C = 60 nF, and different values of R2.Figure 5. Simulated values of period (a), t H (b), t L (c), and duty cycle (d) of the output signal V 2 plotted vs. the analog voltage V an for R 1 = 10 kΩ, C = 60 nF, and different values of R 2 .

Figure 5 .
Figure 5. Simulated values of period (a), tH (b), tL (c), and duty cycle (d) of the output signal V2 plotted vs. the analog voltage Van for R1 = 10 kΩ, C = 60 nF, and different values of R2.

Figure 6 .
Figure 6.Minimum and maximum values of the duty cycle plotted vs. the value of the resistance R2.Figure 6. Minimum and maximum values of the duty cycle plotted vs. the value of the resistance R 2 .

Figure 6 .
Figure 6.Minimum and maximum values of the duty cycle plotted vs. the value of the resistance R2.Figure 6. Minimum and maximum values of the duty cycle plotted vs. the value of the resistance R 2 .

Figure 7 .
Figure 7. Waveforms of the signal V1 plotted vs. time during the charging and discharging phase of the capacitor C for four different values of R2 in the case of (a) Van = 0, (b) Van = VDD/2 = 1.65 V, and (c) Van = VDD = 3.3 V.

Figure 7 .
Figure 7. Waveforms of the signal V 1 plotted vs. time during the charging and discharging phase of the capacitor C for four different values of R 2 in the case of (a) V an = 0, (b) V an = V DD /2 = 1.65 V, and (c) V an = V DD = 3.3 V.

Figure 8 .
Figure 8. Absolute value of the error in the estimated Van plotted vs. the real value of Van for different values of the resistance R2.
is simulated in the case where the digital interface is characterized by the parameters Vt = 1.65 V and four different values of ΔV (0.5 V, 1.2 V, 2.0 V, 2.8 V).The simulations were carried out with values of R2 that results in comparable values of the duty-cycle range for Van values in the range 0-3.3 V.In particular, R2 = 20 kΩ in the case ΔV = 0.5 V (DCmin = 23.7%,DCmax = 76.3%),R2 = 26 kΩ in the case ΔV = 1.2 V (DCmin = 24.8%,DCmax = 75.1%),R2 = 43 kΩ in the case ΔV = 2.0 V (DCmin = 24.6%,DCmax = 75.4%),and R2 = 123 kΩ in the case ΔV = 2.8 V (DCmin = 25.5%,DCmax = 74.5%).The results of the simulations are presented in Figure9, where the duty cycle is plotted vs. Van.As can be seen, in the cases ΔV = 0.5 V and ΔV = 1.2 V the duty cycle is a quasi-linear function of the analog voltage Van, while for higher values of ΔV, significant deviation from the linear response is present.The analog voltage Van was estimated from the value of the duty cycle using the linear regression line fitting the curves presented in Figure9, and the absolute value of the error in the estimated Van (|ΔVan,lin|) is plotted vs. Van for the four different values of ΔV.

Figure 8 . 25 Figure 9 .
Figure 8. Absolute value of the error in the estimated V an plotted vs. the real value of V an for different values of the resistance R 2 .Sensors 2024, 24, x FOR PEER REVIEW 13 of 25

Figure 9 .
Figure 9. Simulated values of the duty cycle of the output signal V 2 plotted vs. the analog voltage V an in the case V t = V DD /2 = 1.65 V and four different values of ∆V.

Figure 9 .
Figure 9. Simulated values of the duty cycle of the output signal V2 plotted vs. the analog voltage Van in the case Vt = VDD/2 = 1.65 V and four different values of ΔV.

Figure 10 .
Figure 10.Absolute value of the error in the estimated Van plotted vs. the real value of Van for Vt = VDD/2 = 1.65 V and four different values of ΔV.

3. 3 .
Digital Interface with Vt Variable and ΔV = 0.5 V In this section, the circuit of Figure 1 is simulated in the case where the digital interface is characterized by five different values of Vt (1.15 V, 1.40 V, 1.65 V, 1.90 V, and 2.15 V) and ΔV = 0.5 V.The digital interface parameters are, respectively, VL = 0.90 V and VH = 1.40 V for Vt = 1.15 V, VL = 1.15 V, and VH = 1.65 V for Vt = 1.40 V, VL = 1.40 V, and VH = 1.90 V for Vt = 1.65 V, VL = 1.65 V, and VH = 2.15 V for Vt = 1.90 V, VL = 1.90 V, and VH = 2.40 V for Vt = 2.15 V.The simulations were carried out with R2 = 20 kΩ for Vt = 1.65 V, R2 = 28

Figure 10 .
Figure 10.Absolute value of the error in the estimated V an plotted vs. the real value of V an for V t = V DD /2 = 1.65 V and four different values of ∆V.

Figure 11 .
Figure 11.Simulated values of the duty cycle of the output signal V2 plotted vs. the analog voltage Van in the case of five different values of Vt and ΔV = 0.5 V.The analog voltage Van was estimated from the value of the duty cycle using the linear regression line fitting the curves presented in Figure 11, and the absolute value of the error in the estimated Van (|ΔVan,lin|) is plotted vs. Van for the five different values of Vt.The results presented in Figure12show that the case Vt = 1.65 V is characterized by a higher duty-cycle range and better linear response of the relation between the duty cycle and Van, thus resulting in a lower error in the estimated value of Van.This shows how Vt = VDD/2 is the best condition that results in the maximization of the accuracy in the estimated analog voltage Van.

Figure 11 .
Figure 11.Simulated values of the duty cycle of the output signal V 2 plotted vs. the analog voltage V an in the case of five different values of V t and ∆V = 0.5 V.

Sensors 2024 , 25 Figure 12 .
Figure 12.Absolute value of the error in the estimated Van plotted vs. the real value of Van for five different values of Vt and ΔV = 0.5 V.

Figure 12 .
Figure 12.Absolute value of the error in the estimated V an plotted vs. the real value of V an for five different values of V t and ∆V = 0.5 V.
. The clock signal clk (27 MHz) is generated using the 27 MHz crystal oscillator present on the Tang nano 9k development board.The UART_RX and UART_TX signals are interfaced with the USB-UART connector of the development board to allow UART communication (baud rate 115200) with a PC using ad-hoc developed LabVIEW programs (National Instruments).Sensors 2024, 24, x FOR PEER REVIEW 17 of 25 . The clock signal clk (27 MHz) is generated using the 27 MHz crystal oscillator present on the Tang nano 9k development board.The UART_RX and UART_TX signals are interfaced with the USB-UART connector of the development board to allow UART communication (baud rate 115200) with a PC using ad-hoc developed LabVIEW programs (National Instruments).

Figure 13 .
Figure 13.Schematic of the digital circuit for the estimation of an analog voltage without the use of an ADC.

Figure 13 .
Figure 13.Schematic of the digital circuit for the estimation of an analog voltage without the use of an ADC.

Figure 14 .
Figure 14.Simulation of the designed digital circuit for the estimation of an analog voltage without the use of an ADC.

Figure 14 .
Figure 14.Simulation of the designed digital circuit for the estimation of an analog voltage without the use of an ADC.

Figure 15 .
Figure 15.Measurement setup used to validate the proposed technique for analog voltage measurements without the use of an ADC.

Figure 15 .
Figure 15.Measurement setup used to validate the proposed technique for analog voltage measurements without the use of an ADC.
, the measured duty cycle plotted vs. the analog voltage Van is presented for different values of R2 and C = 1 nF.

Figure 16 .
Figure 16.Measured duty cycle of the digital signal V2 plotted vs. the analog voltage Van for R1 = 10 kΩ, C = 1 nF, and different values of the resistance R2.

Figure 16 .
Figure 16.Measured duty cycle of the digital signal V 2 plotted vs. the analog voltage V an for R 1 = 10 kΩ, C = 1 nF, and different values of the resistance R 2 .

Table 1 .
Characteristics of the digital interface parameters for different microcontrollers and FPGAs.

Table 2 .
Maximum error of V an (in mV) due to the limited clock frequency and counter resolution for different values of the resistance R 2 and the capacitance C. Color-map: green-10th percentile, yellow-50th percentile, and red-90th percentile.

Table 3 .
Maximum sampling frequency (in Hz) for different values of the resistance R 2 and the capacitance C. Color-map: green-10th percentile, yellow-50th percentile, and red-90th percentile.

Table 4 .
Maximum error of V an (in mV) due to the limited clock frequency, counter resolution and the linearity approximation for different values of the resistance R 2 and the capacitance C. Color-map: green-10th percentile, yellow-50th percentile, and red-90th percentile.

Table 4 .
Maximum error of Van (in mV) due to the limited clock frequency, counter resolution and the linearity approximation for different values of the resistance R2 and the capacitance C. Color-map: green-10th percentile, yellow-50th percentile, and red-90th percentile.

Table 5 .
Performance of the proposed technique to estimate an analog voltage implemented in a FPGA device.

Table 6 .
Performance comparison of the proposed technique for analog voltage measurements without an ADC with similar techniques from literature and a 12 bit ADC integrated in a low-cost microcontroller.