3.6 mW Active-Electrode ECG/ETI Sensor System Using Wideband Low-Noise Instrumentation Amplifier and High Impedance Balanced Current Driver

An active electrode (AE) and back-end (BE) integrated system for enhanced electrocardiogram (ECG)/electrode-tissue impedance (ETI) measurement is proposed. The AE consists of a balanced current driver and a preamplifier. To increase the output impedance, the current driver uses a matched current source and sink, which operates under negative feedback. To increase the linear input range, a new source degeneration method is proposed. The preamplifier is realized using a capacitively-coupled instrumentation amplifier (CCIA) with a ripple-reduction loop (RRL). Compared to the traditional Miller compensation, active frequency feedback compensation (AFFC) achieves bandwidth extension using the reduced size of the compensation capacitor. The BE performs three types of signal sensing: ECG, band power (BP), and impedance (IMP) data. The BP channel is used to detect the Q-, R-, and S-wave (QRS) complex in the ECG signal. The IMP channel measures the resistance and reactance of the electrode-tissue. The integrated circuits for the ECG/ETI system are realized in the 180 nm CMOS process and occupy a 1.26 mm2 area. The measured results show that the current driver supplies a relatively high current (>600 μApp) and achieves a high output impedance (1 MΩ at 500 kHz). The ETI system can detect resistance and capacitance in the ranges of 10 mΩ–3 kΩ and 100 nF–100 μF, respectively. The ECG/ETI system consumes 3.6 mW using a single 1.8 V supply.


Introduction
Bioimpedance sensing has been an important research topic for investigating tissue properties, which provides valuable information for diagnosis, physiology, and pathology [1][2][3]. Dry electrodes have gradually replaced wet electrodes owing to the many advantages in personal healthcare and brain-computer interface applications [4,5]. Dry electrodes enable long-term monitoring in a user-friendly manner; however, they are exposed to relatively high variations in the electrode-tissue impedance [6]. This leads to interference in the wires that connect the electrodes to the readout circuit, thus reducing the signal quality. Some designs use analog buffers in the electrode [7]; this approach performs only impedance conversion, and it still places a stringent low-noise performance on the subsequent readout circuits. An alternative solution to this issue is using an active electrode (AE) containing a preamplifier [8]. This approach allows the electrodes to be placed close to the tissue. Noise interference is reduced by the short path from the electrode to the preamplifier, which relieves the noise requirement of the subsequent back-end (BE) circuits.
However, there are several challenges that are required to be addressed for this approach to be fully compatible with the electrocardiogram (ECG)/electrode-tissue impedance (ETI) sensing system [9,10]. The ETI system uses currents with different amplitudes and frequencies, which are injected into the tissue to measure the impedance spectrum. The variations in skin-electrode impedance are required to be resolved using a driver with a Figure 1 shows a block diagram of the proposed ECG/ETI system. The AE consists of a current driver and a preamplifier. The current driver includes matched current source and sink. The preamplifier, which is realized using CCIA, consists of two gain stages (G m1 , G m2 ). The output ripple is suppressed using a ripple-reduction loop (RRL). The BE consists of five channels for three types of signal (ECG, BP, and IMP) sensing. To handle the in-phase and quadrature components, two sub-channels are used for BP and IMP measurement. The QRS complex in the ECG signal is detected using the BP channel. The IMP channel reads out the resistance and reactance, providing information on the electrode-tissue contact conditions. The ECG/ETI system is realized using a one-poly six-metal (1P6M) 180 nm CMOS process. The analog circuits are implemented using thick-oxide (3.3 V) transistors, which are tolerant up to 5 V. The digital circuits are realized using thin-oxide (1.8 V) transistors. Figure 2 shows the schematic of the ETI measurement system. The current driver injects a balanced current into the tissue through the electrodes, which can be represented as i(t) = |I|cos(ωt), where the angular frequency is ω = 2πf. The corresponding voltages measured by the active electrodes (AE 1 and AE 2 ) can be written as v(t) = |V|cos(ωt + θ). Then, we can obtain the in-phase and quadrature components as v(t) = |V| cos θ cos(ωt) − |V| sin θ sin(ωt) = R(t) cos(ωt) − X(t) sin(ωt) .
(1)   Figure 2 shows the schematic of the ETI measurement system. The current drive injects a balanced current into the tissue through the electrodes, which can be represented as i(t) = |I|cos(ωt), where the angular frequency is ω = 2πf. The corresponding voltage measured by the active electrodes (AE1 and AE2) can be written as v(t) = |V|cos(ωt + θ) Then, we can obtain the in-phase and quadrature components as ( ) | | cos cos( ) | | sin sin( ) The signals are further processed using different phases to obtain resistance R(t) = |V|cos(θ)/|I| and reactance X(t) = |V|sin(θ)/|I|. Using the output of the in-phase and quadrature components, the spectral band power φ(f) of the BP channel can be expressed as 2 Figure 3 shows the schematic of the current driver. It consists of two identical sub drivers to generate a balanced output. One is used for sinking current, and the other is used for sourcing current. This configuration can reject the common-mode (CM) voltage across the load caused by the mismatch in the transconductor (Gmc1,2) and sensing resistor (RS1,S2). Each sub-driver consists of a differential difference amplifier (DDA1,2) followed by the transconductor, which performs the voltage-to-current conversion. The RS1,S2 is used to monitor the output current, and the voltage across the resistor is fed back to the DDA1, through a pair of voltage buffers (VB1,2 and VB3,4), forming a negative-feedback loop. To    Figure 2 shows the schematic of the ETI measurement system. The current driver injects a balanced current into the tissue through the electrodes, which can be represented as i(t) = |I|cos(ωt), where the angular frequency is ω = 2πf. The corresponding voltages measured by the active electrodes (AE1 and AE2) can be written as v(t) = |V|cos(ωt + θ). Then, we can obtain the in-phase and quadrature components as ( ) | | cos cos( ) | | sin sin( )

Current Driver
The signals are further processed using different phases to obtain resistance R(t) = |V|cos(θ)/|I| and reactance X(t) = |V|sin(θ)/|I|. Using the output of the in-phase and quadrature components, the spectral band power φ(f) of the BP channel can be expressed as 2 where w(t) is the windowing function [14].  Figure 3 shows the schematic of the current driver. It consists of two identical subdrivers to generate a balanced output. One is used for sinking current, and the other is used for sourcing current. This configuration can reject the common-mode (CM) voltage across the load caused by the mismatch in the transconductor (Gmc1,2) and sensing resistors (RS1,S2). Each sub-driver consists of a differential difference amplifier (DDA1,2) followed by the transconductor, which performs the voltage-to-current conversion. The RS1,S2 is used to monitor the output current, and the voltage across the resistor is fed back to the DDA1,2 through a pair of voltage buffers (VB1,2 and VB3,4), forming a negative-feedback loop. To The signals are further processed using different phases to obtain resistance R(t) = |V|cos(θ)/|I| and reactance X(t) = |V|sin(θ)/|I|. Using the output of the inphase and quadrature components, the spectral band power ϕ(f ) of the BP channel can be expressed as

Current Driver
where w(t) is the windowing function [14]. Figure 3 shows the schematic of the current driver. It consists of two identical subdrivers to generate a balanced output. One is used for sinking current, and the other is used for sourcing current. This configuration can reject the common-mode (CM) voltage across the load caused by the mismatch in the transconductor (G mc1,2 ) and sensing resistors (R S1,S2 ). Each sub-driver consists of a differential difference amplifier (DDA 1,2 ) followed by the transconductor, which performs the voltage-to-current conversion. The R S1,S2 is used to monitor the output current, and the voltage across the resistor is fed back to the DDA 1,2 through a pair of voltage buffers (VB 1,2 and VB 3,4 ), forming a negative-feedback loop. To accommodate a wide output swing, the buffers are designed to achieve a rail-to-rail output [11].

Current Driver
Source degeneration is used to extend the linear range. Figure 4a shows the previous approach of source degeneration [11], where the equivalent resistance of M 3A,3B increases the input range. The current sources provide DC biasing to set the quiescent point on which the input AC signal is superimposed. M1 and M2 provide transconductance for the input voltage to current conversion. The current is converted to a voltage by the output resistance. The limitation of this approach is that it requires a relatively large input for M 3A,3B to operate in the triode region. accommodate a wide output swing, the buffers are designed to achieve a rail-to-rail output [11]. Source degeneration is used to extend the linear range. Figure 4a shows the previous approach of source degeneration [11], where the equivalent resistance of M3A,3B increases the input range. The current sources provide DC biasing to set the quiescent point on which the input AC signal is superimposed. M1 and M2 provide transconductance for the input voltage to current conversion. The current is converted to a voltage by the output resistance. The limitation of this approach is that it requires a relatively large input for M3A,3B to operate in the triode region.  Source degeneration is used to extend the linear range. Figure 4a shows the previous approach of source degeneration [11], where the equivalent resistance of M3A,3B increases the input range. The current sources provide DC biasing to set the quiescent point on which the input AC signal is superimposed. M1 and M2 provide transconductance for the input voltage to current conversion. The current is converted to a voltage by the output resistance. The limitation of this approach is that it requires a relatively large input for M3A,3B to operate in the triode region.  Figure 4b shows the proposed approach where the control voltage of M 3A,3B is provided by voltage V b through a resistor R b1,b2 . This method allows the source degeneration to be controlled independently of the input level. Additionally, the gate of M 3A,3B is connected to the input terminal through a small capacitor C b1,b2 , which allows tracking of the input variations. When the input (V i1a+ , V i1a− ) changes, C b1,b2 senses the voltage and converts it to current. Then, the current charging the gate capacitance of M 3A,3B creates the control voltage, which modulates the on-resistance for source degeneration. Figure 4c shows the comparison of the transfer characteristic obtained using the output and input signal amplitudes, which indicates the improved linearity of the proposed approach. Figure 5 shows the schematic of DDA. M 1,2 and M 4,5 form the differential pair for the input transconductor. M 3A,3B and M 6A,6B provide source degeneration. The currents from the transconductors are summed at the drain of M 7 and M 9 . M 13A and M 13B operating in the triode region provide the CM feedback control. The differential output voltage, (V o1+ − V o1− ), can be written as where g mi and r oi represent the transconductance and output resistance of transistor M i , respectively.
vided by voltage Vb through a resistor Rb1,b2. This method allows the source degeneration to be controlled independently of the input level. Additionally, the gate of M3A,3B is connected to the input terminal through a small capacitor Cb1,b2, which allows tracking of the input variations. When the input (Vi1a+, Vi1a−) changes, Cb1,b2 senses the voltage and converts it to current. Then, the current charging the gate capacitance of M3A,3B creates the control voltage, which modulates the on-resistance for source degeneration. Figure 4c shows the comparison of the transfer characteristic obtained using the output and input signal amplitudes, which indicates the improved linearity of the proposed approach. Figure 5 shows the schematic of DDA. M1,2 and M4,5 form the differential pair for the input transconductor. M3A,3B and M6A,6B provide source degeneration. The currents from the transconductors are summed at the drain of M7 and M9. M13A and M13B operating in the triode region provide the CM feedback control. The differential output voltage, (Vo1+ − Vo1−), can be written as where gmi and roi represent the transconductance and output resistance of transistor Mi, respectively.   Figure 5. Schematic of the differential difference amplifier. Circuits for source degeneration is shown in blue color. (W/L)3A,3B = (W/L)6A,6B = 1 μm/0.7 μm. Rb1,b2 is realized using a diode-connected transistor having a size of (W/L) = 0.9 μm /0.7 μm. Cb1,b2 = 0.32 pF. Figure 6 shows the schematic of the transconductor (Gmc1,2). It is implemented using the operational transconductance amplifier (OTA) with three current mirrors, which is similar to the one reported in [11]. In this work, the device sizing is modified to be compatible with the supply voltage VDD = 1.8 V. The circuit is fully symmetric, and a simple current mirror is used for reduced overdrive voltage. M16A and M16B, which operate in the triode mode, are used to set the DC bias. We use VRef1 in the secondary current mirror so that M15A and M15B working in the triode region provide additional means of stabilizing the output DC level. Figure 5. Schematic of the differential difference amplifier. Circuits for source degeneration is shown in blue color. (W/L) 3A,3B = (W/L) 6A,6B = 1 µm/0.7 µm. R b1,b2 is realized using a diode-connected transistor having a size of (W/L) = 0.9 µm /0.7 µm. C b1,b2 = 0.32 pF. Figure 6 shows the schematic of the transconductor (G mc1,2 ). It is implemented using the operational transconductance amplifier (OTA) with three current mirrors, which is similar to the one reported in [11]. In this work, the device sizing is modified to be compatible with the supply voltage V DD = 1.8 V. The circuit is fully symmetric, and a simple current mirror is used for reduced overdrive voltage. M 16A and M 16B , which operate in the triode mode, are used to set the DC bias. We use V Ref1 in the secondary current mirror so that M 15A and M 15B working in the triode region provide additional means of stabilizing the output DC level.   Figure 7 shows the schematic of the preamplifier. It consists of two gain stages. The first stage (Gm1) is realized using a folded-cascode differential amplifier [15]. The second stage (Gm2) is implemented using a common-source amplifier to increase the output swing. Feedback loops are used to set the mid-band gain through Cfb1,2 and the bias of the input node through pseudo-resistors. To suppress the output ripple, the RRL forms another feedback loop. For the RRL, continuous-time implementation is used because the discretetime approach based on sampling increases the in-band noise through noise folding [16]. The input signal is upconverted by the chopper CH1, operating at the chopping frequency fCH. The signal is amplified by Gm1, and the output is downconverted by the chopper CH2. The offset at the input of Gm1 is upconverted and filtered out by the low-pass characteristic of the amplifier. A capacitive coupling consisting of the input (Cin1,2) and feedback capacitors (Cfb1,2) is built around the two-stage opamp (Gm1 and Gm2). The combination of CH1 and Cin1,2 creates an equivalent input resistance of (1/2fCHCin1,2). Similarly, CH3 and Cfb1,2 create an equivalent resistance of (1/2fCHCfb1,2). The two resistances form a  Figure 7 shows the schematic of the preamplifier. It consists of two gain stages. The first stage (G m1 ) is realized using a folded-cascode differential amplifier [15]. The second stage (G m2 ) is implemented using a common-source amplifier to increase the output swing. Feedback loops are used to set the mid-band gain through C fb1,2 and the bias of the input node through pseudo-resistors. To suppress the output ripple, the RRL forms another feedback loop. For the RRL, continuous-time implementation is used because the discretetime approach based on sampling increases the in-band noise through noise folding [16].   Figure 7 shows the schematic of the preamplifier. It consists of two gain stages. The first stage (Gm1) is realized using a folded-cascode differential amplifier [15]. The second stage (Gm2) is implemented using a common-source amplifier to increase the output swing. Feedback loops are used to set the mid-band gain through Cfb1,2 and the bias of the input node through pseudo-resistors. To suppress the output ripple, the RRL forms another feedback loop. For the RRL, continuous-time implementation is used because the discretetime approach based on sampling increases the in-band noise through noise folding [16]. Figure 7. Schematic of the CCIA using active feedback frequency compensation (AFFC) and ripplereduction loop (RRL). Cin1,2 = 15 pF, Cfb1,2 = 0.14 pF.

Instrumentation Amplifier
The input signal is upconverted by the chopper CH1, operating at the chopping frequency fCH. The signal is amplified by Gm1, and the output is downconverted by the chopper CH2. The offset at the input of Gm1 is upconverted and filtered out by the low-pass characteristic of the amplifier. A capacitive coupling consisting of the input (Cin1,2) and feedback capacitors (Cfb1,2) is built around the two-stage opamp (Gm1 and Gm2). The combination of CH1 and Cin1,2 creates an equivalent input resistance of (1/2fCHCin1,2). Similarly, CH3 and Cfb1,2 create an equivalent resistance of (1/2fCHCfb1,2). The two resistances form a feedback loop around the opamp. The input signal is upconverted by the chopper CH 1 , operating at the chopping frequency f CH . The signal is amplified by G m1 , and the output is downconverted by the chopper CH 2 . The offset at the input of G m1 is upconverted and filtered out by the low-pass characteristic of the amplifier. A capacitive coupling consisting of the input (C in1,2 ) and feedback capacitors (C fb1,2 ) is built around the two-stage opamp (G m1 and G m2 ). The combination of CH 1 and C in1,2 creates an equivalent input resistance of (1/2f CH C in1,2 ). Similarly, Sensors 2023, 23, 2536 7 of 23 CH 3 and C fb1,2 create an equivalent resistance of (1/2f CH C fb1,2 ). The two resistances form a feedback loop around the opamp.
Nested Miller compensation has been used to achieve stability under a wide range of capacitive loads [15]; however, for stability, the size of the compensation capacitor should be increased in proportion to the load capacitance. Moreover, this approach suffers from bandwidth reduction. In this work, we use AFFC, which has the advantage of extending the bandwidth using a small compensation capacitor. The AFFC is implemented using a cascode Miller (g ma and C m1 ) in parallel with a Miller capacitor (C m2 ) [17]. The cascode Miller, which is implemented using a common-gate transconductor, blocks the feedforward signal that exists in the traditional Miller compensation. Compared to the passive compensation, the gain provided by g ma reduces the size of C m1 . C m2 is used to control the Q-factor for stability. The noise power contribution of the AFFC to the inputreferred noise is relatively small when divided by (A V1 ) 2 , where A V1 ≈ 60 dB is the voltage gain of the first stage. Figure 8 shows the schematic of the folded-cascode differential amplifier (G m1 ). Two additional sets of choppers are embedded in the amplifier. One chopper is placed at the output of the cascode transistors to demodulate the signal down to the baseband while modulating the input offsets to the f CH band. Another one is placed at the drain of the current source to upmodulate the flicker noise. At the output of the amplifier, the signal returns to the baseband while the offset and flicker noise is modulated to high frequency, which is filtered by the second stage. The common-mode feedback (CMFB) loop is realized using the two differential pairs. The CMFB loop may have poles of higher frequency than that of the differential-mode (DM) loop. Therefore, we design the CMFB loop to have a smaller unity-gain frequency than the DM loop. Considering the frequency response, we determine the sizing of the two differential pairs. Nested Miller compensation has been used to achieve stability under a wide range of capacitive loads [15]; however, for stability, the size of the compensation capacitor should be increased in proportion to the load capacitance. Moreover, this approach suffers from bandwidth reduction. In this work, we use AFFC, which has the advantage of extending the bandwidth using a small compensation capacitor. The AFFC is implemented using a cascode Miller (gma and Cm1) in parallel with a Miller capacitor (Cm2) [17]. The cascode Miller, which is implemented using a common-gate transconductor, blocks the feedforward signal that exists in the traditional Miller compensation. Compared to the passive compensation, the gain provided by gma reduces the size of Cm1. Cm2 is used to control the Qfactor for stability. The noise power contribution of the AFFC to the input-referred noise is relatively small when divided by (AV1) 2 , where AV1 ≈ 60 dB is the voltage gain of the first stage. Figure 8 shows the schematic of the folded-cascode differential amplifier (Gm1). Two additional sets of choppers are embedded in the amplifier. One chopper is placed at the output of the cascode transistors to demodulate the signal down to the baseband while modulating the input offsets to the fCH band. Another one is placed at the drain of the current source to upmodulate the flicker noise. At the output of the amplifier, the signal returns to the baseband while the offset and flicker noise is modulated to high frequency, which is filtered by the second stage. The common-mode feedback (CMFB) loop is realized using the two differential pairs. The CMFB loop may have poles of higher frequency than that of the differential-mode (DM) loop. Therefore, we design the CMFB loop to have a smaller unity-gain frequency than the DM loop. Considering the frequency response, we determine the sizing of the two differential pairs. Figure 8. Schematic of the folded-cascode amplifier with common-mode feedback. Figure 9 shows the equivalent small-signal model of the amplifier. Because the openloop gain is calculated, we obtain the model by removing the feedback loops in Figure 7. It includes transconductances (gm1, gm2, and gma) and Miller capacitors (Cm1, Cm2). R1 and C1 are the output resistance and capacitance of the first gain stage, respectively. R1 is determined by the output resistance of the cascode stage, and C1 is the sum of capacitance at the output. The RL and CL are the load resistor and capacitor, respectively. Figure 8. Schematic of the folded-cascode amplifier with common-mode feedback. Figure 9 shows the equivalent small-signal model of the amplifier. Because the openloop gain is calculated, we obtain the model by removing the feedback loops in Figure 7. It includes transconductances (g m1 , g m2 , and g ma ) and Miller capacitors (C m1 , C m2 ). R 1 and C 1 are the output resistance and capacitance of the first gain stage, respectively. R 1 is determined by the output resistance of the cascode stage, and C 1 is the sum of capacitance at the output. The R L and C L are the load resistor and capacitor, respectively. Figure 9 shows the equivalent small-signal model of the amplifier. Because the openloop gain is calculated, we obtain the model by removing the feedback loops in Figure 7. It includes transconductances (gm1, gm2, and gma) and Miller capacitors (Cm1, Cm2). R1 and C1 are the output resistance and capacitance of the first gain stage, respectively. R1 is determined by the output resistance of the cascode stage, and C1 is the sum of capacitance at the output. The RL and CL are the load resistor and capacitor, respectively. Using the circuit model, the open-loop gain of the amplifier can be expressed as.
where A DC = (g m1 g m2 R 1 R L ) is the low-frequency gain. AFFC creates a left-hand plane (LHP) zero, extending the amplifier bandwidth. Assuming the conditions of (C L , C m1 , and C m2 ) >> C 1 , (g m1 R 1 , g m2 R L ) >> 1, and (g ma C L ) >> (g m2 C m1 ), we obtain two zeros (z 0 and z 1 ) and three poles (p 0 , p 1 , and p 2 ) as The 3-dB frequency is determined by p 0 , resulting in the gain-bandwidth product of GBW = g m1 /(C m1 + C m2 ). The right half plane (RHP) zero introduces the phase lag (−tan −1 (GBW/z RHP )) similar to the pole (−tan −1 (GBW/p 0,1,2 )), which reduces the phase margin (PM). The extra phase shift caused by the RHP zero degrades the amplifier stability, and the Miller capacitor (C m2 ) is used for frequency compensation.
To realize a maximally flat frequency response for stability, the Q-factor can be set to 0.7 [18]. Owing to the positive phase shift provided by LHP zero (z LHP ), AFFC can extend the bandwidth of the single-stage amplifier by more than two times [19]. Therefore, when p 1 is placed close to twice the value of GBW, the amplifier stability can still be achieved as To compensate for the negative phase shift caused by p 1 , the location of z 0 is selected as Using Equations (6) and (7), we obtain the expression for g ma as To obtain the expression for C m1 , we substitute p 1 of Equation (5) into Equation (7). Using the expression for g ma given by Equation (8), we obtain where we use relatively small capacitors of C m1 = 0.8 pF and C m2 = 0.2 pF. The g ma is implemented using a common-gate transistor having a size of (W/L) = 0.9 µm/0.7 µm. The PM of the amplifier with pole-zero cancellation can be expressed as where the quality factor is expressed as Q = |p 1,2 |/(2|Re{p 1,2 }|) in case when complex poles are formed for p 1 and p 2 [20]. A detailed derivation of the complex poles and the Q-factor can be found in the Appendix A. Figure 10 shows the comparison of the open-loop gain of the amplifier using AFFC and conventional Miller compensation. The bandwidth is extended by the LHP zero available in the AFFC. The PM is reduced from 82.2 • to 60 • ; it guarantees stable operation. Figure 11 explains the operation of the RRL, and its implementation is similar to the previous work [21]. The process variation creates offsets. G m1 and G m2 are associated with the offset voltages V OS1 and V OS2 , respectively. The V OS2 is not chopped but suppressed by the open-loop gain (A OL1 ) of the preceding stage (G m1 ). Therefore, the input-referred offset can be written as (V OS1 + V OS2 /A OL1 ). The system offset amplified by G m1 creates the offset current. The current is up-converted to f CH by CH 2 , and integrated by G m2 and C m2 , producing the output ripple V out,ripple . At the output, a sense capacitor C S1 converts V out,ripple to a current I AC,ripple . The current demodulated by the chopper CH 3 is converted to I DC,ripple . The current integrated by G m3 and C int generates the integrator output V int , which is converted to the voltage V RRL by G m4 . To cancel the offset current generated by V OS , the V RRL is input to G m1 .
Sensors 2023, 23, x FOR PEER REVIEW 9 of 24 Figure 10 shows the comparison of the open-loop gain of the amplifier using AFFC and conventional Miller compensation. The bandwidth is extended by the LHP zero available in the AFFC. The PM is reduced from 82.2° to 60°; it guarantees stable operation. Figure 11 explains the operation of the RRL, and its implementation is similar to the previous work [21]. The process variation creates offsets. Gm1 and Gm2 are associated with the offset voltages VOS1 and VOS2, respectively. The VOS2 is not chopped but suppressed by the open-loop gain (AOL1) of the preceding stage (Gm1). Therefore, the input-referred offset can be written as (VOS1 + VOS2/AOL1). The system offset amplified by Gm1 creates the offset current. The current is up-converted to fCH by CH2, and integrated by Gm2 and Cm2, producing the output ripple Vout,ripple. At the output, a sense capacitor CS1 converts Vout,ripple to a current IAC,ripple. The current demodulated by the chopper CH3 is converted to IDC,ripple. The current integrated by Gm3 and Cint generates the integrator output Vint, which is converted to the voltage VRRL by Gm4. To cancel the offset current generated by VOS, the VRRL is input to Gm1.  Figure 12 shows a block diagram of the BE signal processing IC. It consists of five channels for three types of measurements (ECG, BP, and IMP). Each channel includes an instrumentation amplifier (IA), a programmable gain amplifier (PGA), and a low-pass filter (LPF). The IC includes a multiphase clock generator, a bias generator/bandgap, and a  Figure 11 explains the operation of the RRL, and its implementation is similar to the previous work [21]. The process variation creates offsets. Gm1 and Gm2 are associated with the offset voltages VOS1 and VOS2, respectively. The VOS2 is not chopped but suppressed by the open-loop gain (AOL1) of the preceding stage (Gm1). Therefore, the input-referred offset can be written as (VOS1 + VOS2/AOL1). The system offset amplified by Gm1 creates the offset current. The current is up-converted to fCH by CH2, and integrated by Gm2 and Cm2, producing the output ripple Vout,ripple. At the output, a sense capacitor CS1 converts Vout,ripple to a current IAC,ripple. The current demodulated by the chopper CH3 is converted to IDC,ripple. The current integrated by Gm3 and Cint generates the integrator output Vint, which is converted to the voltage VRRL by Gm4. To cancel the offset current generated by VOS, the VRRL is input to Gm1.  Figure 12 shows a block diagram of the BE signal processing IC. It consists of five channels for three types of measurements (ECG, BP, and IMP). Each channel includes an instrumentation amplifier (IA), a programmable gain amplifier (PGA), and a low-pass filter (LPF). The IC includes a multiphase clock generator, a bias generator/bandgap, and a  Figure 12 shows a block diagram of the BE signal processing IC. It consists of five channels for three types of measurements (ECG, BP, and IMP). Each channel includes an instrumentation amplifier (IA), a programmable gain amplifier (PGA), and a low-pass filter (LPF). The IC includes a multiphase clock generator, a bias generator/bandgap, and a multiplexer. The bias voltages are generated from the internal bandgap. The multiplexed outputs are digitized using a 12-b analog-to-digital converter (ADC) [22]. The ADC is implemented on a separate test board. The QRS peak detection and BP calculation are performed using a field programmable gate array (FPGA).

Back-End Signal Processing IC
Sensors 2023, 23, x FOR PEER REVIEW 10 of 24 multiplexer. The bias voltages are generated from the internal bandgap. The multiplexed outputs are digitized using a 12-b analog-to-digital converter (ADC) [22]. The ADC is implemented on a separate test board. The QRS peak detection and BP calculation are performed using a field programmable gate array (FPGA). The BP channel extracts the information related to the QRS complex using the inphase and quadrature chopping frequencies of fBPI = (fCH + Δf)(0°) and fBPQ = (fCH + Δf)(90°), respectively. The offset Δf is used to compensate for the channel delay. The IMP channel uses the in-phase and quadrature chopping frequencies of fIMPI = fAC(0°) and fIMPQ = fAC(90°), respectively, where fAC is the AC frequency of the current driver. The non-overlapping clocks are generated from the clock divider and multiphase clock generator. Because there is no input chopper in the IMP channel, the ECG signal is upmodulated to fAC at the IA output of the IMP channel, which is suppressed by the LPF [8]. If fAC = 4 kHz and fCH = 2 kHz is chosen, the signal input to the ECG and BP channels experiences two times frequency modulation, and the residual signals at 4 kHz and 8 kHz can be suppressed by the LPF. Figure 13 shows the schematic of the IA using capacitive coupling. It consists of a folded-cascode amplifier (Gm5), re-used from the preamplifier (Figure 8) without the RRL input. The input and feedback capacitors (Cin1,2 and Cfb1,2) determine the closed-loop gain (Cin1,2/Cfb1,2), and the pseudo-resistors define the CM voltage. 3 ECG channel The BP channel extracts the information related to the QRS complex using the in-phase and quadrature chopping frequencies of f BPI = (f CH + ∆f )(0 • ) and f BPQ = (f CH + ∆f )(90 • ), respectively. The offset ∆f is used to compensate for the channel delay. The IMP channel uses the in-phase and quadrature chopping frequencies of f IMPI = f AC (0 • ) and f IMPQ = f AC (90 • ), respectively, where f AC is the AC frequency of the current driver. The non-overlapping clocks are generated from the clock divider and multiphase clock generator. Because there is no input chopper in the IMP channel, the ECG signal is upmodulated to f AC at the IA output of the IMP channel, which is suppressed by the LPF [8]. If f AC = 4 kHz and f CH = 2 kHz is chosen, the signal input to the ECG and BP channels experiences two times frequency modulation, and the residual signals at 4 kHz and 8 kHz can be suppressed by the LPF. Figure 13 shows the schematic of the IA using capacitive coupling. It consists of a folded-cascode amplifier (G m5 ), re-used from the preamplifier (Figure 8) without the RRL input. The input and feedback capacitors (C in1,2 and C fb1,2 ) determine the closed-loop gain (C in1,2 /C fb1,2 ), and the pseudo-resistors define the CM voltage. Figure 14 shows the schematic of PGA. It consists of an operational transconductance amplifier (OTA), switches, and an array of capacitors. The first stage of the OTA uses a differential amplifier with internal positive feedback for gain boosting [15]. The second stage uses a common-source amplifier for increased output swing. The CMFB is implemented using a switched-capacitor (SC) network clocked by ϕ 1 and ϕ 2 [23]. When ϕ 1 is high (ϕ 2 is low), the amplifier operates in the negative feedback mode using the input capacitor (C IN ) and the feedback capacitor (C FB ). When ϕ 2 is high (ϕ 1 is low), it operates in CMFB mode using the CM input (V ICM ) and the output (V OCM ). The low-frequency closed-loop gain (A CL ) can be expressed as where A OL is the open-loop gain of the OTA. The feedback capacitor is given by C FB = C U = 100 fF. The C IN is the capacitor sum connected to the input, which is determined by closed switches (S 0 -S 2 ). The A CL is variable from 1 to 15 (v/v) by controlling the three switches.
Sensors 2023, 23, x FOR PEER REVIEW 11 of 24 Figure 13. Schematic of the instrumentation amplifier. Figure 14 shows the schematic of PGA. It consists of an operational transconductance amplifier (OTA), switches, and an array of capacitors. The first stage of the OTA uses a differential amplifier with internal positive feedback for gain boosting [15]. The second stage uses a common-source amplifier for increased output swing. The CMFB is implemented using a switched-capacitor (SC) network clocked by φ1 and φ2 [23]. When φ1 is high (φ2 is low), the amplifier operates in the negative feedback mode using the input capacitor (CIN) and the feedback capacitor (CFB). When φ2 is high (φ1 is low), it operates in CMFB mode using the CM input (VICM) and the output (VOCM). The low-frequency closedloop gain (ACL) can be expressed as where AOL is the open-loop gain of the OTA. The feedback capacitor is given by CFB = CU = 100 fF. The CIN is the capacitor sum connected to the input, which is determined by closed switches (S0-S2). The ACL is variable from 1 to 15 (v/v) by controlling the three switches.  Figure 13. Schematic of the instrumentation amplifier. Figure 13. Schematic of the instrumentation amplifier. Figure 14 shows the schematic of PGA. It consists of an operational transconductance amplifier (OTA), switches, and an array of capacitors. The first stage of the OTA uses a differential amplifier with internal positive feedback for gain boosting [15]. The second stage uses a common-source amplifier for increased output swing. The CMFB is implemented using a switched-capacitor (SC) network clocked by φ1 and φ2 [23]. When φ1 is high (φ2 is low), the amplifier operates in the negative feedback mode using the input capacitor (CIN) and the feedback capacitor (CFB). When φ2 is high (φ1 is low), it operates in CMFB mode using the CM input (VICM) and the output (VOCM). The low-frequency closedloop gain (ACL) can be expressed as where AOL is the open-loop gain of the OTA. The feedback capacitor is given by CFB = CU = 100 fF. The CIN is the capacitor sum connected to the input, which is determined by closed switches (S0-S2). The ACL is variable from 1 to 15 (v/v) by controlling the three switches.  Figure 15 shows the schematic of the LPF. Using the unit capacitor C = 100 fF, the states of the switches (S3-S6) determine the cutoff frequency. The number of SC stages determines the order of the filter. Figure 16 shows the simulated frequency responses of the LPFs. The ECG channel uses the first-order LPF to set the cutoff frequency close to 1.5 kHz. The IMP and BP channels use the second and third-order LPF to set the cutoff frequency at 60 Hz and 50 Hz, respectively.  Figure 15 shows the schematic of the LPF. Using the unit capacitor C = 100 fF, the states of the switches (S 3 -S 6 ) determine the cutoff frequency. The number of SC stages determines the order of the filter. Figure 16 shows the simulated frequency responses of the LPFs. The ECG channel uses the first-order LPF to set the cutoff frequency close to 1.5 kHz. The IMP and BP channels use the second and third-order LPF to set the cutoff frequency at 60 Hz and 50 Hz, respectively.   Figure 17 shows the fabricated ICs for ECG/ETI system using the 180 nm CMOS process. The core size of the current driver and the preamplifier are 0.065 mm 2 and 0.29 mm 2 , respectively. The core area of the BE signal processing IC is 0.9 mm 2 . The chips are mounted on three test boards for individual characterization using the chip-on-board (COB) technique. After functional testing, they are assembled for the ECG/ETI system characterization.   Figure 17 shows the fabricated ICs for ECG/ETI system using the 180 nm CMOS process. The core size of the current driver and the preamplifier are 0.065 mm 2 and 0.29 mm 2 , respectively. The core area of the BE signal processing IC is 0.9 mm 2 . The chips are mounted on three test boards for individual characterization using the chip-on-board (COB) technique. After functional testing, they are assembled for the ECG/ETI system characterization.  Figure 17 shows the fabricated ICs for ECG/ETI system using the 180 nm CMOS process. The core size of the current driver and the preamplifier are 0.065 mm 2 and 0.29 mm 2 , respectively. The core area of the BE signal processing IC is 0.9 mm 2 . The chips are mounted on three test boards for individual characterization using the chip-onboard (COB) technique. After functional testing, they are assembled for the ECG/ETI system characterization.   Figure 17 shows the fabricated ICs for ECG/ETI system using the 180 nm CMOS process. The core size of the current driver and the preamplifier are 0.065 mm 2 and 0.29 mm 2 , respectively. The core area of the BE signal processing IC is 0.9 mm 2 . The chips are mounted on three test boards for individual characterization using the chip-on-board (COB) technique. After functional testing, they are assembled for the ECG/ETI system characterization.  Figure 18 shows the measured transconductances of the current driver at 10 kHz using a load of (1 kΩ || 20 pF). The transconductance is relatively constant over the input range from −90 mV to +90 mV. Figure 19a shows the schematic of characterizing the output impedance Z OUT of the current driver. The differential input of the driver is generated using the Keysight 33500B with a high stability time base option. The output current is set to 200 µA by adjusting the input. The Z OUT value is obtained using two resistances (R L1 = 100 Ω, R L2 = 4.7 kΩ) and recording the change in the output voltage. The magnitude of Z OUT can be expressed as

Measured Results
where V L1 and V L2 are measured voltages using R L1 and R L2 , respectively [24]. The measured |Z OUT | is kept constant at 1 MΩ up to 500 kHz, reducing to 300 kΩ at 1 MHz. Figure 19b shows the measured output current as a function of frequency for three inputs. The injected current is measured using the voltage across a 100 Ω resistor, which is in series with the output load of (1 kΩ || 20 pF). For the input of 80 mV pp , the output current is relatively constant, up to 10 kHz, with a maximum error of 0.63%. The driver can operate up to 1 MHz, where the current is reduced to 0.13 mV pp . Figure 19c shows the output current as a function of load impedance. The data are measured at 100 Hz, and a current up to 600 µA pp can be injected into the low impedance load using 120 mV pp .
Sensors 2023, 23, x FOR PEER REVIEW 13 of 24 Figure 17. Microphotograph of (a) current driver, (b) preamplifier, (c) back-end signal processing IC. Figure 18 shows the measured transconductances of the current driver at 10 kHz using a load of (1 kΩ || 20 pF). The transconductance is relatively constant over the input range from −90 mV to +90 mV. Figure 19a shows the schematic of characterizing the output impedance ZOUT of the current driver. The differential input of the driver is generated using the Keysight 33500B with a high stability time base option. The output current is set to 200 μA by adjusting the input. The ZOUT value is obtained using two resistances (RL1 = 100 Ω, RL2 = 4.7 kΩ) and recording the change in the output voltage. The magnitude of ZOUT can be expressed as where VL1 and VL2 are measured voltages using RL1 and RL2, respectively [24]. The measured |ZOUT| is kept constant at 1 MΩ up to 500 kHz, reducing to 300 kΩ at 1 MHz. Figure  19b shows the measured output current as a function of frequency for three inputs. The injected current is measured using the voltage across a 100 Ω resistor, which is in series with the output load of (1 kΩ || 20 pF). For the input of 80 mVpp, the output current is relatively constant, up to 10 kHz, with a maximum error of 0.63%. The driver can operate up to 1 MHz, where the current is reduced to 0.13 mVpp. Figure 19c shows the output current as a function of load impedance. The data are measured at 100 Hz, and a current up to 600 μApp can be injected into the low impedance load using 120 mVpp.  Figure 20a shows the gain response (single-ended) of the preamplifier measured using a Keysight 35670A signal analyzer. The mid-band gain is 39.4 dB (differential) at 100 Hz by consuming 0.56 µA (including bias circuit) from V DD = 1.8 V. The mid-band commonmode rejection ratio (CMRR) and power-supply rejection ratio (PSRR) are 61 dB and 66 dB, respectively. Figure 20b shows the measured noise spectral density using f CH = 2 kHz. The input noise voltage density is 65 nV/ √ Hz with a 1/f corner frequency of 2.5 Hz. The integrated noise from 0.5 to 100 Hz is 1.14 µV rms .
x FOR PEER REVIEW 13 of 24 Figure 17. Microphotograph of (a) current driver, (b) preamplifier, (c) back-end signal processing IC. Figure 18 shows the measured transconductances of the current driver at 10 kHz using a load of (1 kΩ || 20 pF). The transconductance is relatively constant over the input range from −90 mV to +90 mV. Figure 19a shows the schematic of characterizing the output impedance ZOUT of the current driver. The differential input of the driver is generated using the Keysight 33500B with a high stability time base option. The output current is set to 200 μA by adjusting the input. The ZOUT value is obtained using two resistances (RL1 = 100 Ω, RL2 = 4.7 kΩ) and recording the change in the output voltage. The magnitude of ZOUT can be expressed as where VL1 and VL2 are measured voltages using RL1 and RL2, respectively [24]. The measured |ZOUT| is kept constant at 1 MΩ up to 500 kHz, reducing to 300 kΩ at 1 MHz. Figure  19b shows the measured output current as a function of frequency for three inputs. The injected current is measured using the voltage across a 100 Ω resistor, which is in series with the output load of (1 kΩ || 20 pF). For the input of 80 mVpp, the output current is relatively constant, up to 10 kHz, with a maximum error of 0.63%. The driver can operate up to 1 MHz, where the current is reduced to 0.13 mVpp. Figure 19c shows the output current as a function of load impedance. The data are measured at 100 Hz, and a current up to 600 μApp can be injected into the low impedance load using 120 mVpp.  Figure 20a shows the gain response (single-ended) of the preamplifier measured using a Keysight 35670A signal analyzer. The mid-band gain is 39.4 dB (differential) at 100 Hz by consuming 0.56 μA (including bias circuit) from VDD = 1.8 V. The mid-band common-mode rejection ratio (CMRR) and power-supply rejection ratio (PSRR) are 61 dB and 66 dB, respectively. Figure 20b shows the measured noise spectral density using fCH = 2 kHz. The input noise voltage density is 65 nV/√Hz with a 1/f corner frequency of 2.5 Hz. The integrated noise from 0.5 to 100 Hz is 1.14 μVrms.  Figure 20a shows the gain response (single-ended) of the preamplifier measured using a Keysight 35670A signal analyzer. The mid-band gain is 39.4 dB (differential) at 100 Hz by consuming 0.56 μA (including bias circuit) from VDD = 1.8 V. The mid-band common-mode rejection ratio (CMRR) and power-supply rejection ratio (PSRR) are 61 dB and 66 dB, respectively. Figure 20b shows the measured noise spectral density using fCH = 2 kHz. The input noise voltage density is 65 nV/√Hz with a 1/f corner frequency of 2.5 Hz. The integrated noise from 0.5 to 100 Hz is 1.14 μVrms. Next, we present the measured result of BE signal processing IC. Figure 21 shows the measured gain control of the ECG channel. When all the switches of the PGA are in the OFF state, the mid-band gain is 20 dB. When all the switches are in the ON state, the PGA gain is 23 dB, which leads to an overall gain of 43 dB. Figure 22 shows the input noise density of the ECG channel measured using 40 dB gain by consuming 0.4 μA at 1.8 V.
When the chopper is turned on, 1/f noise is effectively suppressed, resulting in a corner frequency of 2 Hz and noise density of 70 nV/√Hz. Figure 23 shows the amplified ECG signal for the input cardiac signal having Vpp = 12 mV (differential), generated from a function generator Keysight 33500B. The output shows Vpp = 600 mV (single-ended), indicating a 40 dB gain.  Next, we present the measured result of BE signal processing IC. Figure 21 shows the measured gain control of the ECG channel. When all the switches of the PGA are in the OFF state, the mid-band gain is 20 dB. When all the switches are in the ON state, the PGA gain is 23 dB, which leads to an overall gain of 43 dB. Figure 22 shows the input noise density of the ECG channel measured using 40 dB gain by consuming 0.4 µA at 1.8 V. When the chopper is turned on, 1/f noise is effectively suppressed, resulting in a corner frequency of 2 Hz and noise density of 70 nV/ √ Hz. Figure 23 shows the amplified ECG signal for the input cardiac signal having V pp = 12 mV (differential), generated from a function generator Keysight 33500B. The output shows V pp = 600 mV (single-ended), indicating a 40 dB gain. Next, we present the measured result of BE signal processing IC. Figure 21 shows the measured gain control of the ECG channel. When all the switches of the PGA are in the OFF state, the mid-band gain is 20 dB. When all the switches are in the ON state, the PGA gain is 23 dB, which leads to an overall gain of 43 dB. Figure 22 shows the input noise density of the ECG channel measured using 40 dB gain by consuming 0.4 μA at 1.8 V.
When the chopper is turned on, 1/f noise is effectively suppressed, resulting in a corner frequency of 2 Hz and noise density of 70 nV/√Hz. Figure 23 shows the amplified ECG signal for the input cardiac signal having Vpp = 12 mV (differential), generated from a function generator Keysight 33500B. The output shows Vpp = 600 mV (single-ended), indicating a 40 dB gain.   Figure 24 shows the measured results of the in-phase and quadrature IMP channels. The result is obtained by injecting current at three frequencies (f AC = 1, 4, and 5 kHz). The baseband output is observed when the demodulation chopper frequency is set to 5 kHz. The measured waveforms show that the output amplitude decreases with the increase in the capacitance value from 15 to 330 pF. Figure 25 shows the measured range of the ETI system. A resistor and a capacitor under the test are connected between the inputs of two AEs. When we use a sinusoidal current of 88 µA pp at 1 kHz, the detection range using 69 dB channel gain is from 100 mΩ to 120 Ω. When the injected current is reduced to 215 nA pp with the minimum PGA gain setting, the maximum range can be extended to 3 kΩ. The minimum range is extended to 10 mΩ using the maximum PGA gain. The simulated results agree well with the value of the reference resistance over the range. In the case of capacitance, the detection of the minimum value is limited by the parasitics of wiring capacitance in the test board. The measured linear range of capacitance is from 100 nF to 100 µF.   Figure 24 shows the measured results of the in-phase and quadrature IMP channels. The result is obtained by injecting current at three frequencies (fAC = 1, 4, and 5 kHz). The baseband output is observed when the demodulation chopper frequency is set to 5 kHz. The measured waveforms show that the output amplitude decreases with the increase in the capacitance value from 15 to 330 pF. Figure 25 shows the measured range of the ETI system. A resistor and a capacitor under the test are connected between the inputs of two AEs. When we use a sinusoidal current of 88 μApp at 1 kHz, the detection range using 69 dB channel gain is from 100 mΩ to 120 Ω. When the injected current is reduced to 215 nApp with the minimum PGA gain setting, the maximum range can be extended to 3 kΩ. The minimum range is extended to 10 mΩ using the maximum PGA gain. The simulated results agree well with the value of the reference resistance over the range. In the case of capacitance, the detection of the minimum value is limited by the parasitics of wiring capacitance in the test board. The measured linear range of capacitance is from 100 nF to 100 μF.   Figure 24 shows the measured results of the in-phase and quadrature IMP channels. The result is obtained by injecting current at three frequencies (fAC = 1, 4, and 5 kHz). The baseband output is observed when the demodulation chopper frequency is set to 5 kHz. The measured waveforms show that the output amplitude decreases with the increase in the capacitance value from 15 to 330 pF. Figure 25 shows the measured range of the ETI system. A resistor and a capacitor under the test are connected between the inputs of two AEs. When we use a sinusoidal current of 88 μApp at 1 kHz, the detection range using 69 dB channel gain is from 100 mΩ to 120 Ω. When the injected current is reduced to 215 nApp with the minimum PGA gain setting, the maximum range can be extended to 3 kΩ. The minimum range is extended to 10 mΩ using the maximum PGA gain. The simulated results agree well with the value of the reference resistance over the range. In the case of capacitance, the detection of the minimum value is limited by the parasitics of wiring capacitance in the test board. The measured linear range of capacitance is from 100 nF to 100 μF.  (a) (b) Figure 25. Measured range of the ETI system for (a) differential resistance and (b) differential capacitance. The values of the injected current are also shown. Figure 26 shows the measured results of the BP channels using a gain of 43 dB, fCH = 2 kHz, and ∆f = 50 Hz. The input cardiac signal having Vpp = 20 mV is generated using a function generator. Figure 27 shows the measured waveforms of the ECG and IMP channels. The electrodes attached to the wrists are connected to the current driver. A differential current of 303 μApp is injected into the electrode. Other sets of electrodes are connected between the body and test boards (AE and BE), thus amplifying the biopotential signal using 45 dB gain. The environmental noise is suppressed using a filtering function of the Keysight MSO-X oscilloscope. The motion artifact is induced by applying a hard push to the electrode. The result shows a successful operation of the proposed ETI system in vivo, where the ECG signals are measured while ETI is monitored.  Figure 26 shows the measured results of the BP channels using a gain of 43 dB, f CH = 2 kHz, and ∆f = 50 Hz. The input cardiac signal having V pp = 20 mV is generated using a function generator. Figure 27 shows the measured waveforms of the ECG and IMP channels. The electrodes attached to the wrists are connected to the current driver. A differential current of 303 µA pp is injected into the electrode. Other sets of electrodes are connected between the body and test boards (AE and BE), thus amplifying the biopotential signal using 45 dB gain. The environmental noise is suppressed using a filtering function of the Keysight MSO-X oscilloscope. The motion artifact is induced by applying a hard push to the electrode. The result shows a successful operation of the proposed ETI system in vivo, where the ECG signals are measured while ETI is monitored. Figure 28 shows the block diagram of the peak detection method based on Pan and Tompkins [25]. The magnitude of the signal derivative is processed through a movingaverage filter. The detection threshold is set using the measured BP signal. The threshold detects the region of the QRS complexes. Additionally, a time domain search is performed around the detected beat to enhance the accuracy of locating the peak. Figure 29 shows the output of the processed waveform, indicating the successful detection of the ECG peaks. The power breakdown given in Table 1 shows that power consumption is dominated by the current driver. Table 2 shows the performance summary. The proposed ETI system is realized using a 1.26 mm 2 (excluding ADC) consuming 3.6 mW from a 1.8 V single power supply.   Figure 28 shows the block diagram of the peak detection method based on Pan and Tompkins [25]. The magnitude of the signal derivative is processed through a movingaverage filter. The detection threshold is set using the measured BP signal. The threshold detects the region of the QRS complexes. Additionally, a time domain search is performed around the detected beat to enhance the accuracy of locating the peak. Figure 29 shows the output of the processed waveform, indicating the successful detection of the ECG peaks. The power breakdown given in Table 1 shows that power consumption is dominated by the current driver. Table 2 shows the performance summary. The proposed ETI system is realized using a 1.26 mm 2 (excluding ADC) consuming 3.6 mW from a 1.8 V single power supply.        Table 3 shows a comparison of the current drivers reported in the previous works [11,24,[26][27][28]. In [26], electrical impedance tomography (EIT) for hand prosthesis control is proposed for the human-machine interface. The implemented IC uses a fully differential current driver and a current feedback IA, achieving a maximum output current of up to 1 mA pp ; however, the bandwidth (500 kHz) is lower than ours, and the THD (−42 dB or 0.79%) performance needs further improvement. Work [27] presents a currentconveyor-based current driver for EIT, achieving a wide bandwidth of up to 10 MHz. Targeted for EIT prostate and breast cancer detection, this work shows a high drive current of up to 1.2 mA pp ; however, the output impedance (101 kΩ) at 1 MHz is lower than ours. The two works [24,27] use a high supply (18 V and 3.3 V), increasing power consumption. Work [28] presents a current driver IC for a portable EIT system, achieving a relatively high output impedance (1 MΩ at 1 MHz) using a 1.2 V supply; however, the maximum output current is limited to 400 µA pp with relatively high THD. The proposed driver features a high output impedance (1 MΩ) and operates at a low supply (1.8 V) suitable for portable system applications.  Table 4 shows a comparison of the system with other works [29][30][31][32]. Work [29] presents a low-power (0.221 mW) readout IC using a digital-assisted baseline impedance cancellation technique, providing an extended frequency (1 MHz) measurement; however, the impedance range and resolution are lower than ours. In [30], a six-channel EIT system for portable breast cancer detection is proposed and validated in a wearable setting. The system provides a good signal-to-noise (SNR) of up to 90 dB; however, the impedance range is not shown, and it consumes a relatively high power (53.4 mW). Work [31] presents a high input impedance, low noise ETI sensor system using a current mismatch cancellation technique, achieving a relatively good resolution (0.5 mΩ) and low power (0.128 mW); however, the current is limited to 100 µA pp demanding a high gain, high power preamplifier. Work [32] is a commercial system with a balanced impedance range, resolution, and power consumption. Compared to other works, the proposed system achieves the lowest minimum impedance value, a relatively good resolution, and a high driver current. The system is realized using 3.6 mW power suitable for portable applications.

Conclusions
This paper presents an active-electrode ECG/ETI sensor system using a wideband low-noise IA and a high-impedance current driver. The balanced current driver uses a matched current source and sink, which operate under negative feedback to increase the output impedance. To increase the linear input range, a new source degeneration method is proposed. The measured output impedance of the driver is 1 MΩ and 300 kΩ at 500 kHz and 1 MHz, respectively. The AFFC technique is applied for the preamplifier to achieve a wide bandwidth using a small Miller compensation capacitor. The proposed IA achieves a noise density and 1/f noise corner of 65 nV/ √ Hz and 2.5 Hz, respectively. The BE signal processing IC is designed for three types of signal monitoring (ECG, BP, and IMP). The measured results show that the output of the BP channel is successfully used for real-time detection of the QRS complex in the ECG signal. Using the gain programmability, the detection range of the IMP channel is increased from 25 to 43 dB. The resistance detection range is from 10 mΩ to 3 kΩ, and the capacitive range is from 100 nF to 100 µF. Characterizing the complete system shows successful detection of the motion artifact while measuring the ECG/ETI using 3.6 mW.