Shadow Filters Using Multiple-Input Differential Difference Transconductance Amplifiers

This paper presents new voltage-mode shadow filters employing a low-power multiple-input differential difference transconductance amplifier (MI-DDTA). This device provides multiple-input voltage-mode arithmetic operation capability, electronic tuning ability, high-input and low-output impedances. Therefore, the proposed shadow filters offer circuit simplicity, minimum number of active and passive elements, electronic control of the natural frequency and the quality factor, and high-input and low-output impedances. The proposed MI-DDTA can work with supply voltage of ±0.5 V and consumes 9.94 μW of power. The MI-DDTA and shadow filters have been designed and simulated with the SPICE program using 0.18 μm CMOS process parameters to validate the functionality and workability of the new circuits.


Introduction
The universal filters are the systems that can realize several filtering functions into the same topology such as low-pass (LP), high-pass (HP), band-pass (BP), band-stop (BS), and all-pass (AP) filters, usually with second-order transfer functions [1][2][3][4][5]. These second-order filters can be applied for three-way high-fidelity loud-speakers, phase-locked loops, and high-order filters [6][7][8]. The filters with orthogonal control of the natural frequency and the quality factor are usually required because it is easy to design the required operating frequency and the required quality factor.
The shadow filter was first introduced in [9]. It consists of a conventional universal filter with LP and BP outputs, summing circuit, and an external amplifier. The output signal of the LP filter is amplified by the external amplifier and fed back to the summing circuit at the input of the universal filter. The adjustable gain of the amplifier can be used to modify the natural frequency and the quality factor of the universal filters, which is valuable for trimming the parameters of filters when non-ideal effects are occurred. The concept of the shadow filter in [9] was developed next to obtain both modification of the natural frequency and the quality factor with an external amplifier [10].
In this paper a new voltage-mode shadow filters using low-voltage and low-power multiple-input differential difference transconductance amplifiers (MI-DDTA) have been proposed. The MI-DDTA offers multiple-input addition and subtraction of voltages, which is possible by using the multiple-input gate-driven MOS transistor (MIGD MOST) technique [31][32][33][34][35][36]. The proposed filters offer high-input and low output impedance which is required for cascading in voltage-mode circuits. The natural frequency and the quality factor can be controlled electronically. The proposed circuits can work with ±0.5 V supply and they have been designed and simulated with SPICE, using 0.18 µm CMOS process parameters to verify the functionality and workability of the new circuits.
It is worth noting that the DDTAs using multiple-input bulk-driven MOST technique have been proposed already in [37][38][39]. The DDTAs in [37,38] use a 0.5 V of supply voltage, and the DDTA in [39] uses a 0.3 V of supply voltage. These DDTAs consume ultra-low power in the range of nano watt; however, they are suitable for applications operating with limited bandwidth in the range of a few hundred Hz like applications in biomedical systems. Figure 1a shows the electrical symbol of the MI-DDTA. The low-frequency characteristics of the device are given by:

Proposed MI-DDTA
In brief, the operation of the circuit could be characterized as follows: the voltage at the low-impedance output w is a sum of two differential input voltages V y1 = V y+1 − V y−2 and V y2 = V y+2 − V y−1 . The output current I o at the high-impedance output o is equal to the product of V w , and a transconductance gain g m , namely, the second equation of (1) describes a voltage-controlled current source. The CMOS structure of the proposed MI-DDTA is shown in Figure 1b. It consists of a differential difference amplifier (DDA) with unity gain feedback, followed by a transconductance amplifier (TA).
The unity gain DDA consists of a differential stage based on the flipped voltage follower M 1 -M 5 that allowed the minimum voltage supply to be as low as the sum of one gatesource (V GS-M3 ) and one drain source (V DS-M5 ) voltage, i.e., V DDmin = V GS-M3 + V DS-M5 ; hence, the low voltage supply capability is guaranteed. To increase the number of inputs of the differential pair M 1 and M 2 , the multiple-input gate-driven MOS transistor (MI-GD-MOST) technique is used [31][32][33][34][35][36]. This multiple-input increase the arithmetic operation capability of the DDTA circuit. Figure 1a shows the electrical symbol of the MI-DDTA. The low-frequency characteristics of the device are given by: MI-DDTA y +1 o w y +n y -1 y -n V y+1 V y+n V y-1 V y-n In brief, the operation of the circuit could be characterized as follows: the voltage at the low-impedance output w is a sum of two differential input voltages 1 = +1 − −2 and 2 = +2 − −1 . The output current at the high-impedance output o is equal to the product of , and a transconductance gain , namely, the second equation of (1) describes a voltage-controlled current source. The CMOS structure of the proposed MI-DDTA is shown in Figure 1b. It consists of a differential difference amplifier (DDA) with unity gain feedback, followed by a transconductance amplifier (TA).
The unity gain DDA consists of a differential stage based on the flipped voltage follower M1-M5 that allowed the minimum voltage supply to be as low as the sum of one gate-source (VGS-M3) and one drain source (VDS-M5) voltage, i.e., VDDmin = VGS-M3 + VDS-M5; hence, the low voltage supply capability is guaranteed. To increase the number of inputs of the differential pair M1 and M2, the multiple-input gate-driven MOS transistor (MI-GD-MOST) technique is used [31][32][33][34][35][36]. This multiple-input increase the arithmetic operation capability of the DDTA circuit.
The symbol of the MI-GD-MOST and its implementation is shown in Figure 2. The arbitrary number of inputs V1,…Vn are simply obtained by parallel connection of the input capacitor CG and two anti-parallel MOS transistors ML operating in cutoff region, hence creating high resistance value with minimum occupied chip area. These high resistances are essential for proper DC operation of the circuit while the input capacitors ensure the AC path for the input signals. The second stage of the unity gain DDA is created by class-AB stage M6, M7 and high resistance RMOS. This RMOS is also created by two cut-off transistors ML, and ensures the proper DC bias current of this output stage, while the capacitor C ensures the AC path for the signal; hence a simple class-AB stage is obtained. The compensation capacitor Cc ensure the stability of the DDA circuit. The symbol of the MI-GD-MOST and its implementation is shown in Figure 2. The arbitrary number of inputs V 1 , . . . V n are simply obtained by parallel connection of the input capacitor C G and two anti-parallel MOS transistors M L operating in cutoff region, hence creating high resistance value with minimum occupied chip area. These high resistances are essential for proper DC operation of the circuit while the input capacitors ensure the AC path for the input signals. The second stage of the unity gain DDA is created by class-AB stage M 6 , M 7 and high resistance R MOS . This R MOS is also created by two cut-off transistors M L , and ensures the proper DC bias current of this output stage, while the capacitor C ensures the AC path for the signal; hence a simple class-AB stage is obtained. The compensation capacitor C c ensure the stability of the DDA circuit. β = α·g m1,2 (r ds1,2 r ds4,5 )(g m6 + g m7 )(r ds1,2 r ds4,5 ) 1 + α·g m1,2 (r ds1,2 r ds4,5 )(g m6 + g m7 )(r ds1,2 r ds4,5 ) where β is the voltage gain of the capacitive voltage divider, at the gates of M 1 and M 2 , which neglecting the impact of the parasitic capacitances of MOS transistor, can be approximated as: where n is the number of differential inputs of the MI-DDTA (note that one more capacitor C G0 is used in feedback connection). Assuming n = 2 and C G0 = C G1 = C G2 results in α = 1/3. The output resistance seen at the w terminal, R w , is given by: α·g m1,2 (r ds1,2 r ds4,5 )(g m6 + g m7 ) (4) are essential for proper DC operation of the circuit while the input capacitors ensure the AC path for the input signals. The second stage of the unity gain DDA is created by class-AB stage M6, M7 and high resistance RMOS. This RMOS is also created by two cut-off transistors ML, and ensures the proper DC bias current of this output stage, while the capacitor C ensures the AC path for the signal; hence a simple class-AB stage is obtained. The compensation capacitor Cc ensure the stability of the DDA circuit.  Note, that both the low-frequency gain β, as well as the output resistance R w , are deteriorated by the input capacitive divider. However, thanks to the two-stage architecture of the internal OTA, used to create the MI-DDTA, and class AB operation, both parameters can achieve acceptable values.
The input capacitance seen from a single y terminal, for identical capacitances C G, which are much larger than parasitic capacitances of an MOS transistor, is: The gain bandwidth product (GBW) of the internal OTA, M 1 -M 7 , which is approximately equal to the 3-dB frequency of the gain β, depends on the transconductance of the input differential stage and the compensation capacitor C C : The transconductance stage is realized using the mirror topology M 8 -M 16 . The structure employs the self-cascode connections M 10c -M 16c in order to increase the output resistance and the gain of the TA. The current I SET can be used to regulate the transconductance of the TA, which in the weak inversion region, with unity-gain current mirrors, is given by: where n p is the subthreshold slope factor for a p-channel MOS transistor and U T is the thermal potential. The output resistance of the TA, i.e., the resistance seen from its o output, R o , can be approximated as: and its DC voltage gain A TA is given by: The parasitic poles associated with internal nodes of the TA are located well above the GBW product of the TA, consequently, the GBW product depends on the loading capacitance at the o terminal C LTA , and is given by: Figure 3a shows the block diagram of the shadow filter [10] that has been used to realize the first proposed shadow filter as shown in Figure 3b. The DDTA1, DDTA2 along with capacitors C1 and C2 realize the 2nd-order filter while DDTA3 along with resistor Sensors 2023, 23, 1526 5 of 18 R1 realize the amplifier (A). The inverting high-pass (HP) and band-pass (BP) responses are obtained at the VHP and VBP1 outputs, respectively, while VLP, VBP2, and VBS provide non-inverting low-pass (LP), BP, and band-stop (BS) responses. It should be noted that the input Vin possesses high impedance and outputs VHP, VBP2, and VBS possess low impedance while the output VLP needs the buffer circuit if low-impedance load is connected. The outputs VLP and VHP are summed and amplified. Using (1) and nodal analysis, the transfer functions of LP, HP, BP and BS filters can be expressed by:

Proposed Shadow Filters
where g m3 R 1 = A. The gain A can be regulated by g m3 , with constant R 1 , or by regulating R 1 with constant g m3 .  Figure 3a shows the block diagram of the shadow filter [10] that has been used to realize the first proposed shadow filter as shown in Figure 3b. The DDTA1, DDTA2 along with capacitors C1 and C2 realize the 2nd-order filter while DDTA3 along with resistor R1 realize the amplifier (A). The inverting high-pass (HP) and band-pass (BP) responses are obtained at the VHP and VBP1 outputs, respectively, while VLP, VBP2, and VBS provide non-inverting low-pass (LP), BP, and band-stop (BS) responses. It should be noted that the input Vin possesses high impedance and outputs VHP, VBP2, and VBS possess low impedance while the output VLP needs the buffer circuit if low-impedance load is connected. The outputs VLP and VHP are summed and amplified. Using (1) and nodal analysis, the transfer functions of LP, HP, BP and BS filters can be expressed by:   The natural frequency (ω o ) and the quality factor (Q) are given by:

Proposed Shadow Filters
From (15), the parameter ω o can be controlled by g m1 = g m2 and from (16), the parameter Q can be controlled by A (i.e., regulating g m3 with constant R 1 ) while maintaining g m1 = g m2 and C 1 = C 2 . Thus, the parameters ω o and Q can be controlled electronically.
From (11)-(14), increasing the parameter Q will decrease the passband of LP and HP filters by 1/(1 + A), whereas the gain of the BP filter will be constant.
It should be noted from (16) that the parameter Q can be increased if A > 1. When the amplifier inputs are swapped (i.e., connecting the y −1 -terminal to V LP and the y +1 -terminal to V HP ), the parameter Q will be proportional to (1 − A). In this case 0 < A < 1 is used.
The block diagram of the second proposed shadow filter is shown in Figure 4a. In this system two amplifiers A 1 and A 2 are used to amplify the output signals V BP and V LP , respectively. The proposed filter, employing four MI-DDTAs, two grounded capacitors, and one resistor is shown in Figure 4b. The DDTA 1 and DDTA 2 , along with capacitors C 1 and C 2 are used to realize the 2nd order filter while the resistor R 1 along with the DDTA 1 and DDTA 2 , respectively, are used to realize the amplifiers A 1 and A 2 . The non-inverting LP and BP responses are obtained at the V LP1 and V BP2 outputs, respectively, while V LP2 , V HP , and V BP1 provide inverting LP, HP, and BP responses. It should be noted that the input V in possesses high impedance while the outputs V LP2 , V HP , and V BP2 possess low impedance. The output V BP1 is amplified by A 1 using DDTA 3 and resistor R 1 and the output V LP1 is amplified by A 2 using DDTA 4 and the same resistor R 1 .
Using (1) and nodal analysis, the transfer function of the second proposed filter in Figure 4b can be expressed by: where g m3 R 1 = A 1 and g m4 R 1 = A 2 . From (17)- (19), they are valid for A 1 < 1 and A 2 < 1.
The natural frequency of the filter and its quality factor can be expressed as: From (20), the parameter ω o can be controlled by A 2 through adjusting g m4 or by adjusting g m1 = g m2 . However, adjusting the parameter ω o by A 2 affects the parameter Q. The parameter Q can be controlled by A 1 without affecting the parameter ω o through adjusting g m3 . From (17)- (20), adjusting the parameter ω o will change the passband of LP and BP filters whereas the passband of HP filter is constant.
The non-ideal first transfer function of the proposed shadow filter in Figure 3a can be expressed by: where Using (23), D(s) of the transfer functions can be rewritten as: where: where: The non-ideality of transconductance g mn can be neglected by satisfying the following condition: The non-ideal transfer function of the second proposed shadow filter in Figure 4b can be expressed by Using (23), D(s) of the transfer functions can be rewritten as where D = β −21 − g mn3 R 1 β +31 β +22 , and E = β +21 − g mn4 R 1 β −41 β +22 . The non-ideality of the transconductance g mn can be neglected by satisfying the following condition: Considering the parasitic parameters of DDTA by letting y-terminals possess very high impedance levels, which can be neglected, low parasitic resistance R w at w-terminal and parallel of parasitic capacitance C o and resistance R o at o-terminal. From Figures 3b and 4b, the parasitic parameters C o1 and R o1 of DDTA 1 are parallel with C 1 , parasitic parameters C o2 and R o2 of DDTA 2 are parallel with C 2 , and parasitic parameters C o3 and R o3 of DDTA 2 are parallel with R 1 . These parasitic parameters can be neglected by choosing appropriately values such as g mj 1/R oj , C j C oj , and R 1 R oj , where j = 1, 2, 3 of DDTA j .

Simulation Results
The proposed shadow filters were simulated using SPICE. The MI-DDTA as shown in Figure 1a was designed using a 0.18 µm CMOS technology and the transistor aspect ratios are shown in Table 1. The power supply was ±0.5 V.  60/1 Figure 5a shows the DC transfer characteristic V w against V y+1 and V y−1 of the MI-DDTA while (b) shows the AC transfer characteristic and −3 dB bandwidth of V w /V y+1 and V w /V y−1 with load capacitance of 10 pF, the −3 dB bandwidth is around 483.3 kHz and the low frequency gain is −0.016 dB. It is notable the capability of operation in a wide range of the input voltages. Note, that both, the differential, as well as common-mode range of the input differential amplifier M1-M2 is increased 1/α times, thanks to the input capacitive divider. the input differential amplifier M1-M2 is increased 1/α times, thanks to the input capacitive divider.  Figure 6 shows the small-signal transconductance of the transconductance stage, against the input voltage , for different I SET (Figure 6a), and against ISET (Figure 6b). It is worth noting that although the input range is sufficient for the proposed applications, this range, if needed, could be simply increased using a linearization technique like the source degeneration that results in increased dynamic rang of the system. The parasitic parameters of DDTA are Ry = 6.28 GΩ, = 540 Ω, = 11.9 MΩ, and = 33.67 fF.  Figure 6 shows the small-signal transconductance of the transconductance stage, against the input voltage V w, for different I SET (Figure 6a), and against I SET (Figure 6b). It is worth noting that although the input range is sufficient for the proposed applications, this range, if needed, could be simply increased using a linearization technique like the source degeneration that results in increased dynamic rang of the system. The parasitic parameters of DDTA are R y = 6.28 GΩ, R w = 540 Ω, R o = 11.9 MΩ, and C o = 33.67 fF. Figure 6 shows the small-signal transconductance of the transconductance stage, against the input voltage , for different I SET (Figure 6a), and against ISET (Figure 6b). It is worth noting that although the input range is sufficient for the proposed applications, this range, if needed, could be simply increased using a linearization technique like the source degeneration that results in increased dynamic rang of the system. The parasitic parameters of DDTA are Ry = 6.28 GΩ, = 540 Ω, = 11.9 MΩ, and = 33.67 fF.
(a) (b) The first proposed shadow filter was designed with C1 = C2 = 3.3 nF and R1 = 46.5 kΩ. Note that these passive values are sufficient to avoid the impact of parasitic effects. The transconductance 3 adjusted by the current ISET3 was used to control the amplifier A. The bias currents ISET1 and ISET2 were used to control 1 and 2 , respectively. The first simulation was performed with A = 0, by setting the bias current ISET3 = 0 and ISET1 = ISET2 = 1 μA ( = 21.5 μS). This setting resulted in natural frequency (fo) of 1.036 kHz and the quality factor (Q) of 1.
The magnitude responses of the LP, HP, BP, and BS filters are shown in Figure 7. Figure 8 shows the magnitude responses of the BP filter when the bias currents ISET1 = ISET2 The first proposed shadow filter was designed with C 1 = C 2 = 3.3 nF and R 1 = 46.5 kΩ. Note that these passive values are sufficient to avoid the impact of parasitic effects. The transconductance g m3 adjusted by the current I SET3 was used to control the amplifier A. The bias currents I SET1 and I SET2 were used to control g m1 and g m2 , respectively.
The first simulation was performed with A = 0, by setting the bias current I SET3 = 0 and I SET1 = I SET2 = 1 µA (g m = 21.5 µS). This setting resulted in natural frequency (f o ) of 1.036 kHz and the quality factor (Q) of 1.
The magnitude responses of the LP, HP, BP, and BS filters are shown in Figure 7. Figure 8 shows the magnitude responses of the BP filter when the bias currents I SET1 = I SET2 are varied. This result confirms that the natural frequency of the shadow filter can be electronically controlled. Figure 9 shows the magnitude frequency responses when the amplifier A is used to set the quality factor Q equal to 1.0, 2.0, 3.2, 3.9, and 4.6. Figure 9c shows that the quality factor of the BP filter can be controlled by the amplifier A (A > 1) with the passband gain equal to 0 dB while the passband gain of the LP, HP and BS filters in Figure 9a-c respectively, will decrease when the quality factor is increased. are varied. This result confirms that the natural frequency of the shadow filter can be elec tronically controlled. Figure 9 shows the magnitude frequency responses when the am plifier is used to set the quality factor Q equal to 1.0, 2.0, 3.2, 3.9, and 4.6. Figure 9 shows that the quality factor of the BP filter can be controlled by the amplifier ( >1 with the passband gain equal to 0 dB while the passband gain of the LP, HP and BS filter in Figure 9a-c respectively, will decrease when the quality factor is increased.     The second proposed shadow filter was designed with C1 = C2 = 3.3 nF and R1 = 46.5 kΩ. The bias currents ISET1 and ISET2 were used to adjust 1 and 2 , respectively. The 3 that was adjusted by ISET3 and 4 adjusted by ISET4 were used to control the amplifiers 1 and 2 , respectively. The first simulation was performed with 2 = 0 by setting the bias currents ISET4= 0, ISET1 = ISET2 = 1 μA ( = 21.5 μS), while the amplifier 1 was The second proposed shadow filter was designed with C 1 = C 2 = 3.3 nF and R 1 = 46.5 kΩ. The bias currents I SET1 and I SET2 were used to adjust g m1 and g m2 , respectively. The g m3 that was adjusted by I SET3 and g m4 adjusted by I SET4 were used to control the amplifiers A 1 and A 2 , respectively. The first simulation was performed with A 2 = 0 by setting the bias currents I SET4 = 0, I SET1 = I SET2 = 1 µA (g m = 21.5 µS), while the amplifier A 1 was used to control the parameter Q. The simulated magnitude responses of the LP, HP, and BP filters with Q = 1.1, 2.1, 3.6, 4.5, 10.0 are shown in Figure 10. This result confirmed that the parameter Q can be controlled by A 1 , without affecting the parameter ω o .  Figure 11 shows the simulated magnitude frequency responses of the LP, HP, and BP filters when the amplifier A 2 gain was regulated by g m4 and the amplifier A 1 was used to control the parameter Q = 1. This result confirmed that when the parameter ω o is varied by the amplifier A 2 , the passband gain of the LP and BP filter is changing while the passband gain of the HP filter is constant.
(c)  Figure 12a shows the simulated total harmonic distortion (THD) of the LP filter for f = 100 Hz. The amplifiers A1 and A2 were not active (ISET3 = ISET4 = 0 A). It can be noticed that THD was less than 1.2% for Vin < 250 mVpp and its transient response is shown in Figure  12b. Figure 12c shows the simulated third intermodulation distortion (IMD3) of the BP filter for a two-tone test, with two closely spaced tones of f1 = 0.9 kHz and f2 = 1.1 kHz. The IMD3 was less than 1.5% for the input amplitude up to 40 mVpp.  Figure 12a shows the simulated total harmonic distortion (THD) of the LP filter for f = 100 Hz. The amplifiers A 1 and A 2 were not active (I SET3 = I SET4 = 0 A). It can be noticed that THD was less than 1.2% for V in < 250 mV pp and its transient response is shown in Figure 12b. Figure 12c shows the simulated third intermodulation distortion (IMD 3 ) of the BP filter for a two-tone test, with two closely spaced tones of f 1 = 0.9 kHz and f 2 = 1.1 kHz. The IMD 3 was less than 1.5% for the input amplitude up to 40 mV pp .
The simulated magnitude responses of the LP, HP, and BP filters for process, voltage, and temperature (PVT) corners were investigated. Figure 13a-c show respectively the results of Monte Carlo (MC) analysis, were variations of the threshold voltages of MOS transistors by 10% (LOT tolerance), supply voltages by +/− 10% and temperature from −10 • C to 70 • C were assumed. As it can be noticed, the proposed filter is robust under the assumed PVT variations.
Finally, Table 2 provides a comparison of the proposed filters with previously published shadow filters in [22,23,26,29,30]. The proposed filters provide lower power consumption, as compared with [22,23], lower output impedance, as compared with [26,30] (except the output impedance of the LP filter in Figure 3b), larger number of low-impedance nodes, as compared with [29], and lower supply voltage, as compared with [23,26,29,30]. Figure 12a shows the simulated total harmonic distortion (THD) of the LP filter for f = 100 Hz. The amplifiers A1 and A2 were not active (ISET3 = ISET4 = 0 A). It can be noticed that THD was less than 1.2% for Vin < 250 mVpp and its transient response is shown in Figure  12b. Figure 12c shows the simulated third intermodulation distortion (IMD3) of the BP filter for a two-tone test, with two closely spaced tones of f1 = 0.9 kHz and f2 = 1.1 kHz. The IMD3 was less than 1.5% for the input amplitude up to 40 mVpp.  The simulated magnitude responses of the LP, HP, and BP filters for process, voltage, and temperature (PVT) corners were investigated. Figure 13a-c show respectively the results of Monte Carlo (MC) analysis, were variations of the threshold voltages of MOS transistors by 10% (LOT tolerance), supply voltages by +/− 10% and temperature from −10 °C to 70 °C were assumed. As it can be noticed, the proposed filter is robust under the assumed PVT variations.

Conclusions
This paper presents new voltage-mode shadow filters with single-input multipleoutput topology, using low-voltage low-power multiple-input differential difference transconductance amplifiers. The multiple-input DDTA can be easily realized using MIGD-MOST technique. The proposed filters offer high-input impedance and most of the output terminals offer low-impedance. The natural frequency and the quality factor of the filters can be electronically and independently controlled. The impact of the non-idealities of the DDTA on the performance of the proposed shadow filter is studied. The SPICE simulation results using 0.18 µm CMOS process from TSMC is given to validate the workability of the new circuits.
Funding: This work was supported by the University of Defence within the Organization Development Project VAROPS.

Conflicts of Interest:
The authors declare no conflict of interest.