A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor’s operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

As the applications of image sensor systems become more diverse, they require extreme characteristics that are difficult to achieve, such as 200-megapixel (MP) resolution, 140 dB dynamic range, ultra-compact multi-functionality, and invisible ray cameras [11][12][13]. Additionally, increased power consumption and heat generation are issues as more image functions are required for high-resolution cameras, such as fast auto-focus (<0.3 s) and slow-motion video with ultra-high frame rates (>240 frames/s) [13][14][15][16]. Moreover, there has been a recent demand for ultra-low-power characteristics for always-on-display capabilities in imaging systems.
There are many ways to read out the output of a pixel array, but in most cases, an array of thousands of analog-to-digital converters (ADCs) is integrated into a column-parallel architecture and used to digitize the pixel output. A single high-precision ADC must be implemented with a sub-micron pitch (<1 µm) to realize a high-resolution image sensing

Image Sensor Architecture
An imaging system has an inevitable trade-off between system performance and power consumption. To optimize this complex timing budget, the first step is to thoroughly understand how advanced image sensors are configured. Image sensors have evolved to implement pixel arrays and digitizer arrays on separate chips in stacks of three-dimensional (3-D) integrated circuits (ICs) using through-silicon via (TSV) or Cu-Cu connection techniques to achieve a small form factor [7], as shown in Figure 1. With the 3-D stacked architecture, an upper chip for the pixel array and a lower chip for the digitizer array can be separately implemented using optimal process technologies. Therefore, the rest of this section describes the structure of pixel and digitizer arrays for read-out timing analysis and system optimization. parallel architecture and used to digitize the pixel output. A single high-precision ADC must be implemented with a sub-micron pitch (<1 µm) to realize a high-resolution image sensing system with low-noise characteristics. Therefore, single-slope ADCs with relatively simple structures are commonly used as pixel digitizers. When utilizing a column-parallel ADC array to digitize the output of a pixel array, it is crucial to cancel out the dark noise of the pixels to obtain a high-quality image. To suppress the low-frequency noise of a pixel, most state-of-the-art image sensing systems use the digital correlated-double sampling (CDS) technique, which subtracts two digitized outputs of a pixel before and after it receives external light [17,18]. The digital CDS technique requires twice as many ADC operations, making the system timing budget insufficient for modern image systems with high resolution and a high frame rate. Furthermore, there are many other complex considerations for read-out timing, such as auto-zeroing (AZ), analog CDS, pixel reset, and the shutter.
This paper proposes a read-out timing optimization methodology utilizing an optimal reference offset for high-resolution, high-frame-rate image sensing systems. It includes considerations for the pixel array, the digital-to-analog converter (DAC) for the ramp reference of a single-slope ADC, and both analog and digital CDS techniques. With this timing optimization methodology, the amplifier bandwidth of the power-hungry comparator array can also be optimized, enabling energy-efficient image sensing. The rest of this article is organized as follows: Section 2 describes the architecture of modern image sensing systems. The proposed read-out timing optimization methodology is discussed in Section 3. Section 4 presents an implementation example with the proposed timing optimization. This paper concludes in Section 5.

Image Sensor Architecture
An imaging system has an inevitable trade-off between system performance and power consumption. To optimize this complex timing budget, the first step is to thoroughly understand how advanced image sensors are configured. Image sensors have evolved to implement pixel arrays and digitizer arrays on separate chips in stacks of threedimensional (3-D) integrated circuits (ICs) using through-silicon via (TSV) or Cu-Cu connection techniques to achieve a small form factor [7], as shown in Figure 1. With the 3-D stacked architecture, an upper chip for the pixel array and a lower chip for the digitizer array can be separately implemented using optimal process technologies. Therefore, the rest of this section describes the structure of pixel and digitizer arrays for read-out timing analysis and system optimization.    Figure 2 shows a simplified active pixel sensor (APS) structure with one pinned photodiode and four transistors (4-T) for a CMOS image sensor (CIS) [19,20]. A photodiode in a pixel acts as a light-to-electron converter. When incident light is applied, a photodiode in the pixel produces electrons proportional to the intensity of the light. The four MOS Sensors 2023, 23, 7048 3 of 14 transistors consist of a row selection transistor (SEL), a pixel reset gate (RG), a charge transfer gate (TG), and a source follower (SF) buffer. The output of the pixels is read out row-by-row with the rolling shutter method, so the SEL transistor is used to select the pixel row to digitize. After row selection, a reset sequence is required to eliminate residual electrons by turning on the RG before using the pixel as a sensor. Figure 2 shows a simplified active pixel sensor (APS) structure with one pinned pho todiode and four transistors (4-T) for a CMOS image sensor (CIS) [19,20]. A photodiode in a pixel acts as a light-to-electron converter. When incident light is applied, a photodiode in the pixel produces electrons proportional to the intensity of the light. The four MOS transistors consist of a row selection transistor (SEL), a pixel reset gate (RG), a charge transfer gate (TG), and a source follower (SF) buffer. The output of the pixels is read ou row-by-row with the rolling shutter method, so the SEL transistor is used to select the pixel row to digitize. After row selection, a reset sequence is required to eliminate residua electrons by turning on the RG before using the pixel as a sensor. Once the pixel reset is completed, electrons are generated by the photodiode receiv ing incident light and transferred to a floating diffusion (FD) node by turning on the TG An FD node has a capacitance on the order of fF or smaller, and electron-to-voltage con version with a conversion gain (CG) occurs during this photodiode-to-FD charge transfe process. Furthermore, the FD node voltage becomes the output voltage of the pixe through the in-pixel SF buffer, which is digitized by the following ADC. Figure 3 shows the timing diagram of the 4-T pixel with a digital CDS technique. To cancel out the pixel output variation, including pixel reset noise, a digital CDS technique is widely used. For a digital CDS function, two digitizations are performed, and the digita difference is equivalent to the perceived intensity of the light. Therefore, the dark signa is read before the TG is turned on, and the light signal is read after the TG is turned on.  Once the pixel reset is completed, electrons are generated by the photodiode receiving incident light and transferred to a floating diffusion (FD) node by turning on the TG. An FD node has a capacitance on the order of fF or smaller, and electron-to-voltage conversion with a conversion gain (CG) occurs during this photodiode-to-FD charge transfer process. Furthermore, the FD node voltage becomes the output voltage of the pixel through the in-pixel SF buffer, which is digitized by the following ADC. Figure 3 shows the timing diagram of the 4-T pixel with a digital CDS technique. To cancel out the pixel output variation, including pixel reset noise, a digital CDS technique is widely used. For a digital CDS function, two digitizations are performed, and the digital difference is equivalent to the perceived intensity of the light. Therefore, the dark signal is read before the TG is turned on, and the light signal is read after the TG is turned on.  Figure 2 shows a simplified active pixel sensor (APS) structure with one pinned photodiode and four transistors (4-T) for a CMOS image sensor (CIS) [19,20]. A photodiode in a pixel acts as a light-to-electron converter. When incident light is applied, a photodiode in the pixel produces electrons proportional to the intensity of the light. The four MOS transistors consist of a row selection transistor (SEL), a pixel reset gate (RG), a charge transfer gate (TG), and a source follower (SF) buffer. The output of the pixels is read out row-by-row with the rolling shutter method, so the SEL transistor is used to select the pixel row to digitize. After row selection, a reset sequence is required to eliminate residual electrons by turning on the RG before using the pixel as a sensor. Once the pixel reset is completed, electrons are generated by the photodiode receiving incident light and transferred to a floating diffusion (FD) node by turning on the TG. An FD node has a capacitance on the order of fF or smaller, and electron-to-voltage conversion with a conversion gain (CG) occurs during this photodiode-to-FD charge transfer process. Furthermore, the FD node voltage becomes the output voltage of the pixel through the in-pixel SF buffer, which is digitized by the following ADC. Figure 3 shows the timing diagram of the 4-T pixel with a digital CDS technique. To cancel out the pixel output variation, including pixel reset noise, a digital CDS technique is widely used. For a digital CDS function, two digitizations are performed, and the digital difference is equivalent to the perceived intensity of the light. Therefore, the dark signal is read before the TG is turned on, and the light signal is read after the TG is turned on.

Read-Out IC Structure
The SF elements in the pixel array on the top chip require a current load (I PL ) to function properly, which is usually implemented on the bottom chip. As shown in Figure 4, once the pixel reset (period A) is complete, the auto-zero (AZ) operation (period B) of the ADC can be started. During the AZ phase, DC offset and flicker noise are stored for the analog CDS operation, and a self-bias network is operated to determine the operating bias of the amplifier. When the AZ operation is completed, the digitizer reads out the data before and after receiving the incident light and then finds the difference to obtain the result of the digital CDS (periods C to I). In the single-slope counting sections (periods E and I), a comparator compares the pixel output with the reference voltage, which is the ramp signal implemented based on the DAC. Additionally, the reference offset (OFF RAMP ) can be added before the start of the ramping to prevent missing the dark signal, and the added offset is naturally canceled out with the digital CDS technique.

Read-Out IC Structure
The SF elements in the pixel array on the top chip require a current load (IPL) to function properly, which is usually implemented on the bottom chip. As shown in Figure 4, once the pixel reset (period A) is complete, the auto-zero (AZ) operation (period B) of the ADC can be started. During the AZ phase, DC offset and flicker noise are stored for the analog CDS operation, and a self-bias network is operated to determine the operating bias of the amplifier. When the AZ operation is completed, the digitizer reads out the data before and after receiving the incident light and then finds the difference to obtain the result of the digital CDS (periods C to I). In the single-slope counting sections (periods E and I), a comparator compares the pixel output with the reference voltage, which is the ramp signal implemented based on the DAC. Additionally, the reference offset (OFFRAMP) can be added before the start of the ramping to prevent missing the dark signal, and the added offset is naturally canceled out with the digital CDS technique.

Read-Out Timing Optimization Methodology
A simplified block diagram of an image sensor is shown in Figure 5. To achieve a column-parallel ADC architecture, a comparator must be composed of a simple structure, which is a 5-transistor first amplifier and a common-source second amplifier. The twostage amplifier with an open-loop topology is well-used in an ADC array structure [7,8,18,21]. The read-out sequence of the image sensor from period A to I (one-row readout time) is repeated until the entire pixel array has been read row by row. Therefore, the one-row read-out time can be determined based on the pixel resolution and the target frame rate of the image sensing system. For example, if a 100 MP image sensor (10,000 × 10,000) is to be digitized at a target of 10 fps, the one-row read-out time would be 10 µs in a single ADC per single pixel column (1 ADC/col) structure. The one-row read-out time should be carefully distributed from period A to period I without any redundant or bottleneck periods. In this paper, an advanced read-out timing optimization methodology is proposed with an optimum reference offset.

Read-Out Timing Optimization Methodology
A simplified block diagram of an image sensor is shown in Figure 5. To achieve a column-parallel ADC architecture, a comparator must be composed of a simple structure, which is a 5-transistor first amplifier and a common-source second amplifier. The two-stage amplifier with an open-loop topology is well-used in an ADC array structure [7,8,18,21]. The read-out sequence of the image sensor from period A to I (one-row read-out time) is repeated until the entire pixel array has been read row by row. Therefore, the one-row read-out time can be determined based on the pixel resolution and the target frame rate of the image sensing system. For example, if a 100 MP image sensor (10,000 × 10,000) is to be digitized at a target of 10 fps, the one-row read-out time would be 10 µs in a single ADC per single pixel column (1 ADC/col) structure. The one-row read-out time should be carefully distributed from period A to period I without any redundant or bottleneck periods. In this paper, an advanced read-out timing optimization methodology is proposed with an optimum reference offset.

Period A: Reset
At the beginning of every horizontal read-out time, a pixel row for digitization should be selected using the SEL transistor. Additionally, a reset operation at the FD node should be completed to empty the FD capacitor C FD . The kT/C noise generated during the reset period is suppressed by the digital CDS technique. This reset and selection of the pixel

Period A: Reset
At the beginning of every horizontal read-out time, a pixel row for digitization should be selected using the SEL transistor. Additionally, a reset operation at the FD node should be completed to empty the FD capacitor CFD. The kT/C noise generated during the reset period is suppressed by the digital CDS technique. This reset and selection of the pixel are relatively independent of the image resolution and can be defined as an absolute time interval according to a pixel structure.

Periods B and C: AZ
Before starting the AZ operation, the RG is turned off, which causes a voltage fluctuation (ΔRGOFF) that is transferred to the bottom digitizer chip through the 3-D chip-to-chip connection. During the AZ period, therefore, the effect of the voltage fluctuation from the top pixel chip should be sufficiently settled, as should the operation of the amplifier to determine the DC bias and store low-frequency noise. In this period, the amplifier of the single-slope ADC is in a very fast unity-gain configuration and has a very small time constant. Therefore, the settling bottleneck induced by the ΔRGOFF is the output of the pixel, which is the input of the ADC. With the negligible time constant of the ADC, the resistance for the RC time constant is determined by the transconductance of the pixel source follower, the on-resistance of the pixel selection transistor, and the metal line resistance of the pixel output. The time constant and slew rate of the SF can be obtained as follows: where gm,SF is the transconductance of the SF, RSEL is the on-resistance of the SEL, and RLINE is the line resistance from the pixel to the ADC, including the chip-to-chip connection line.
In the worst-case settling situation, slewing is caused by the condition SF·SRSF < ΔRGOFF, and the required settling and slewing voltage can be given by: Then, the required time for the slewing and settling can be derived as follows: where ETARG,B is the target achieved settling error in period B, and the timing budget for the period can be obtained as TSLEW,B + TSETTLE,B.

Periods B and C: AZ
Before starting the AZ operation, the RG is turned off, which causes a voltage fluctuation (∆RG OFF ) that is transferred to the bottom digitizer chip through the 3-D chip-to-chip connection. During the AZ period, therefore, the effect of the voltage fluctuation from the top pixel chip should be sufficiently settled, as should the operation of the amplifier to determine the DC bias and store low-frequency noise. In this period, the amplifier of the single-slope ADC is in a very fast unity-gain configuration and has a very small time constant. Therefore, the settling bottleneck induced by the ∆RG OFF is the output of the pixel, which is the input of the ADC. With the negligible time constant of the ADC, the resistance for the RC time constant is determined by the transconductance of the pixel source follower, the on-resistance of the pixel selection transistor, and the metal line resistance of the pixel output. The time constant and slew rate of the SF can be obtained as follows: where g m,SF is the transconductance of the SF, R SEL is the on-resistance of the SEL, and R LINE is the line resistance from the pixel to the ADC, including the chip-to-chip connection line.
In the worst-case settling situation, slewing is caused by the condition τ SF ·SR SF < ∆RG OFF , and the required settling and slewing voltage can be given by: Then, the required time for the slewing and settling can be derived as follows: where E TARG,B is the target achieved settling error in period B, and the timing budget for the period can be obtained as T SLEW,B + T SETTLE,B . For period C, the voltage fluctuation induced by the turn-off signal of the AZ is well suppressed by the pseudo-differential amplifier topology of the ADC. Therefore, the timing budget for this period can be defined as a small absolute value for non-overlapping clock timing.

Period D: Reference Offset and Its Counting
In the ideal case, the ADC decision time of the dark signal is the end of period D. However, the pixel output has a wide output variation, so it can be missed without the ramp offset (OFF RAMP ). Therefore, in general, the dark ramping period should be long enough to include the output variation before digital CDS. However, if the ramp settling at the output of the amplifier is not sufficient until the time of the ADC decision, this settling error cannot be suppressed by the digital CDS technique. To achieve the high color linearity (CL) characteristic of an imager, the linearity relative to the ideal dark signal should be constant with respect to the light intensity. The color linearity (CL) error can be expressed as follows: where O X is the digitized output with the external incident light equivalent to the X LSB input, O 0 is the output with no input, and O REF is the output with the high code LSB input for the ratio calculation. In addition, O X,IDEAL , O 0,IDEAL , and O REF,IDEAL represent the ideal output values without any settling error. In high-resolution image sensors, the remaining settling error can thus degrade the CL error.
In this paper, a read-out timing optimization methodology is proposed to find the optimal reference DAC offset with the optimal settling error. There are two factors that contribute to settling errors in this period. The first factor is the voltage fluctuation due to OFF RAMP . With the reference offset and the target achieved settling error in period D (E TARG,D ), the timing budget for this period is given by: where τ OTA1 is the time constant of the first amplifier, which is directly related to the bandwidth of the amplifier and can be approximated by the time constant of the singleslope ADC (τ ADC ). The second factor that affects settling error in this period is ramp settling. Figure 6 shows ideal and realistic reference ramp waveforms, where t CCLK is the unit-time step of the counter clock frequency. The reference ramp signal with a finite amplifier bandwidth of the following ADC causes a time-variable delay at the output of the ADC. At the start of the ramp, this time-variable delay is zero, which is the minimum delay. After sufficient settling time, the ramp delay gradually increases to the time constant of the amplifier, which is the maximum delay. In a single-slope ADC, the decision time is directly digitized by a following counter; thus, this ramp settling error must be well suppressed before the ADC decision. For an ideal ramp, the time to count OFFRAMP with an input signal of X LSB is given by: For a realistic ramp, however, the time taken for a decision can be determined by For an ideal ramp, the time to count OFF RAMP with an input signal of X LSB is given by: For a realistic ramp, however, the time taken for a decision can be determined by finding the zero-crossing solution of the following equation: Using (9) and (10), the CL in (7) can be estimated with an X LSB input and a reference input. Figure 7 shows the CL error estimation versus the settling time budget for OFF RAMP with an input of 10 LSBs and a reference of 256 LSBs. As an example, to ensure linearity characteristics above 99%, the minimum time for period D can be chosen as a relative value of 3τ OTA1 . As shown in Figure 7, with a sufficient settling time of more than 4τ OTA1 , the CL error becomes relatively independent of the ramp offset. For an ideal ramp, the time to count OFFRAMP with an input signal of X LSB is gi by: · .
For a realistic ramp, however, the time taken for a decision can be determined finding the zero-crossing solution of the following equation: Using (9) and (10), the CL in (7) can be estimated with an X LSB input and a refere input. Figure 7 shows the CL error estimation versus the settling time budget for OFFR with an input of 10 LSBs and a reference of 256 LSBs. As an example, to ensure linea characteristics above 99%, the minimum time for period D′ can be chosen as a rela value of 3τOTA1. As shown in Figure 7, with a sufficient settling time of more than 4τO the CL error becomes relatively independent of the ramp offset.

Period E: Dark Counting
Although the ideal decision timing of the dark signal is at the end of period D, ramping period should be longer to include the peak-to-peak variation of the pixel outp

Period E: Dark Counting
Although the ideal decision timing of the dark signal is at the end of period D, the ramping period should be longer to include the peak-to-peak variation of the pixel output. If the ramping period is too short to include all pixel output, the fixed-pattern noise (FPN) of the output image is severely degraded. Therefore, it is important to budget the ramping period to the appropriate time, which can be iteratively determined between Monte-Carlo simulation of the ADC and the timing optimization method presented in this paper. After the iterations, the timing budget for period E can be defined.

Periods F, G, and H: TG
After the reset counting, the TG of the pixel must be turned on to transfer the electrons accumulated at the PN junction of the photodiode to the FD node for light counting. After reset counting, a small timing margin before turning on TG is required to avoid clock overlapping, so allocating a small absolute time is enough for period F.
For period G, the on-time of the TG should be long enough to allow sufficient photodiode-to-FD charge transfer. By comprehensively considering the structure and process of the pixel array, including back deep trench isolation (BDTI)/front deep trench isolation (FDTI), and front-side illumination (FSI)/back-side illumination (BSI), the timing budget for the on-time of the TG can be defined, which is independent of the ADC.
When the TG is turned off, a voltage fluctuation (∆TG OFF ), which is similar to ∆RG OFF in period B, is induced and transferred to the digitizer chip. Since the ramping time in period H is the same as that in period D , which is used for OFF RAMP ramping, the settling time for ∆TG OFF can be optimized with period H*. At the pixel output, the required settling and slewing voltages can be derived as follows: The minimum time budgets for the slewing and settling voltages are then given by: where E TARG,H is the target achieved settling error in period H, and the minimum time budget for period H* can be calculated by: where T D is a chosen time budget for period D , considering the result shown in Figure 7.

Period I: Light Counting
For the single-slope counting of the light digitization, the ADC decision timing is dependent on the light intensity. If there is no light coming into the pixel chip, the ADC decision occurs with the same timing as the dark digitization. If there is detectable light, stronger light intensity leads to a later ADC decision. Therefore, the light counting period should sufficiently cover the pixel output range, and then the count of this period must be longer than 2 N LSB with an N-bit single-slope ADC. The timing budget for this period is then given by: (2 N + COUNT MARGIN )/t CCLK (16) where COUNT MARGIN is a single-slope counting margin that considers the system offset, mismatch, noise, and PVT variation.

Timing Optimization
Based on the timing analysis of each read-out period, an optimal timing diagram for a high-resolution image sensor can be derived. By utilizing the proposed timing optimization methodology with an optimal offset of a ramp reference, an optimized time for each period can be assigned, and an optimal ramp offset and amplifier bandwidth can also be achieved.
For example, consider a 12,000 × 9000 pixel array that needs to be digitized with a 12-bit ADC array at 15 fps. The ADC array needs to process the pixel output of 9000 rows 15 times in 1 s, and a one-row read-out time is then 7.4 µs. With a specific pixel structure, system architecture design, and circuit simulation results, design parameters for a highresolution image sensor can be achieved, as shown in Table 1. With the design parameters, the settling time for ramp offset and the time constant of the amplifier versus ramp offset can be calculated, as shown in Figure 8. A large ramp offset is required to ensure a sufficient ramp offset settling time, which in turn requires a small time constant, which increases power consumption.   Through the iterative calculation based on the other parameters in Table 1 and the equations in Section 3, optimized time budget results can be achieved, as shown in Table 2. With the proposed timing optimization methodology, an optimal reference offset of 440 LSB was achieved. Considering the effect of the PVT variation, a reference offset of 480 LSB can be chosen. Furthermore, an optimal amplifier time constant of 121.6 ns is also derived, which is equivalent to a bandwidth of 1.31 MHz. Without optimizing the reference offset as proposed in this paper, the power efficiency of an image sensing system becomes very poor. For example, an amplifier bandwidth of 2.49 MHz would be required to maintain the same CL error with an unoptimized reference offset of 256 LSB.
With this approach, the power consumption of the amplifier array, which is one of the most power-hungry circuits, can be minimized. This can increase the system's energy efficiency or frame rate by minimizing one-row read-out timing.

Implementation and Experimental Results
A power-efficient digitizer array for verifying the proposed time budgeting method is implemented in a 28-nanometer process with a chip size of 47 mm 2 . The prototype digitizer is designed with an optimal reference ramp offset and a 10-bit column-parallel single-slope ADC array. Figure 9 shows an annotated microphotograph of the digitizer chip, which can be stacked with a pixel chip. The width of the implemented ADC is only 1.005 µm, with a height of 1800 µm. The heights of the comparator array and counter array of the ADC are 1400 µm and 400 µm, respectively. The comparator array and counter array are operated with a supply voltage of 2.8 V and 1 V, respectively. The peripheral blocks include a DAC for reference ramp signal generation, a voltage doubler for the pixel chip, and reference current generation.  Figure 10 shows the histogram of the digitized reset data before applying the digital CDS technique. It shows an output distribution (1-σ) of 20 LSB, which corresponds to a 6.6-σ reliability of 120 LSB. Since the reference DAC offset is included in the digitized data without the digital CDS technique, the x-axis origin of the figure was moved to zero for clarity. After applying the digital CDS technique, the digitized output histogram with a 1σ distribution of 5 LSB is achieved, as shown in Figure 11. Furthermore, thanks to the digital CDS technique, the DC offset of the histogram is also suppressed, from 0.64 LSB to 0.003 LSB.  Figure 10 shows the histogram of the digitized reset data before applying the digital CDS technique. It shows an output distribution (1-σ) of 20 LSB, which corresponds to a 6.6-σ reliability of 120 LSB. Since the reference DAC offset is included in the digitized data without the digital CDS technique, the x-axis origin of the figure was moved to zero for clarity. After applying the digital CDS technique, the digitized output histogram with a 1-σ distribution of 5 LSB is achieved, as shown in Figure 11. Furthermore, thanks to the digital CDS technique, the DC offset of the histogram is also suppressed, from 0.64 LSB to 0.003 LSB. 6.6-σ reliability of 120 LSB. Since the reference DAC offset is included in the digitized da without the digital CDS technique, the x-axis origin of the figure was moved to zero f clarity. After applying the digital CDS technique, the digitized output histogram with a σ distribution of 5 LSB is achieved, as shown in Figure 11. Furthermore, thanks to t digital CDS technique, the DC offset of the histogram is also suppressed, from 0.64 LSB 0.003 LSB.  The digitizer array chip is connected to a 0.7 µm 108 MP pixel array chip in a 3 stacked configuration for its performance verification [7]. Figure 12 shows the measur random noise (RN) and column FPN. The sample image captured by the 3-D stacked C at 20 lux and 10 fps is shown in Figure 13. With a one-row read-out time of 6.9 µs, amplifier bandwidth of 1.1 MHz, and a reference DAC offset of 512 LSB, an RN of 1.4 rms and a column FPN of 66 ppm are measured at an analog gain of 16. The 108 M imager consumes only 551 mW and also achieves a remarkable figure-of-merit (FoM) 0.71 e -·nJ based on the common FoM equation for image sensor applications [10]. In Tab 3, the performance of the 108 MP imager is summarized and compared with previous published works [5,11,12,14,16]. Compared to other image sensors, this work shows a markable FoM with a low RN. The digitizer array chip is connected to a 0.7 µm 108 MP pixel array chip in a 3-D stacked configuration for its performance verification [7]. Figure 12 shows the measured random noise (RN) and column FPN. The sample image captured by the 3-D stacked CIS at 20 lux and 10 fps is shown in Figure 13. With a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference DAC offset of 512 LSB, an RN of 1.4 erms and a column FPN of 66 ppm are measured at an analog gain of 16. The 108 MP imager consumes only 551 mW and also achieves a remarkable figure-of-merit (FoM) of 0.71 e -·nJ based on the common FoM equation for image sensor applications [10]. In Table 3, the performance of the 108 MP imager is summarized and compared with previously published works [5,11,12,14,16]. Compared to other image sensors, this work shows a remarkable FoM with a low RN. amplifier bandwidth of 1.1 MHz, and a reference DAC offset of 512 LSB, an RN of 1.4 e rms and a column FPN of 66 ppm are measured at an analog gain of 16. The 108 MP imager consumes only 551 mW and also achieves a remarkable figure-of-merit (FoM) of 0.71 e -·nJ based on the common FoM equation for image sensor applications [10]. In Table  3, the performance of the 108 MP imager is summarized and compared with previously published works [5,11,12,14,16]. Compared to other image sensors, this work shows a remarkable FoM with a low RN.

Conclusions
This work presents a timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope ADCs. By optimizing the ramp reference offset and amplifier bandwidth, the power consumption in the amplifier array is reduced without compromising performance. The methodology has been successfully applied to a 108 MP 3-D stacked CMOS image sensor, resulting in a random noise of 1.4 erms, column fixed-pattern noise of 66 ppm, and FoM of 0.71 e -·nJ. The importance of this work lies in its ability to enhance energy efficiency in high-resolution image sensors,

Conclusions
This work presents a timing optimization methodology for power-efficient highresolution image sensors with column-parallel single-slope ADCs. By optimizing the ramp reference offset and amplifier bandwidth, the power consumption in the amplifier array is reduced without compromising performance. The methodology has been successfully applied to a 108 MP 3-D stacked CMOS image sensor, resulting in a random noise of 1.4 erms, column fixed-pattern noise of 66 ppm, and FoM of 0.71 e -·nJ. The importance of this work lies in its ability to enhance energy efficiency in high-resolution image sensors, which allows for higher frame rates and improved overall system performance. The proposed design methodology is versatile and could be adapted for a wide range of imaging applications that demand optimized performance and reduced power consumption.