A Ku-Band GaN-on-Si MMIC Power Amplifier with an Asymmetrical Output Combiner

In this paper, a microwave monolithic integrated circuit (MMIC) high-power amplifier (HPA) for Ku-band active radar applications based on gallium nitride on silicon (GaN-on-Si) is presented. The design is based on a three-stage architecture and was implemented using the D01GH technology provided by OMMIC foundry. Details on the architecture definition and design process to maximize delivered power are provided along with stability and thermal analyses. To optimize the amplifier performance, an asymmetry was included at the output combiner. Experimental results show that the HPA achieves a 39.5 dBm pulsed-mode output power, a peak linear gain of 23 dB, a drain efficiency of 27%, and good input/output matching in the 16–19 GHz frequency range. The chip area is 5 × 3.5 mm2 and for the measurements was mounted on a custom-made module. These results demonstrate that GaN-on-Si-based Solid-State Power Amplifiers (SSPAs) can be used for the implementation of Ku-band active radars.


Introduction
Active radars worldwide operate in various frequency bands, including the X, C, L, S, and Ku bands, which can be combined for certain applications. The L and S bands are commonly used in dense environments such as forests or glaciers due to their penetration capabilities. The X and C bands, on the other hand, are employed for high-resolution applications, making them valuable for tactical purposes. Additionally, the Ku band is particularly advantageous for studying large surfaces and achieving higher resolutions, making it popular in military applications [1].
The Ku band offers benefits such as enabling the use of small antennas in lightweight applications like Synthetic Aperture Radar (SAR), Surface Movement Radar (SMR), Ground Surveillance Radar (GSR), and Altimeter Radar. These radar systems often require peak power ranging from a few watts to tens of watts, utilizing short pulses to achieve high accuracy, high update rates, and high-resolution target detection [2][3][4][5][6][7].
To meet the demands of these applications, the development of high-power amplifiers (HPAs) is essential. HPAs must generate high RF power at the operating frequency while maintaining enhanced efficiency. While efficiency and output power are important, ensuring high reliability and controlled aging for long-term operation is equally crucial. This necessitates optimizing circuit designs to operate at reduced levels of electrical and thermal stress. The primary source of stress for high-power active devices is self-heating, which calls for lowering the maximum operating temperature of these devices compared to the technology's maximum rating.
Achieving high output power in an HPA often requires a large number of transistors in parallel in the final stage [8][9][10][11][12][13]. To enhance reliability and extend the HPA's lifespan, it is necessary to ensure that the transistors operate below the maximum power density allowed by the technology. Consequently, increasing the number of transistors in parallel in the final stage becomes necessary to ensure they operate well below the technology's maximum power density. However, designing the output combiner becomes more challenging as the number of transistors increases.
In this paper, we propose the use of an asymmetrical output combiner for designing a 16-19 GHz GaN high-power amplifier (HPA) specifically for active radar applications. Thanks to this asymmetry, all the output transistors are matched closer to their optimum load impedance, resulting in all of them providing nearly the same performance.
The organization of this paper is as follows: Section 2 discusses the general characteristics of the employed technology, the OMMIC's D01GH GaN-on-Si process. Section 3 focuses on the design of the HPA, while Section 4 presents the measurement results. Finally, Section 5 provides the conclusions derived from this study.

Technology Description
The D01GH process is based on an AlN-GaN-AlGaN Double Heterostructure Field-Effect Transistor (DHFET) active layer, which can be fabricated on either a high-resistivity silicon substrate (GaN-on-Si) or a silicon carbide substrate (GaN-on-SiC). GaN-on-SiC devices generally offer higher output power (P out ), power density, and power-added efficiency (PAE) than GaN-on-Si devices. Furthermore, the SiC substrate exhibits lower losses and better thermal conductivity compared to the Si substrate. However, the SiC substrate is more expensive to manufacture and is not compatible with other Si-based technologies. In this design, the silicon substrate was chosen due to its availability.
The transistors of this technology feature a mushroom-shaped 100 nm gate to enhance performance in terms of noise and frequency. The kit includes non-alloyed ohmic contacts for ultra-low resistance and transistor-based diodes for mixing, level shifting, or implementing varactors. Two different ways to implement resistors and Metal-Insulator-Metal (MIM) capacitors can be utilized, depending on which layers are involved.
The process is intended to be used for microwave and millimeter-wave applications and includes air bridges, thick interconnect metal, and high resistivity via holes. This process utilises in situ passivation to minimize lag effects [13].
The main electrical characteristics of this process include a cut-off frequency of 105 GHz and an RF power density of 3.3 W/mm (with a peak value of 5.7 W/mm) [13]. The breakdown voltage is 40 V, and the quiescent V DD is 12 V.

HPA Design
The first step in designing an HPA is to define its architecture, including the number of stages and the number of transistors in each stage. The Load/Source pull method [14] based on the process design kit (PDK) devices was used to optimize the size of the transistors for the desired performance. A specific transistor with eight fingers and a finger width of 125 µm was chosen for its good saturated power and linear gain: approximately 32 dBm and 10 dB, respectively. To achieve a gain of approximately 25 dB, the number of stages was set to three, taking into account the insertion losses introduced by the interstages that connect the different amplification stages. In order to ensure a long lifespan for the circuit while achieving a theoretical output power of 41 dBm, we employed eight transistors in the last stage with a power density of 1.58 W/mm. This power density is significantly lower than the maximum allowed by the technology (3.3 W/mm). By operating under these conditions, the transistors remain well below the maximum temperature of 200 • C specified by the technology for a backside temperature of 85 • C. Finally, to ensure proper signal distribution to the last stage, the second and first stages were composed of four and two transistors, respectively. Figure 1 shows the overall architecture of the HPA, while Figures 2 and 3 display the schematic and a die photograph of the manufactured circuit, respectively. The design occupies an area of 5 × 3.5 mm 2 . In the following subsections, a brief description of the HPA design is presented.

Matching Networks Design
As shown in Figure 2, the output matching network is an interface between the eight transistors of the third stage (power stage) and the ground-signal-ground (GSG) output port. Its main purpose is to provide the optimum load to the transistors while minimizing the losses. The design of this network is the most critical part when designing an HPA, since the output power level directly depends on it. The output matching network was designed to be symmetrical to the output of the circuit and originally consisted of a double-L matching network made up of two T-lines and two capacitors. Thanks to the symmetry of the network, only three capacitors were needed for the entire matching network, instead of the sixteen originally needed (two for each transistor).  As shown in Figure 3, a slight asymmetry was included in the layout of the output matching network by making the output T-lines slightly different in length. This was because EM simulations revealed that if the output network is completely symmetrical, the coupling between the lines results in different loadings for each of the eight output transistors. This means that not all transistors in the output stage contribute to the output power in the same way. To illustrate this, Figure 4 displays the optimum impedance for maximum power delivery (Zopt) and the actual impedances that the top four transistors see in the 17.3 GHz to 18.4 GHz frequency range after analyzing the EM simulations of the output matching network (Z 1−4 ) for the cases when the output network is completely symmetrical (Figure 4a) and when the output network has the asymmetry shown in Figure 3 (Figure 4b). It can be observed that with a symmetric output matching network, Z 2 and Z 3 are close to Zopt, while Z 4 and Z 1 deviate significantly (see Figure 4a). However, after including the asymmetry, impedances Z 1−4 are uniformly distributed around Zopt (see Figure 4b). This significantly improves the large-signal response, as shown in Figure 5, where the simulated P sat at 5 dB compression and the PAE of the design without asymmetry (Figure 5a,b) and with asymmetry (Figure 5c,d) are displayed. The simulations demonstrate that the inclusion of asymmetry results in a 1 dBm improvement in Pout and a 6% improvement in PAE.
The procedure followed to develop the rest of the matching networks was the same as explained above. The main difference is that the objective when designing output matching networks is to minimize insertion loss, while in the case of inter-stage matching networks the goal is mainly to minimize mismatch loss, and in the input matching network it is to improve input return loss. To achieve these objectives, EM simulations and optimization were used.

Stability Analysis
When designing an HPA, the appearance of oscillations related to circuit instabilities must be carefully avoided. Different types of oscillations can occur in microwave power amplifiers: low frequency or bias, even mode or small signal, odd mode and parametric [15].
In the drain biasing networks, series RC filters in parallel with de-coupling capacitors were included to remove low-frequency stability issues. The capacitors were sized to reduce oscillations at low frequencies, in this case around 2 GHz.
The inherent stability of a transistor itself is known as even-mode stability. Even-mode oscillations occur when the load or source impedances connected at the transistor input or output provide a reflection coefficient magnitude greater than one. This is usually avoided by adding a stabilization circuit. In this case, a parallel RC circuit at the input of the amplifier was used to remove even-mode instabilities.
Odd-mode oscillations are due to the instabilities that could appear in a transistor due to leakage caused by its connection in parallel with another transistor [14]. To prevent such oscillations, stabilization buses made up of small resistors, called isolation resistors, connected between the input and the output of the transistors were included.
Finally, parametric oscillations occur when the power amplifier enters the nonlinear regime. In this situation, the transistors' internal nonlinear elements vary, generating unstable feedback loops. The conventional method to detect parametric oscillations is to calculate the zero-poles of all closed-loop transfer functions in the nonlinear regime. The amplifier is unstable if there is a pole with a positive real part located in the right half plane (RHP) of one transfer function [16]. Parametric oscillations are associated with an increase in gain when the power amplifier enters the nonlinear regime. The most common way to reduce these oscillations is to place a resistor in series with the gate of one transistor to reduce the gain. In our case, the input parallel RC circuit used to remove even-mode instabilities also removed parametric oscillations.

Thermal Analysis
GaN technology can achieve high power densities, which can lead to increased selfheating and higher operating channel temperatures in the transistor. This is especially problematic in GaN technologies that use a silicon substrate, due to its poor thermal conductivity. The thermal resistance of GaN-on-Si technology is about twice that of GaNon-SiC [17], which means that the maximum power that can be dissipated is much lower and, therefore, the achievable power density will also be lower.
To ensure that the circuit will stay below the maximum junction temperature (Tj) set by the foundry to prevent malfunctions (200 • C), a thermal analysis was performed using the ADS Electrothermal Simulator assuming a backside temperature of 85 • C. As can be observed in Figure 6, the maximum value of the temperature is 156.6 • C, which is reached at the gates of the transistors of the last stage.  Figure 7 shows the measurement module without the lid. This includes the HPA and the external bias networks. The cavity resonance coupled with the HPA can draw a huge quiescent current, which can cause the breakdown of the device. Also, the resonance can affect the gain, stability, P out , etc. [18]. To mitigate these effects, an RF absorber with a height of 0.8 mm was included on the lid of the module. The signals were inserted and extracted using waveguides. A Peltier thermoelectric module was used to refrigerate the circuit. The S-parameter measurements were carried out in continuous-wave mode and the results are shown in Figure 8. For V DS = 10 V, the measurements show that the S 21 is above 20 dB from 16 GHz to 19 GHz, reaching a peak gain of 23 dB at 17.6 GHz. Secondly, the S 11 parameter is below -10 dB from 16.3 GHz to 18.8 GHz. Regarding the output matching (S 22 ), its value is below -10 dB from 16.4 GHz to 19.3 GHz. The power measurements were performed in pulsed mode using 100 µs pulses and a duty cycle of 1%. Figure 9 shows the saturated output power for the designed HPA at 17.3 GHz. This circuit provides 39.5 dBm of output power, which is equivalent to 8.9 W. These results were achieved under a total current consumption of 3.3 A and 11 V of drain voltage. The drain efficiency was measured. Since the gain of the circuit is large, the PAE can be considered similar to the drain efficiency. The resulting drain efficiency is 27%, with P out = 8.91 W, V DC = 11 V, and I DC = 3.3 A. An amplifier module based on this MMIC would meet both short-pulse (20-100 ns) and long-pulse (1-100 µs) applications with an output power between 8 and 100 W if various MMICs were combined.   Table 1 shows a comparison of state-of-the-art composite GaN power amplifiers using OMMIC's 100 nm GaN-on-Si technology. The designs in [10,11] outperform ours in terms of PAE and output power, but they achieve this by driving their transistors to the maximum power density allowed by the technology. In contrast, our design prioritizes reliability and longevity by sacrificing some power to keep the transistors operating well below 200 • C (assuming a backside temperature of 85 • C). The thermal simulator indicates that our maximum temperature is only 156.6 • C, which provides a much longer lifespan for our design. In terms of area, our design occupies a larger footprint due to its lower operating frequency. Although [10] operates in a similar frequency range, it uses a smaller area because it has only two stages and consequently achieves a lower gain.

Conclusions
In this paper, a composite MMIC HPA for Ku-band active radar applications based on OMMIC's D01GH GaN-on-Si process is presented. To ensure that all transistors in the output stage contribute to the output power in the same way, an asymmetry was added to the output combiner. The HPA achieves a peak gain of 23 dB, and good input/output matching in the 16-19 GHz frequency range, with a pulsed-mode output power of 39.5 dBm and a drain efficiency of 27% for a pulse width of 100 µs. These results support the use of GaN-on-Si-based SSPAs for the implementation of Ku-band active radars.

Conflicts of Interest:
The authors declare no conflict of interest.