Decision Levels and Resolution for Low-Power Winner-Take-All Circuit

Sensors in many applications must select the largest element in a sequence of currents. This can be performed in an analog way by the Winner-Take-All (WTA) circuit. This paper considers the classic version of the WTA Lazzaro circuit, working with MOS devices in a subthreshold regime. Since the separation of the gainer by analytically computable “decision levels” has recently been introduced, this paper aims to numerically verify and discuss these levels and their dependence on circuit and device parameters. For VT, the threshold voltage of MOS devices, which is primarily responsible for differences between components (mismatch), its relationship with the output voltages is theoretically demonstrated and numerically checked.


Introduction
Winner-Take-All (WTA) circuits are one of the most important building blocks in analog parallel signal processing, such as spatial acquisition and tracking, sound localization, image processing and neuromorphic systems [1][2][3][4][5][6][7]. The main function of a WTA is to select the highest input signal among multiple inputs, so two-input WTAs can also be used as half-wave and full-wave rectifiers [8][9][10]. Many WTA proposals can be found in the literature, such as voltage-mode configurations based on differential pair structures [11,12] or on inhibitory and local excitatory feedback loop circuits [13][14][15][16]. The first approach suffers from complexity and a high power comsumption, whereas the second approach has potential stability issues due to positive feedback.
In recent years, the processing of nanoamps has become increasingly important. These currents can come from sensors inside the human body- [17], from chemical reaction sensors, from motion tracking or from computer memory- [18]-to name just a few examples. In fact, the analog processing of very small signals was used in "neuromorphic" circuits initiated by Carver Mead at Caltech in the early 1990s [19,20]. In that context, the first W (inner) T(ake) A(ll) circuit appeared, known today as the "Lazzaro Circuit"- [21]. Its simplicity that leads to space savings on integrated chips has distinguished it technologically. Many improvements to the Lazzaro circuit have been proposed in the meantime [22,23], but the basic principle and configuration have not changed.
In [24], Sekerkiran et al. proposed a modified version of Lazzaro's WTA, which improved the resolution without requiring positive feedback, thus avoiding major stability issues. Their approach consisted of using an aditional transistor per cell to increase the open loop gain and, therefore, improve resolution. However, both Lazzaro's and Sekerkiran's WTAs need a high voltage swing at the input nodes to turn on the winning cell, which results in a slow response to abrupt input current changes.
The parameters of MOS and their interconnections must be as identical as possible. Integrated circuit technology, engaged in a race to reduce the size of chips and circuits, can-not ensure the strict identity of the parameters on the same chip or on different chips. Thus appears the so-called "mismatch"- [22][23][24][25], whose size is a criterion for the performance of the chips. It is all the more important as the circuit works with lower currents. In this way, the study of the variation in the performances of the circuits with MOS transistors working in the subthreshold (or weak inversion) when the model parameters slide around the design value is decisive. This paper considers the original Lazzaro circuit, working in the subthreshold as a selector of the maximum current rank. For the list of output voltages, a parallel paper co-authored by the present author- [26,27]-introduced a "higher decision level". Above it, only the highest rank (winner) in the output list must be placed. Similarly, a "lower decision level" must be above the second-largest rank and under the higher level. Both levels were rigorously defined and used to introduce the resolution performance of the selector.
In fact, we need two notions of resolution. One for the input lists-the input resolution-and one for the selection result-the output resolution. To be sensitive and efficient, a WTA fed with "crowded" lists must select the output through a "wide" separation. Below, after introducing the circuit static model in Section 2, we present the theoretical questions about decision levels and about the resolution in Sections 3 and 4. In Section 5, the monotonic dependence of the winner size on the threshold voltage V T of MOS devices is proven. Section 6 contains numerically computed examples. Analytically computed decision levels and resolutions are extensively checked and analyzed.

The Circuit Model
For the subthreshold regime-i.e., when V GS ≤ V T and V DS ≥ 0-we use the usual MOS model [28] with the usual notations: Then, the steady state of the Lazzaro WTA circuit in Figure 1 (with all devices in the subthreshold) can be obtained by I j = I T j and I C = N ∑ j=1 I T j where I T j and I T j are the I DS currents for T j and T j , respectively. Thus, we will move on to the following: where In the above equations, the MOS parameters are I 0 , k and V T while I j , I C and V DD are outside constant sources. For an input list of currents I = (I 1 , I 2 , . . . , I N ), Equation (3) provides the common potential V with which Equation (2) gives the output voltages U = (U 1 , U 2 , . . . , U N ). Obviously, we have to make sure that all transistors T j and T j work in the subthreshold, which means [26,29] V and U j must be restricted to As we prove in [26], the following restrictions are sufficient: where I M is the absolute maximum of currents allowed for processing. For ∆ andĈ, see below. Let us note that the right side in (9) is not a restriction. Finally, let us mention that, in [29], for the dynamic model of our circuit, the invariance of the solution in a weak inversion region as well as its asymptotic stability have been studied.

Decision Levels
To explain the issue of decision levels, let us start with a simple example. Let us consider our WTA in the particular case of N = 3, fed with the infinite number of lists in L(3, I M , ∆), that is, lists with three currents, no bigger that I M and separated from each other by the minimum distance ∆. The first list I = (I 1 , I 2 , I 3 ) with the (decreasing) order σ = (3, 1, 2) arrives at the WTA input-see Figure 2. The goal is to signal the "winning" rank σ1 = 3 of the largest current I 3 , even in the extreme case when "the loser"which is the second-largest current I 1 -is at the minimum distance ∆, I 3 − I 1 = ∆ and ∆ is so small that the two are not distinguishable on the [0, The WTA circuit translates the reading of the winner rank to the output list of voltages U = (U 1 , U 2 , U 3 ), which has the same order σ = (3, 1, 2). However, the winner U 3 is now split from the loser U 1 by a gap D − D, which is sufficiently large on the [0, U M ] scale.
In fact, we have to have U 3 ≥ D > D ≥ U 1 > U 2 . D is called "the upper decision level" and has the property that it is surpassed only by the winner. Thus, the outputs (U 1 , U 2 , U 3 ) are compared with D-see Figure 2-and rank 3 will be the unique winner.
The winning ranks are "3" in the first case and "2" in the second, since U 3 and W 2 surpass D.
Furthermore, D is called "the lower decision level", and all the "losers" (U 1 and U 2 here) are under it. The distance D − D is significant on the scale [0, U M ], where U M is the maximum voltage. Returning to Figure 2, let us consider a second list (J 1 , J 2 , J 3 ) from L(3, I M , ∆) applied at the input. Suppose that J 2 > J 3 > J 1 and the winner rank "2" has to be signaled. This is performed by obtaining the output voltages (W 1 , where the only rank surpassing the upper decision level D is "2", the winner. The losers are below the lower decision level D. The processing should be similar for any list from L(3, I M , ∆) when using the same decision levels D and D and the same circuit parameters.
For the input list I = (I 1 , I 2 , . . . , I N ) written in the terminal order, let us denote σ = (σ1, σ2, . . . , σN) a permutation of the indices such that the currents in I σ = (I σ1 , I σ2 , . . . , I σN ) are in decreasing order: Then, from (2), it is clear that the output voltages U = (U 1 , U 2 , . . . , U N ) are in the same decreasing order, i.e., Both I σ1 and U σ1 are called "winner" while both I σ2 and U σ2 are called "loser". To U σ3 , U σ4 , . . . , U σN and to I σ3 , I σ4 , . . . , I σN as well, we use the same name, "losers". We will assume that the input currents I ∈ N belong to the class L(N, I M , ∆), i.e., their components are inside the [0, I M ] interval and are mutually separated by distance ∆ at least. To abbreviate the writing, from here on, we will denote this class simply by L. Thus, This leads to the existence of C jm , C jM intervals in which each I σj current is forced to belong: Here, for each j ∈ 1, N, and We putĈ the list of maximum currents of each rank from (10). Note that the intervals in (14) do not overlap. All possible lists at the input (i.e., satisfying (7)- (10)) have in common the number of elements N, the maximum current I M and a measure of the agglomeration of the currents ∆. Let us denote by L this (infinite) family of input lists. The raison d'être of the WTA circuit is to identify the rank σ1 of the highest current I σ1 in list I and to achieve this for any input list in L without changing the parameters or configuration.
A recent co-work by the author of this paper- [26]-has introduced two "decision levels", D and D, which split the output list as follows: Here, D is defined as the smallest winner of the output lists when all inputs in L are applied. Similarly, D is the highest loser for all inputs in L. The main attraction of these particular levels consists of the fact that they can be obtained "semi-analytically".
Thus, it is proven that where is the L-list with currents in (15). This means that the upper decision level D is exactly the winner of the output list U = U C = U 1 C , U 2 C , . . . , U N C when the currents in C are the input. It is shown that they are the smallest possible currents of each rank, computable as in (15). Also, we have where C = (C 1M , C 2M , C 3m , . . . , C Nm ) -see (15) and (16). In other words, the lower decision level D is identified as the loser of the output list U = U(C) = (U 1 (C), U 2 (C), . . . , U N (C)) when the currents in C are the input. In addition, (22) shows that the first two currents in C are the highest in their class L, while all others currents are the lowest possible in their respective rank. After C and C are evaluated, they are used as inputs I j in (2)+(3) to compute (numerically) the outputs U C and U(C). From them, the decision levels D and D are extracted as in (19) and (21), respectively. Finally, we need the largest U M voltage when applying L. It can be shown that the maximum output voltage U M is obtained if we apply-see [26]-at the input C = (C 1M , C 2m , C 3m , . . . , C Nm ) (23) and take the maximum voltage in the output

Resolutions
In order to appreciate the WTA performances, apart from the threshold D and D, we need a measure of the finesse of selecting the winner. First, we need a measure of the "crowding" of the currents at the input.
The family L contains lists of currents on the [0, I M ] scale, whose cramming is measured by ∆. The difference between the largest and the second-largest current of any list is at least ∆. The coefficient ω defined by This will be called "THE INPUT RESOLUTION". When ω is very small, perceiving I w (the winner) and I l (the loser) as distinct from each other is difficult and prone to error. On the output side, the voltages are similarly arranged on the [0, U M ] scale. However, the positions of the w (i.e., winner) and l (i.e., loser) ranks are now controlled by the decision levels D and D: D and D do not change when a new list from L arrives. Under constraints in (7)-(10), D and D are fixed by (19) and (21). Each winner of each list surpasses D. Each loser of each list in L falls under D. The gap D − D compared with the entire U M will be denoted by Ω and called "THE OUTPUT RESOLUTION": The similarity between ω at input and Ω at output is complete. Both of them indicate how much of the "reading scale" is taken up by the smallest possible size difference between the w and l ranks. The circuit is effective if "it amplifies" the resolution of the input list. The large values for Ω/ω mean that the winning rank is highly distinct. To understand the WTA input-output mechanism, we study the function Ω(ω) when I M and I C are unchanged. For clarity, we will translate the results obtained so far in terms of ω, where ω = ∆/I M .
In [26], it is shown that at least for a part of ω's "spectre". However, examples show that the ratio Ω ω is in the order of hundreds at least.
From (27), it follows immediately that which means that the Ω(ω) function is monotonously increasing. This corresponds to "the intuition" that more disjointed current lists are processed more efficiently (i.e., the gap D − D is bigger).

Exploring the Mismatch
The threshold voltage V T is the value of the voltage V GS that controls the transition between the distinct operating regions of the MOS. The value of V T is influenced by the thickness of the oxide layer, as well as by body doping. Also, V T depends a lot on the parasitic charge trapped between oxide and silicon. In contrast to this "accidental" charge, some charge can be introduced intentionally through the process called "ion implantation".
Moreover, it is well known that subthreshold design has dramatically increased the sensitivity to process variation. This fact is taken into account by introducing the variation in the zero current with threshold voltage. Indeed, where I 0 does not depend on V T -see [28]. Subsequently, we use (33) in models (2) and (3) and try to evaluate the influence of V T on the output U j . Fortunately, we can analytically deduce a qualitative behaviour. Namely, we can show that U j decreases with V T : For this, let us denote F j (V, that the function in (4) becomes Equation (3) with a fixed I C gives We easily obtain Then, (36) gives However, from (2), Here, the two derivatives of F j are positive and by also using (37) we derive ∂U j ∂I 0 > 0.

Decision Levels
In this paragraph, we deal with the decision levels D and D on the [0, U M ] scale. The known quantities are k, V T , I 0 and V t (i.e., the MOS device parameters) then N, I C and V DD (circuit parameters) and I M and ∆ (i.e., L class characteristics). All these quantities must satisfy the restrictions (7)- (10). Their numerical values are k = 0.9, V T = 1 V, I 0 = 10 −18 Amp, V t = 0.026 V, N = 100, I C = 10 −17 Amp, V DD = 1.5 V, I M = 10 nA and ∆ = 0.01 nA. We will call this case "Example 1". Now follows the analytical part of decision levels calculation. Our result is obtained in formula (20), (22) and (23), which give three particular input lists of currents C, C and C. For their calculation, we use (15) and (16), which lead to C jm = (100 − j)0.01 and C jM = 10 − (j − 1)0.01, both in nAmps and for j ∈ 1, 100. Thus, lists C, C and C from (20), (22) and (23) are now known. At this point, the numerical part of the calculation begins. We solve the 101 equations in (2) and (3) three times corresponding to the inputs C, C and C. We obtain three output sequence U C , U(C) and U C , respectively, each of 100 voltages. From each of them, we select one component according to (19), (21) and (24). Namely, the largest voltage in U C is the upper decision level U 1 C = D. This means that the input resolution yields an input one of 681 times higher. The ratio Ω/ω is a performance index for WTA. Now, we change V T from 1 V to 1.1 V. For the same parameters, k, I 0 , V t , N, V DD , I M and ∆, we obtain the lists C, C and C. Solving again the 101 equations from (2) and (3) (this time with V T = 1.1 V), we obtain U 1 C = D = 515 mV, U 2 (C) = D = 179 mV and U 1 C = U M = 589 mV. Then, Ω% = 57%-see Figure 3b and the comments in Section 6.2.

Mismatch
We take the device parameters in Example 1 except for I 0 , which is replaced by (33) with I 0 = 10 −33 Amp. Also, we successively use in (33) V T as 1 V, 1.02 V, 1.04 V, . . ., 1.1 V. For the class L with I M = 10 nA and ∆ = 0.01 nA, N = 100, we follow the procedure in Section 6.1 and determine U M , D and D for each of these six cases. The results are presented in Table 1. We notice that major effects occur when the threshold voltage V T increases by 10%-See Figure 3a,b. The maximum voltage U M decreases drastically by 27%, while the higher decision level D decreases by 29%. Remarkably, the lower decision level D is hardly influenced by the deviation of V T . Even more remarkable is that the decrease in the output resolution by 10 percent does not sufficiently reflect the major worsening of the accuracy in the appreciation of the maximum U σ1 . It turns out that the maximum output voltage U M must accompany the output resolution parameter Ω in the WTA circuit specifications.

Example 3
With the WTA data from the previous example, let us take a list of 100 currents given by Among these 100 currents two groups are shown in Table 2 Column 1. The largest current in our list I = (I 1 , I 2 , . . . , I 100 ) is found at terminal 50. If σ = (σ 1 , σ 2 , . . . , σ 100 ) is the permutation that gives the descending order, then σ 1 = 50, i.e., I σ 1 = I 50 = 1.97 nA, as in Table 2 Column 1. Also, the second-largest current is at terminal 99. Thus, σ 2 = 99, i.e., I σ 2 = I 99 = 1.96 nA, as in Table 2. Now, we solve the Equations (2) and (3) with the above currents and V T = 1 V. Out of the output U = (U 1 , U 2 , . . . , U 100 ), Table 2 Column 2 shows the voltages U 49 to U 54 and U 95 to U 100 . It is verified that the order in U is given by the same permutation σ as currents, such that the winner is U σ1 = U 50 = 749 mV and the loser is U σ2 = U 99 = 137 mV-see Table 2  The output resolution is Ω% = 68%, way better than ω% = 0.1% at the input.
Next, we change the threshold voltage V T ( Table 2 Column 3) to 1.1 V and obtain an output similarly ordered, i.e., the winner is U 50 and the loser is U 99 . Their placement above D = 515 mV and under D = 179 mV, respectively, (see Table 1) shows the correctitude of detaching the largest element of the input list. Table 2. Examples 3 and 4. I 49 − I 54 and I 95 − I 100 , two groups of currents given in (38)-(40) are listed in Column 1. Column 2 shows output voltages for V T = 1 V. Column 3 shows output voltages for V T = 1.1 V. Column 4 shows the indices σj-the j-th current (and voltage) in descending order.

Conclusions
Finding the maximum in continuous signal strings is a fundamental operation in signal processing. When processing speed is essential, the analog version is preferable. In this framework, the WTA circuit has imposed itself through technological simplicity. Of course, in this case we have to solve the problem of precision in separating the maximum rank ("winner") from the next rank ("loser"). This paper, in close connection with [26], verifies numerically that "the decision levels" work correctly. For this, the theoretical notions of decision levels, resolution and mismatch are specified first. Then, a class of strings of 100 currents is considered for which the decision levels and input and output resolution are analytically calculated. Numerical processing follows that simulates the operation of the WTA circuit. An ordered string of voltages is obtained at the output. It is verified that the largest element of this string exceeds the upper decision level while the rest of the elements are crowded much further, namely, below the lower decision level. The output resolution compared to the input resolution indicates how much "the winner" is separated, i.e., the effectiveness of the WTA. It is theoretically shown that any of the output voltages decreases monotonically with increases in V T . It is then verified by numerical calculation that the small increase in the threshold voltage of the MOS transistors leads to a drastic decrease in both the decision levels and the output resolution. Since the manufacturing technology cannot ensure a really constant V T for series production, this is a major problem in the design of MOS circuits, especially those that work in the subthreshold.