1.2 V Differential Difference Transconductance Amplifier and Its Application in Mixed-Mode Universal Filter

This paper presents a new mixed-mode universal filter based on a differential difference transconductance amplifier (DDTA). Unlike the conventional transconductance amplifier (TA), this DDTA has both advantages of the TA and the differential difference amplifier (DDA). The proposed filter can offer four-mode operations of second-order transfer functions into a single topology, namely, voltage-mode (VM), current-mode (CM), transadmittance-mode (TAM), and transimpedance-mode (TIM) transfer functions. Each operation mode offers five standard filtering responses; therefore, at least twenty filtering transfer functions can be obtained. For the filtering transfer functions, the matching conditions for the input and passive component are absent. The natural frequency and the quality factor can be set orthogonally and electronically controlled. The performance of the proposed topology was evaluated by PSPICE simulator using the 0.18 µm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC). The voltage supply was 1.2 V and the power dissipation of the DDTA was 66 µW. The workability of the filter was confirmed through experimental test by DDTA-based LM13600 discrete-component integrated circuits.


Introduction
Universal filters are basic electronic blocks that usually provide five filtering responses into a single topology, namely, low-pass (LP), high pass (HP), band pass (BP), band stop (BS), and all pass (AP) filters. The applications such as three crossover network high-fidelity loudspeakers [1,2], touch-tone telephone tone decoders [2], and high-order filters [3] require universal filters as the basic building blocks. Moreover, universal filters can be fabricated as commercial programmable filter-integrated circuits [4]. As a commercially available IC, it is valuable if a single IC can provide a multi-mode filter that depends on the applications of the circuit designer. There are many universal filters available in the open literature, for example, see [5][6][7][8][9][10][11][12][13][14]. Considering input and output signals, these universal filters can be classified as four-mode operations as follows: voltage-mode (VM) filter when both input and output signals are in voltage form [5,6]; current-mode (CM) filter when both input and output signals are in current form [7,8]; transadmittance-mode (TAM) filter when the input signal is in voltage form while the output signal is in current form [9][10][11], and finally transimpedance-mode (TIM) filter when the input signal is in current form while the output signal is in voltage form [12][13][14]. It should be noted that the universal filters in [12][13][14] offer only a single-mode filter.
A universal filter that allows electronic tunability can offer some advantages such as the ease of compensation when the natural frequency is deviated by the effect of temperature or process variations, while a universal filter without a floating capacitor and resistor and free from the passive component matching condition is more suitable for integrated circuit implementation. A universal filter that requires a minus-type input signal or an input signal matching condition needs additional circuits such as current-mirror for CM operation or inverting amplifier for VM operation. This requirement defects VM operation because many passive components are usually required, unless the universal filter provides a fully differential structure. Finally, a universal filter that provides at least twenty filtering responses means that each operation mode can realize five standard filtering responses; hence, the full capability of the mixed-mode universal filter can be obtained.
This study focused on a mixed-mode universal filter that could realize VM, CM, TAM, and TIM filters into a single topology. Each operation mode could realize five standard filtering responses; thus, twenty filtering responses could be obtained. The active device, named differential difference transconductance amplifier (DDTA), was used in this study. This device employs high-input impedance terminals with the advantage of input voltage arithmetic operation such as the differential difference amplifier (DDA) [47], and the capability of electronic tuning such as the transconductance amplifier. Thus, a DDTA-based circuit is easy for addition and subtraction of voltage signals and possesses an electronic tuning capability [48][49][50][51]. Unlike the standard differential difference transconductance amplifier that was created by two differential pair DDAs followed by the transconductance amplifier presented in [52], the proposed DDTA is based on one multiple-input differential pair DDA [53][54][55][56] that serves as a differential difference transconductance amplifier followed by a voltage buffer. Therefore, the proposed DDTA could reduce the count of active blocks, power dissipation, and chip area as a result of using the multiple-input MOS transistor (MI−MOST) technique [57]. It is worth noting that the MI-MOST comes with several advantages compared with the multiple-input floating-gate (MIFG) transistor [58]. The MIFG transistor uses the charge conversation principle and hence it is incompatible with modern nanoscale gate-leakage CMOS technologies [59]. The MIFG implementation requires two-polysilicon technology, and the remaining residual charge on its gate causes voltage offset. Therefore, a new DDTA-based mixed-mode universal filter that could provide at least twenty filtering responses of VM, CM, TAM, and TIM filters is presented in this paper. The DDTA uses the MI−MOST technique that offers simplification of its overall structure and a reduction in the power dissipation. The proposed mixed-mode universal filter offers the following advantages such as: i. electronic tuning capability; ii.
being free from a floating passive component; The comparison of the proposed filter with the previous mixed-mode universal filters is shown in Table 1. Compared with [30,31] that have equal active and passive components, the proposed filter is free from active and passive component matching conditions as well as the minus-type input signal requirement. Compared with [43] that offers similar performances, the proposed filter employs fewer components and provides more filtering functions. Compared with [44][45][46] that employ fewer devices, the proposed filter applies the input voltage signal via a high-impedance node whereas the filters in [44][45][46] apply the input voltage signal via a capacitor or resistor.
This paper is organized as follows: in Section 2, the TA-based DDA using MI-MOSTs and the proposed mixed-mode universal filter are presented; Section 3 presents the simulation results and experimental results; and Section 4 concludes the paper.

Proposed Mixed-Mode Universal Filter
The symbol of DDTA is shown in Figure 1a. The relationship of the terminals can be expressed by The symbol of DDTA is shown in Figure 1a. The relationship of the terminals can be expressed by It should be noted that the output is the addition and subtraction of inputs 1 , 2 , and 3 , while the output is the current that is converted from by , where is the internal transconductance of DDTA. Therefore, DDTA included the DDA as an input stage that serves also as a transconductance amplifier (TA) as an output stage. Compared with the differential difference current conveyor transconductance amplifier (DDCCTA) [60], the DDTA structure employs less MOS transistors. Figure 1b shows the internal structure of the proposed DDTA. The voltage follower (VF) circuit was used to avoid the loading effect. Therefore, the w-terminal possessed a low-impedance level that could be directly connected to a low-resistance external load. The structure of DDTA in [52] was developed to the DDTA using MI-MOST as shown in Figure 2. Figure 3a shows the MI-MOST symbol with n number of inputs where the input terminals V1, …, Vn are coupled to the gate terminal of the conventional MOST by n input capacitors CG1, …, CGn. To guarantee the DC operation, the high resistances RMOS1, …, RMOSn are connected in parallel to each input capacitor, as shown in Figure 3b. The high resistance is implemented by two MOSTs (MR) operating in the cut-off region as shown in Figure 3c, which offers a minimum area of chip. It is worth noting that the pseudo-resistors shunt the input capacitors for proper DC operation of the input transistor; therefore, there are no floating-gate issues as in the case of the MIFG transistor. However, for AC operation, the input capacitors create a short circuit for the AC signal, the same as in the case of the MIFG technique.  It should be noted that the output V w is the addition and subtraction of inputs V y1 , V y2 and V y3 , while the output I o is the current that is converted from V w by G m , where G m is the internal transconductance of DDTA. Therefore, DDTA included the DDA as an input stage that serves also as a transconductance amplifier (TA) as an output stage. Compared with the differential difference current conveyor transconductance amplifier (DDCCTA) [60], the DDTA structure employs less MOS transistors. Figure 1b shows the internal structure of the proposed DDTA. The voltage follower (VF) circuit was used to avoid the loading effect. Therefore, the w-terminal possessed a low-impedance level that could be directly connected to a low-resistance external load.
The structure of DDTA in [52] was developed to the DDTA using MI-MOST as shown in Figure 2. Figure 3a shows the MI-MOST symbol with n number of inputs where the input terminals V 1 , . . . , V n are coupled to the gate terminal of the conventional MOST by n input capacitors C G1 , . . . , C Gn . To guarantee the DC operation, the high resistances R MOS1 , . . . , R MOSn are connected in parallel to each input capacitor, as shown in Figure 3b. The high resistance R MOS is implemented by two MOSTs (M R ) operating in the cut-off region as shown in Figure 3c, which offers a minimum area of chip. It is worth noting that the pseudo-resistors shunt the input capacitors for proper DC operation of the input transistor; therefore, there are no floating-gate issues as in the case of the MIFG transistor. However, for AC operation, the input capacitors create a short circuit for the AC signal, the same as in the case of the MIFG technique.

Proposed Mixed-Mode Universal Filter
The symbol of DDTA is shown in Figure 1a. The relationship of the terminals expressed by It should be noted that the output is the addition and subtraction of inpu 2 , and 3 , while the output is the current that is converted from by , is the internal transconductance of DDTA. Therefore, DDTA included the DDA input stage that serves also as a transconductance amplifier (TA) as an output stage pared with the differential difference current conveyor transconductance am (DDCCTA) [60], the DDTA structure employs less MOS transistors. Figure 1b show internal structure of the proposed DDTA. The voltage follower (VF) circuit was u avoid the loading effect. Therefore, the w-terminal possessed a low-impedance lev could be directly connected to a low-resistance external load. The structure of DDTA in [52] was developed to the DDTA using MI-MOST as s in Figure 2. Figure 3a shows the MI-MOST symbol with n number of inputs whe input terminals V1, …, Vn are coupled to the gate terminal of the conventional MOS input capacitors CG1, …, CGn. To guarantee the DC operation, the high resistances …, RMOSn are connected in parallel to each input capacitor, as shown in Figure 3b. Th resistance is implemented by two MOSTs (MR) operating in the cut-off reg shown in Figure 3c, which offers a minimum area of chip. It is worth noting th pseudo-resistors shunt the input capacitors for proper DC operation of the input tr tor; therefore, there are no floating-gate issues as in the case of the MIFG transistor. ever, for AC operation, the input capacitors create a short circuit for the AC sign same as in the case of the MIFG technique.  It is worth noting that the multiple input techniques are simply created by a set of parallel capacitors shunted with high-resistance pseudo-resistors (M R ). This technique can be applied to the gate-, bulk-, gate-bulk (DTMOS), or bulk-quasi-floating-gate terminals of a standard MOS transistor [61].
In Figure 2, the transistors M 1 -M 6 and M 9 create the DDA core circuit. The MI-MOST differential pairs M 1 and M 2 , the transistor M 3 , and the two current sources M 4 and M 5 create the differential stage of the DDA. The transistor M 3 along with M 2 and M 5 create a flipped voltage follower (FVF) [62] and it is used to enforce the current of M 3 (i.e., I M3 ) to be equal to the tail current, same as in the case of the differential stage of the conventional structure. The FVF modifies the gate of M 3 to ensure equal drain currents for both differential pairs M 1 and M 2 [63]. Furthermore, due to the FVF, the minimum voltage supply is the sum of one gate-source and one drain-source voltage It is worth noting that the multiple input techniques are simply created by a set of parallel capacitors shunted with high-resistance pseudo-resistors (MR). This technique can be applied to the gate-, bulk-, gate-bulk (DTMOS), or bulk-quasi-floating-gate terminals of a standard MOS transistor [61].
In Figure 2, the transistors M1-M6 and M9 create the DDA core circuit. The MI-MOST differential pairs M1 and M2, the transistor M3, and the two current sources M4 and M5 create the differential stage of the DDA. The transistor M3 along with M2 and M5 create a flipped voltage follower (FVF) [62] and it is used to enforce the current of M3 (i.e., IM3) to be equal to the tail current, same as in the case of the differential stage of the conventional structure. The FVF modifies the gate of M3 to ensure equal drain currents for both differential pairs M1 and M2 [63]. Furthermore, due to the FVF, the minimum voltage supply is the sum of one gate-source and one drain-source voltage ( (min) = − 3 + − 5 ). Transistors M6 and M9 form a super class AB second stage [64]. The R MOS is responsible for the gate DC biasing of the transistor M6, whereas the capacitor C delivers the AC signal to this gate. The node ′ is connected to the input terminal of M2, creating negative feedback for obtaining a unity-gain voltage follower. The DDA stability is insured by the compensation capacitor Cc. The transistors M12-M18, RMOS1, and capacitors Cc1 and C1 are used to work as a voltage follower circuit. The operation is similar to the first stage of DDTA that was previously explained. Therefore, the relationship = 1 − 2 + 3 ( = ′ ) can be obtained. The bias current and Mb generated the bias voltage for M4−M8 and M15−M17. The terminal ′ is connected to a linear adjustable resistor that converts the voltage ′ to current ′ . This current is mirrored by M7−M10 to the o-terminals; thus, = ′ can be achieved. Additional output current o-terminals can be obtained using complementary transistors such as M8 and M11. Hence, this part works as a transconductance amplifier. The output current is obtained as Note that the high linearity is achieved due to the linear resistance Rset. The DDA operates in a closed loop, just forming a second-generation current conveyor, with the ′ output terminal loaded by Rset, and such a configuration can be considered as a transconductance amplifier. However, the attenuation of the input signal by capacitors allows enlarging the input common mode range, as well as the range of linear operation (the range where the so-called hard nonlinearities associated with changing the region of operation of transistors do not appear). Transistors M 6 and M 9 form a super class AB second stage [64]. The R MOS is responsible for the gate DC biasing of the transistor M 6 , whereas the capacitor C delivers the AC signal to this gate. The node w is connected to the input terminal of M 2 , creating negative feedback for obtaining a unity-gain voltage follower. The DDA stability is insured by the compensation capacitor C c . The transistors M 12 -M 18 , R MOS1 , and capacitors C c1 and C 1 are used to work as a voltage follower circuit. The operation is similar to the first stage of DDTA that was previously explained. Therefore, the relationship (2) Note that the high linearity is achieved due to the linear resistance R set . The DDA operates in a closed loop, just forming a second-generation current conveyor, with the w output terminal loaded by R set , and such a configuration can be considered as a transconductance amplifier. However, the attenuation of the input signal by capacitors allows enlarging the input common mode range, as well as the range of linear operation (the range where the so-called hard nonlinearities associated with changing the region of operation of transistors do not appear).
The proposed mixed-mode universal filter using DDTAs is shown in Figure 4. It consisted of five DDTAs and two grounded capacitors. The variant transfer functions could be obtained by applying the appropriate input signals V in1 , V in2 , I in1 , and I in2 and selecting the appropriate output signals V o1 , V o2 , V o3 , V o4 , V o5 , I o1 , and I o2 . The input voltage which is not used (V in = 0) should be attached to ground while the input current which is not used (I in = 0) should be floated. The G msetj (G msetj = 1/R setj ) is the transconductance of DDTA j (j = 1, 2, 3, 4, 5). Using (1) and nodal analysis, the output voltages and currents of the proposed mixed-mode universal filter can be expressed by where D(s) = s 2 C 1 C 2 G mset5 + sC 1 G mset1 G mset5 + G mset1 G mset2 G mset5 . By appropriately applying the input signals (V in1 , V in2 , I in1 , and I in2 ) and choosing the output terminals (V o1 , V o2 , V o3 , V o4 , V o5 , I o1 , I o2 , I o3 , and I o4 ), the VM, CM, TAM, and TIM filters can be expressed as in Table 3. It was evident that the proposed filter offers four modes of operation into a single topology. Each mode of operation provides five standard filtering transfer functions; hence, at least twenty transfer functions can be obtained. In addition, several filtering functions can be obtained from the same mode of operation; thus, the proposed topology can provide 36 filtering functions. It should be noted that some filtering functions offer some advantages such as the gain of transfer function when V in1 is the input and V o5 is the output for LP of the VM filter, the high-Q filter when V in1 = V in2 is the input and V o2 is the output for BP of the VM filter, and offer both non-inverting and inverting filtering functions for HP of TAM filter.
The natural frequency (ω o ) and the quality factor (Q) of the proposed filter can be given as From (14) and (15), the parameter ω o can be adjusted electronically by G mset1 and G mset2 whereas the parameter Q can be given by C 2 /C 1 by keeping G mset1 = G mset2 . Thus, the proposed filter can be electronically controlled for parameter ω o and orthogonally controlled for parameters ω o and Q.  It should be noted that some filtering functions offer some advantages such as the gain of transfer function when 1 is the input and 5 is the output for LP of the VM filter, the high-Q filter when 1 = 2 is the input and 2 is the output for BP of the VM filter, and offer both non-inverting and inverting filtering functions for HP of TAM filter.
The natural frequency ( ) and the quality factor ( ) of the proposed filter can be given as = √ From (14) and (15), the parameter can be adjusted electronically by 1 and 2 whereas the parameter can be given by 2 / 1 by keeping 1 = 2 . Thus, the proposed filter can be electronically controlled for parameter and orthogonally controlled for parameters and . It should be noted that the terminals 3 , 4 , and 5 possess low-output impedance whereas the terminals 1 , 2 , 3 , and 4 possess a high-output impedance, and thus the loads can be connected directly without additional buffer circuit requirements. The terminals 1 and 2 possess a high-input impedance, hence the condition such as 1 = 2 is not required for additional buffer circuits. However, the terminals 1 and 2 do not provide a low-output impedance and the terminals 1 and 2 do not provide a low-input impedance; therefore, the buffer circuits may be required if low-impedance loads are connected and if low-impedance current signals are supplied. In the case of CM and TIM filters, the matching condition is absent and in the case of VM and TAM, the inverting-type input is not used. It should be noted that the terminals V o3 , V o4 , and V o5 possess low-output impedance whereas the terminals I o1 , I o2 , I o3 , and I o4 possess a high-output impedance, and thus the loads can be connected directly without additional buffer circuit requirements. The terminals V in1 and V in2 possess a high-input impedance, hence the condition such as V in1 = V in2 is not required for additional buffer circuits. However, the terminals V o1 and V o2 do not provide a low-output impedance and the terminals I in1 and I in2 do not provide a low-input impedance; therefore, the buffer circuits may be required if low-impedance loads are connected and if low-impedance current signals are supplied. In the case of CM and TIM filters, the matching condition is absent and in the case of VM and TAM, the inverting-type input is not used.
The non-ideal transconductance gain G msetnj is given by where ω gmj and G msetj denote the first-order pole frequency and the open-loop transconductance gain of j-th DDTA. The non-ideal transconductance gain of DDTA is caused by the parasitic capacitor and parasitic resistor at o-terminal. In the frequency range that can generate these parasitic parameters, G msetnj can be modified as [65] G msetnj (s) ∼ = G msetj 1 − µ j s (18) where µ j = 1/ω gmj . The filter in Figure 4 was re-analyzed by using (16), and the denominator of the transfer functions can be rewritten as Using (18), (19) becomes From (20), the non-idealities of the DDTAs affect the circuit characteristics which depart from ideal values. The parasitic effects from the DDTA could be made negligible by satisfying the following condition: Therefore, the non-ideal natural frequency (ω on ) and the non-ideal quality factor (Q n ) can be expressed, respectively, by The sensitivity of the ω on and Q n with respect to circuit components and non-ideal parameters can be expressed as follows: It can be expressed from (25)-(27) that the proposed filter showed good active and passive sensitivities because all the sensitivities were within unity in magnitude.

Simulation Results
The DDTA in Figure 2 was designed using a 1.2 V voltage supply (V DD = −V SS = 0.6 V) and 5 µA bias current. The circuit consumed 66 µW of power. The PSPICE simulation was used to simulate the circuit using a 0.18 µm CMOS technology from TSMC. The parameters of the components and the simulated performances of the used DDTA are shown in Tables 2 and 3, respectively.  Table 3. Parameters of the components of DDTA in Figure 2.  Figure 5 shows the relation between voltages V w and V y1 with R set = 15 kΩ and its voltage error. At V y1 = 0 mV, the voltage error was −0.13 mV and at V y1 = ±100 mV, the voltage error was less than 2 mV. To show the voltage-to-current converter of DDTA, the voltage V in (V in = V in+ − V in− ) was applied to the input, and the current at o-terminal was measured. Figure 6 shows the relation between I o and V in with different values of R set (R set = 10, 15, 20, 25 kΩ). The transconductances G mset of DDTA can be given by 1/R set (G mset1 = 1/R set ). The simulated performances of DDTA in Figure 2 are summarized in Table 2.
The proposed mixed-mode filter in Figure 4 was designed for obtaining 1 kHz of the natural frequency. The capacitors C 1 = C 2 =10 nF and R set1 = R set2 = R set3 = R set4 = R set5 = 15 kΩ. These R set resistors can be integrated on chip using a high-resistance poly resistor; however, the high value 10 nF capacitors should be off-chip.   7a, 8a, 9a and 10a show, respectively, the simulated magnitude frequency responses of the LP, HP, BP, and BS responses of the VM, CM, TAM, and TIM filters. The natural frequency of these results was 1.04 kHz. The simulated magnitude and phase characteristics of the AP filter of the VM, CM, TAM, and TIM filters are shown respectively in Figures 7b, 8b, 9b and 10b. The total power consumption of the filter was 330 µ W. It can be confirmed from Figures 7-10 that the proposed mixed-mode filter provides five standard filtering responses of VM, CM, TAM, and TIM filters.  responses of the LP, HP, BP, and BS responses of the VM, CM, TAM, and TIM filters. The natural frequency of these results was 1.04 kHz. The simulated magnitude and phase characteristics of the AP filter of the VM, CM, TAM, and TIM filters are shown respectively in Figures 7b, 8b, 9b and 10b. The total power consumption of the filter was 330 µ W. It can be confirmed from Figures 7-10 that the proposed mixed-mode filter provides five standard filtering responses of VM, CM, TAM, and TIM filters.  To confirm that the proposed filter provided electronic tuning ability, the BP filter was simulated by adjusting 1 = 2 = 10 kΩ, 15 kΩ, 20 kΩ, 25 kΩ while 3 = 4 = 5 = 15 kΩ. Figure 11 shows the center frequency of 0.64 kHz, 0.79 kHz, 1.04 kHz, To confirm that the proposed filter provided electronic tuning ability, the BP filter was simulated by adjusting R set1 = R set2 = 10 kΩ, 15 kΩ, 20 kΩ, 25 kΩ while R set3 = R set4 = R set5 = 15 kΩ. Figure 11 shows the center frequency of 0.64 kHz, 0.79 kHz, 1.04 kHz, and 1.51 kHz when the resistance R set1 = R set2 was 25 kΩ, 20 kΩ, 15 kΩ, and 10 kΩ, respectively. The total harmonic distortion (THD) of the LP response of VM and CM filters was investigated by applying the single-tone input signal of 100 Hz to the input. The simulated THDs of VM and CM filters with different amplitudes are respectively shown in Figure 12a,b. The THD was less than 1.09% for input amplitude of 325 mV (peak) of the VM filter and the THD was less than 1.21 for input amplitude of 20 µA (peak) of the CM filter. The RMS output noise of the LP filter integrated in the bandwidth of 1 kHz was performed and the value of this noise was 150 µV. Thus, the dynamic range for 1.09% THD was 63.69 dB.  The proposed filter was investigated by applying two tones closely spaced in frequency into the input of the BP filter and the third-order distortion products (IMD3s) produced by the circuit nonlinearity were determined. In this case, the IMD3 of the VM and CM filters was investigated by applying the first tone with a sine wave frequency of 0.9 kHz and the second tone with 1.1 kHz. The simulated IMD3s of the VM and CM filters are respectively shown in Figure 13a,b. The IMD3 was around −37.23 dB for 100 mV (peak) of the VM filter and the IMD3 was around −36 dB for 7 µA (peak) of the CM filter. The VM filter was used to test its temperature performance. The simulated magnitude frequency responses of the LP, BP, HP, BS, and AP filter when the temperature was varied from −10 to 70 • C are shown in Figure 14. The proposed filter was also investigated using a Monte Carlo analysis by assuming that the fluctuation of the natural frequency changes caused by deviation of the capacitors and the threshold voltage of the MOS transistor. The BP response of the VM filter was simulated by setting 5% tolerances of the capacitors C 1 and C 2 and 5% variations of the transistor threshold voltage at 1.04 kHz, Q ∼ = 1, and 200 Gaussian distribution runs. Figure 15 shows the derived histogram of the natural frequency which expressed that the standard deviation (σ) of f o was 33.339 Hz and the maximal and minimal values of f o were 1.132 kHz and 0.967 kHz, respectively. The VM filter was used to test its temperature performance. The simulated magnitude frequency responses of the LP, BP, HP, BS, and AP filter when the temperature was varied from −10 to 70 °C are shown in Figure 14 . The proposed filter was also investigated using a Monte Carlo analysis by assuming that the fluctuation of the natural frequency changes caused by deviation of the capacitors and the threshold voltage of the MOS transistor. The BP response of the VM filter was simulated by setting 5% tolerances of the capacitors C1 and C2 and 5% variations of the transistor threshold voltage at 1.04 kHz, Q ≅ 1, and 200 Gaussian distribution runs. Figure 15 shows the derived histogram of the natural frequency which expressed that the standard deviation (σ) of fo was 33.339 Hz and the maximal and minimal values of fo were 1.132 kHz and 0.967 kHz, respectively.

Experimental Results
The proposed mixed-mode universal filter was also tested experimentally to confirm its functionality. The simulation results based on the macro model and the measured results are included for comparison. The DDTA was realized using OTAs as shown in Figure 16 [52]. The prototype circuit was realized using commercially available integrated circuit LM13700N that consists of two current-controlled transconductance amplifiers. Note the benefit of the MI-MOST on the TA-based DDA in Figure 2 in simplifying the CMOS structure and reducing the number of ICs needed to build the filter application. For instance, to create the multiple input (y 1 , y 2 , and y 3 ) of the DDA in Figure 16, two transconductance amplifiers (OTA 1 , OTA 2 ) are needed and another two OTAs are needed to construct the TA, hence two LM13700Ns are needed for each DDTA.

Experimental Results
The proposed mixed-mode universal filter was also tested experimentally to confirm its functionality. The simulation results based on the macro model and the measured results are included for comparison. The DDTA was realized using OTAs as shown in Figure 16 [52]. The prototype circuit was realized using commercially available integrated circuit LM13700N that consists of two current-controlled transconductance amplifiers. Note the benefit of the MI-MOST on the TA-based DDA in Figure 2 in simplifying the CMOS structure and reducing the number of ICs needed to build the filter application. For instance, to create the multiple input (y1, y2, and y3) of the DDA in Figure 16, two transconductance amplifiers (OTA1, OTA2) are needed and another two OTAs are needed to construct the TA, hence two LM13700Ns are needed for each DDTA. For measurement setup, the supply voltage was ±5 V and the capacitances C1 and C2 were 220 nF. The Agilent Technology DSOX 1102G oscilloscope was used for supplying the sinusoidal input signal and measuring the output waveforms. The transconductances 1 = 2 = 3 = 4 = 5 = 1.51 mS were designed to obtain the mixed-mode filter with the natural frequency of 1.09 kHz and the quality factor of 1 ( ≅ 1). Figures 17a,  18a, 19a and 20a show the experimental frequency responses of the LP, HP, BP, and BS responses of the VM, CM, TAM, and TIM filters, respectively. Figures 17b, 18b, 19b and  20b show the experimental frequency response of magnitude and phase characteristics of the AP responses of the VM, CM, TAM, and TIM filters, respectively. To measure the frequency responses of TAM filter, a resistor was used to convert the output current to volt- For measurement setup, the supply voltage was ±5 V and the capacitances C 1 and C 2 were 220 nF. The Agilent Technology DSOX 1102G oscilloscope was used for supplying the sinusoidal input signal and measuring the output waveforms. The transconductances g m1 = g m2 = g m3 = g m4 = g m5 = 1.51 mS were designed to obtain the mixed-mode filter with the natural frequency of 1.09 kHz and the quality factor of 1 (Q ∼ = 1). Figures 17a, 18a, 19a and 20a show the experimental frequency responses of the LP, HP, BP, and BS responses of the VM, CM, TAM, and TIM filters, respectively. Figures 17b, 18b, 19b and 20b show the experimental frequency response of magnitude and phase characteristics of the AP responses of the VM, CM, TAM, and TIM filters, respectively. To measure the frequency responses of TAM filter, a resistor was used to convert the output current to voltage, and the voltage according to this resistance was calculated to the output current for plotting. In case of CM and TIM filters, the high resistances (i.e., R in 662 Ω) were used to convert the input voltage to the input current at input terminals and convert the output current to the output voltage output terminals. The voltage according to the resistances was calculated as currents for plotting.     The experimental frequency responses of the BP response of the VM filter with different transconductances (g m = 0.48 mS, 0.87 mS, 1.51 mS, and 2.93 mS) are shown in Figure 21. This result was used to confirm that the proposed mixed-mode filter provides an electronic tuning ability without drubbing the quality factor. The Experimental setup of the universal filter is shown in Figure S1 in the Supplementary Materials. This result was used to confirm that the proposed mixed-mode filter provides an electronic tuning ability without drubbing the quality factor. The Experimental setup of the universal filter is shown in Figure S1 in the Supplementary Materials.   This result was used to confirm that the proposed mixed-mode filter provides an electronic tuning ability without drubbing the quality factor. The Experimental setup of the universal filter is shown in Figure S1 in the Supplementary Materials.

Conclusions
A new mixed-mode universal filter using five DDTAs and two grounded capacitors was shown in this paper. The proposed filter offers 36 filtering responses into a single