0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator

This paper presents the extremely low-voltage supply of the CMOS structure of a differential difference transconductance amplifier (DDTA). With a 0.3-volt supply voltage, the circuit offers rail-to-rail operational capability. The circuit is designed for low-frequency biomedical and sensor applications, and it consumes 357.4 nW of power. Based on two DDTAs and two grounded capacitors, a voltage-mode universal filter and quadrature oscillator are presented as applications. The universal filter possesses high-input impedance and electronic tuning ability of the natural frequency in the range of tens up to hundreds of Hz. The total harmonic distortion (THD) for the band-pass filter was 0.5% for 100 mVpp @ 84.47 Hz input voltage. The slight modification of the filter yields a quadrature oscillator. The condition and the frequency of oscillation are orthogonally controllable. The frequency of oscillation can also be controlled electronically. The THD for a 67 Hz oscillation frequency was around 1.2%. The circuit is designed and simulated in a Cadence environment using 130 nm CMOS technology from United Microelectronics Corporation (UMC). The simulation results confirm the performance of the designed circuits.


Introduction
In recent years, extremely low-voltage operation capability and low-power consumption became inevitable requirements in modern, battery-operated, portable electronics and self-powered systems. In modern nanoscale complementary metal-oxide-semiconductor (CMOS) technologies, scaling the power supply voltage sustains the reliability and performance improvement of digital circuits; however, it causes performance degradation in the analog part. This poses a continual challenge for analog circuit designers to maintain acceptable performance for applications and systems-on-chip. The main impact of reducing the voltage supply on analog circuit performance, such as an operational amplifier (Op-Amp) or transconductance amplifier (TA or OTA), is the reduced input voltage swing, the transconductance value, and the voltage gain. A conventional design technique used to increase the input voltage swing is rail-to-rail circuits composed of both PMOS and NMOS differential pairs. However, these circuits are complex due to the additional differential pair, current branches, and circuitry used to maintain constant transconductance over the whole input voltage range. Therefore, non-conventional techniques, such as bulk-driven (BD) [1][2][3][4][5][6][7][8][9][10][11][12][13][14], floating-gate (FG), and quasi-floating-gate (QFG) [15,16], are suitable candidates for circuits operating with low supply voltages. They may reduce the threshold voltage or even remove it from the signal path, resulting in an extended input voltage range. Multiple-input MOS transistor (MI-MOST) is an alternative technique to the FG. However, unlike the FG, the MI-MOST: (a) does not need two polysilicon technologies; hence, it can be implemented in any standard CMOS technology; (b) it can process both AC and DC signals; and (c) there is no gate floating, and hence no issue associated with removing the initial charge trapped as in the case of FG. The multiple-input can be applied to the gate, to the bulk, or to their combination [17][18][19][20][21][22][23][24][25][26][27]. From the realization point of view, analog filter applications with MI-MOST may reduce the count of needed active devices [17][18][19][20][21][22][23][24]28,29]. This leads to simplified filter circuitry and reduced power consumption and chip area.
The universal filter and oscillator are important blocks for analog signal processing. Their applications include communication, control, and instrumentation systems [30][31][32]. Biquadratic filters and oscillators can be applied to biomedical systems [33][34][35]. Therefore, low-voltage supply and low-power consumption are mainly considered for these applications.
The differential difference transconductance amplifier (DDTA) is a useful analog block for filter applications [36][37][38][39][40]. It combines the features of a differential difference amplifier (DDA) with unity gain, like addition and subtraction voltage ability, high-input impedance, a low number of components, and the advantages of a operational transconductance amplifier (OTA), such as electronic tuning ability and simple circuitry. There are DDTA-based universal filters and oscillators available in the literature [36][37][38][39][40]. However, these DDTAs are not suitable for extremely low-voltage supply (i.e., ≤0.3 V) applications. Their structures are standard; hence, reducing their voltage supply leads to significant performance degradation, for instance a reduced input voltage swing. Focusing on recently published universal filters and/or oscillators [41][42][43][44][45][46][47], only the circuit in [48] can work with sub-volt supply (±0.3 V) and low-power consumption (5.77 µW).
Therefore, this paper presents an innovative CMOS structure for DDTA capable of working under a 0.3 V supply voltage with a rail-to-rail input voltage swing without degrading the other circuit's performance. As an application of DDTA, a multiple-input, multiple-output (MIMO) universal filter is presented. The filter employs two DDTAs and two grounded capacitors. A variety of filter responses can be obtained by suitably applying the input signal and suitably choosing the output terminal. The natural frequency of filter responses can be electronically controlled. The proposed universal filter has also been modified to work as a quadrature oscillator. The frequency of oscillation can be controlled electronically. The proposed universal filter and quadrature oscillator can be applied to biomedical and sensor systems due to their extremely low voltage supply and low power consumption. This paper is organized as follows: In Section 2, the DDTA and its innovative CMOS structure are presented; Section 3 presents its application in the voltage-mode universal filter and the quadrature oscillator; Section 4 presents the simulation results; and Section 5 concludes the paper.

DDTA and Its CMOS Structure
The symbol of the DDTA is shown in Figure 1. In the ideal case, this active component is described by the following equations: The CMOS structure of the proposed DDTA is shown in Figure 2. The circuit consists of two main blocks, namely, the differential-difference amplifier operating in a unity feedback configuration, thus forming a differential-difference current conveyor (DDCC), and the transconductance amplifier (TA). Both circuits are based on non-tailed differential amplifiers [1], which allow for operation in an ultra-low-voltage environment with rail-torail input swing.  The CMOS structure of the proposed DDTA is shown in Figure 2. The circuit consists of two main blocks, namely, the differential-difference amplifier operating in a unity feedback configuration, thus forming a differential-difference current conveyor (DDCC), and the transconductance amplifier (TA). Both circuits are based on non-tailed differential amplifiers [1], which allow for operation in an ultra-low-voltage environment with rail-torail input swing. The DDCC block consists of two stages, the input differential amplifier, M1-M6, and the class-A output stage, M9-M10. The capacitance CC is used for frequency compensation. Its value can be calculated in the same way as that for a two-stage operational amplifier. The input stage of the DDCC circuit can be seen as a non-tailed differential pair with an additional partial positive feedback (PPF) circuit. The solution, first presented in [2] and experimentally validated in [3], has been adopted here. The transistors, M7 and M8, generate negative conductances, -gm7 and -gm8, which partially compensate for the positive conductances of the diode-connected transistors, M2A,B (≈gm2), thus increasing the resistances at the gate-drain nodes of these transistors, and consequently the voltage gain from inputs to the gate terminals of M1A,B. This improves the overall transconductance and voltage gain of the first stage.
In the proposed realization, the input transistors M1A,B have been replaced by bulkdriven MI-MOST transistors. The symbol and CMOS realization of these devices are shown in Figure 3. This approach allows design simplification and the decreasing of the total dissipation power by removing one differential stage of the conventional DDCC. This is the result of the fact that summation of input signals is realized using the passive voltage divider/summing circuit composed of the capacitances CBi (see Figure 3b). The capacitances are shunted by large resistances, RMOSi, that allow proper DC biasing of the bulk terminals of M1A,B. The resistors are realized as the antiparallel connection of two MOS transistors operating in a cutoff region, as shown in Figure 3c.  The CMOS structure of the proposed DDTA is shown in Figure 2. The circuit consists of two main blocks, namely, the differential-difference amplifier operating in a unity feedback configuration, thus forming a differential-difference current conveyor (DDCC), and the transconductance amplifier (TA). Both circuits are based on non-tailed differential amplifiers [1], which allow for operation in an ultra-low-voltage environment with rail-torail input swing. The DDCC block consists of two stages, the input differential amplifier, M1-M6, and the class-A output stage, M9-M10. The capacitance CC is used for frequency compensation. Its value can be calculated in the same way as that for a two-stage operational amplifier. The input stage of the DDCC circuit can be seen as a non-tailed differential pair with an additional partial positive feedback (PPF) circuit. The solution, first presented in [2] and experimentally validated in [3], has been adopted here. The transistors, M7 and M8, generate negative conductances, -gm7 and -gm8, which partially compensate for the positive conductances of the diode-connected transistors, M2A,B (≈gm2), thus increasing the resistances at the gate-drain nodes of these transistors, and consequently the voltage gain from inputs to the gate terminals of M1A,B. This improves the overall transconductance and voltage gain of the first stage.
In the proposed realization, the input transistors M1A,B have been replaced by bulkdriven MI-MOST transistors. The symbol and CMOS realization of these devices are shown in Figure 3. This approach allows design simplification and the decreasing of the total dissipation power by removing one differential stage of the conventional DDCC. This is the result of the fact that summation of input signals is realized using the passive voltage divider/summing circuit composed of the capacitances CBi (see Figure 3b). The capacitances are shunted by large resistances, RMOSi, that allow proper DC biasing of the bulk terminals of M1A,B. The resistors are realized as the antiparallel connection of two MOS transistors operating in a cutoff region, as shown in Figure 3c. The DDCC block consists of two stages, the input differential amplifier, M 1 -M 6 , and the class-A output stage, M 9 -M 10 . The capacitance C C is used for frequency compensation. Its value can be calculated in the same way as that for a two-stage operational amplifier. The input stage of the DDCC circuit can be seen as a non-tailed differential pair with an additional partial positive feedback (PPF) circuit. The solution, first presented in [2] and experimentally validated in [3], has been adopted here. The transistors, M 7 and M 8 , generate negative conductances, -g m7 and -g m8 , which partially compensate for the positive conductances of the diode-connected transistors, M 2A,B (≈g m2 ), thus increasing the resistances at the gate-drain nodes of these transistors, and consequently the voltage gain from inputs to the gate terminals of M 1A,B . This improves the overall transconductance and voltage gain of the first stage.
In the proposed realization, the input transistors M 1A,B have been replaced by bulkdriven MI-MOST transistors. The symbol and CMOS realization of these devices are shown in Figure 3. This approach allows design simplification and the decreasing of the total dissipation power by removing one differential stage of the conventional DDCC. This is the result of the fact that summation of input signals is realized using the passive voltage divider/summing circuit composed of the capacitances C Bi (see Figure 3b). The capacitances are shunted by large resistances, R MOSi , that allow proper DC biasing of the bulk terminals of M 1A,B . The resistors are realized as the antiparallel connection of two MOS transistors operating in a cutoff region, as shown in Figure 3c. The low-frequency open-loop voltage gain of the DDCC, from one differential input, with the second input grounded for AC signals, can be expressed as follows: where Gm is the transconductance of the input differential stage given by: The low-frequency open-loop voltage gain of the DDCC, from one differential input, with the second input grounded for AC signals, can be expressed as follows: where G m is the transconductance of the input differential stage given by: where β is the voltage gain of the input capacitive divider, equal to 1 2 if all capacitances C Bi are equal to each other and the input capacitance of the MOS transistor from its bulk terminal can be neglected. The factor m represents the absolute value of the ratio of negative to positive conductances at the gate/drain nodes of M 2A,B : Note that the transconductance G m as well as the voltage gain A vo tend to infinity, as m tends to unity, namely, when the negative conductances generated by M 7 and M 8 fully compensate the positive conductances of M 2 , thus leading to infinite voltage gain from inputs to the drain/gate nodes of M 2A,B . However, when the difference between g m2 and g m7,8 is decreasing, namely when m is increasing to unity, then the circuit sensitivity to transistor mismatch is increasing as well, which limits the maximum value of m. The second limitation is associated with the location of the parasitic pole associated with the PPF circuit, which is given by the formula where C ∑ is the total capacitance associated with the gate/drain nodes of M 2A,B . Note that the frequency of this pole decreases with increasing m, namely, as the total resistance at the gate/drain nodes of M 2 increases with increasing positive feedback. For stable operation, the pole should be located well above the GBW product of the internal DDA, which is In view of the above considerations, the output signal at the W terminal for low frequencies can be expressed as Note that accuracy of this function is improved thanks to the impact of the PPF, which enlarges the low-frequency voltage gain A vo . The 3 dB frequency of this function is approximately equal to ω GBW . The low-frequency output resistance at the W terminal is given as follows: Thus, the resistance r outW is also improved (decreased) thanks to the larger value of A vo .
The second block of the proposed DDTA is the linear transconductance amplifier, TA. The circuit applied here was first proposed and validated experimentally in [4]. It can be considered as a non-tailed BD pair [1], linearized with an additional linear resistance R, which significantly improves the linearity of the circuit. Thanks to its non-tailed architecture, the circuit can operate from a very low-voltage supply.
Assuming that transistor M B is identical with M 3 and M 4 , the DC transfer characteristic of the TA in Figure 2 can be described by the formula [4]  (10) and n p is the subthreshold slope factor for a p-channel MOS, U T is the thermal potential, and η = (n p − 1) = g mb1,2 /g m1,2 is the bulk-to-gate transconductance ratio for transistors M 1 and M 2 .
As it was shown in [4], if the following condition holds then the circuit exhibits an optimum linearity. However, even for the non-optimal case, the linearity of Equation (9) is much better than for the original circuit without the resistance, R; therefore, the TA can be tuned using the current source I set , while still maintaining good linearity of its transfer characteristic. The small-signal transconductance g m of the TA in the general case is thus, in the optimum case, (R = 1/g m1,2 ), it is equal to 4g mb1,2 /3. Figure 4 shows the proposed voltage-mode MIMO universal filter. The topology employs two DDTAs and two grounded capacitors. The terminals V in1 , V in2 , V in3 , V in4 , and V in5 provide high-input impedances, and the terminals V o1 and V o3 low-output impedances, whereas the terminals V o2 and V o4 require external buffer circuits if a low-impedance load is applied.  Using (1) and nodal analysis, the output voltages of Figure 4 can be expressed as follows: Using (1) and nodal analysis, the output voltages of Figure 4 can be expressed as follows:

Proposed Universal Filter
From (14)- (17), the low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS), and all-pass (AP) responses can be obtained by properly applying the input signal and choosing the output terminals as shown in Table 1. The input terminals that are not used should be connected to ground. In the case of the all-pass filtering response, the circuit requires an inverting-type input signal, which can be obtained using additional DDTA.
The natural frequency (ω o ) and the quality factor (Q) of the filter can be respectively expressed as From (18) and (19), the natural frequency and the quality factor can be designed, as the quality factor can be given by C 1 /C 2 by letting g m1 = g m2 whereas the natural frequency can be obtained electronically by adjusting g m (g m = g m1 = g m2 ).

Filtering Function
Input Output

Proposed Quadrature Oscillator
The proposed universal filter in Figure 4 was modified to work as a quadrature oscillator as shown in Figure 5. It can be obtained by using a non-inverting BP filtering response and a feedback connection. Using (14), the transfer function between V o1 and V in3 can be expressed as follows:  Thus, the CO of the oscillator can be controlled by 1 and/or 2 , and letting 1 = 2 , the FO can be controlled electronically by ( = 1 = 2 ). Therefore, the FO and CO of the oscillator can be orthogonally controlled. The nodes Vo3 and Vo4 provide quadrature output signals. It can be confirmed by the relationship between Vo3 and Vo4: Thus, the phase difference between Vo3 and Vo4 is 90°. After setting s = jω0 into (24) and taking into account Equations (22) and (23) and the condition gm1 = gm2, the ratio (24) is one; thus, if oscillation condition (22) is accomplished, the oscillator provides equal amplitudes of both quadrature signals independently of the oscillation frequency.

Non-Idealities Analysis
Considering non-idealities of the DDTA, (1) can be rewritten as: where 1 denotes the voltage gain from 1 to of -th DDTA, 2 denotes the voltage gain from 2 to of -th DDTA, and 3 denotes the voltage gain from 2 to of -th DDTA. Ideally, the voltage gains 1 , 2 , and 3 are unity. The is the nonideal transconductance gain of the DDTA, whose frequency dependence is given by parasitic capacitance Co and resistance Ro at o-terminal. In the frequency range near the cutoff frequency, can be approximated as [48] ( ) ≅ (1 − ) where = 1⁄ , denotes the first-order pole. Using (25), the output voltages of Figure 4 can be rewritten to the form  Letting V o1 /V in3 = 1, the oscillator characteristic can be derived as Letting g m1 = g m2 = g m , the condition of oscillation (CO) is and the frequency of oscillation (FO) is Thus, the CO of the oscillator can be controlled by C 1 and/or C 2 , and letting g m1 = g m2 , the FO can be controlled electronically by g m (g m = g m1 = g m2 ). Therefore, the FO and CO of the oscillator can be orthogonally controlled. The nodes V o3 and V o4 provide quadrature output signals. It can be confirmed by the relationship between V o3 and V o4 : Thus, the phase difference between V o3 and V o4 is 90 • . After setting s = jω 0 into (24) and taking into account Equations (22) and (23) and the condition g m1 = g m2 , the ratio (24) is one; thus, if oscillation condition (22) is accomplished, the oscillator provides equal amplitudes of both quadrature signals independently of the oscillation frequency.

Non-Idealities Analysis
Considering non-idealities of the DDTA, (1) can be rewritten as: where β i1 denotes the voltage gain from V y1 to V w of i-th DDTA, β i2 denotes the voltage gain from V y2 to V w of i-th DDTA, and β i3 denotes the voltage gain from V y2 to V w of i-th DDTA. Ideally, the voltage gains β i1 , β i2 , and β i3 are unity. The g mni is the non-ideal transconductance gain of the DDTA, whose frequency dependence is given by parasitic capacitance C o and resistance R o at o-terminal. In the frequency range near the cutoff frequency, g mni can be approximated as [48] g mni (s) where µ i = 1/ω gmi , ω gi denotes the first-order pole.
Using (25), the output voltages of Figure 4 can be rewritten to the form −(sC 1 g mn2 + g mn1 g mn2 β 21 )V in5 s 2 C 1 C 2 + sC 2 g mn1 β 21 + g mn1 g mn2 β 12 β 21 (30) Considering the denominator D(s) of (27)-(30), the modified parameters ω o and Q can be expressed by: From (27), the modified oscillator characteristic can be expressed as The modified CO and FO of the oscillator are then Since this work is focused on circuits that operate at low frequency, Equation (26) is not taken in consideration. In the case that the universal filter and the quadrature oscillator operate in the frequency range in which the frequency dependence of g m asserts its influence, then (26) should be used to refine the error analysis.

Simulation Results
The DDTA circuit and its applications were designed in a Cadence environment, using 130 nm CMOS technology from UMC. The transistor's aspect ratio and values of passive devices are included in Table 2  The open-loop gain of the DDCC (i.e., without the unity gain feedback) was simulated as 73.9 dB, and the phase margin was 56.2 • for 20 pF load capacitor. The simulated magnitude characteristics of the DDCC are shown in Figure 6. The low-frequency gain for V W /V Y1 (=V W /V Y3 ) and V W /V Y2 is 14 mdB and 57.29 mdB, while the −3 dB bandwidth is 22.24 kHz and 22.23 kHz, respectively.  The simulated DC transfer characteristics of the DDCC are shown in Figure 7. As is evident, the DDCC enjoys rail-to-rail operation for all its inverting and non-inverting inputs. This rail-to-rail operation capability is a design achievement. The simulated DC transfer characteristics of the DDCC are shown in Figure 7. As is evident, the DDCC enjoys rail-to-rail operation for all its inverting and non-inverting inputs. This rail-to-rail operation capability is a design achievement.
The simulated gain and phase characteristics for the TA with I set = 0.5 µA and 20 pF load capacitance are shown in Figure 8. The low DC gain is 23.2 dB, and the bandwidth (BW) is 19.65 kHz, while the phase error is 3.8 • . Figure 9a,b shows the DC characteristic of the output current and the transconductance versus fully differential input voltage V in (V in = V + − V y4 ) for the TA for I set = 0.125 µA, 0.25 µA, and 0.5 µA. The rail-to-rail operation with high linearity is evident. The simulated DC transfer characteristics of the DDCC are shown in Figure 7. As is evident, the DDCC enjoys rail-to-rail operation for all its inverting and non-inverting inputs. This rail-to-rail operation capability is a design achievement.    The simulated DC transfer characteristics of the DDCC are shown in Figure 7. As is evident, the DDCC enjoys rail-to-rail operation for all its inverting and non-inverting inputs. This rail-to-rail operation capability is a design achievement. The simulated gain and phase characteristics for the TA with Iset = 0.5 µ A and 20 pF load capacitance are shown in Figure 8. The low DC gain is 23.2 dB, and the bandwidth (BW) is 19.65 kHz, while the phase error is 3.8°.   To determine the impact of mismatch and process variation on the circuit's performance, Monte Carlo (MC) simulations (200 runs) were carried out. As the histograms show in Figure 10, the impact of mismatch and process variation on the gain and −3 dB BW of the DDCC is low. The impact is also low on the gain and phase error of the TA as shown in Figure 11. To determine the impact of mismatch and process variation on the circuit's performance, Monte Carlo (MC) simulations (200 runs) were carried out. As the histograms show in Figure 10, the impact of mismatch and process variation on the gain and −3 dB BW of the DDCC is low. The impact is also low on the gain and phase error of the TA as shown in Figure 11.
The process, voltage, temperature (PVT) corners analysis was also provided on the proposed DDTA. The MOS transistor corners were slow-slow, slow-fast, fast-slow, and fast-fast, the voltage supply corners were (V DD − V SS ) ± 10%, and the temperature corners were −20 • C and 70 • C. Tables 3 and 4 show the results of the minimum, nominal, and maximum values of the gain, −3 dB BW for the DDCC, and gain and phase error for the TA. The impact of the PVT corners in all cases is acceptable.  To determine the impact of mismatch and process variation on the circuit's performance, Monte Carlo (MC) simulations (200 runs) were carried out. As the histograms show in Figure 10, the impact of mismatch and process variation on the gain and −3 dB BW of the DDCC is low. The impact is also low on the gain and phase error of the TA as shown in Figure 11.    The process, voltage, temperature (PVT) corners analysis was also provided on the proposed DDTA. The MOS transistor corners were slow-slow, slow-fast, fast-slow, and fast-fast, the voltage supply corners were (VDD − VSS) ± 10%, and the temperature corners were −20 °C and 70 °C. Tables 3 and 4 show the results of the minimum, nominal, and maximum values of the gain, −3 dB BW for the DDCC, and gain and phase error for the TA. The impact of the PVT corners in all cases is acceptable.  The universal filter in Figure 4 was simulated for C 1 = C 2 = 5 nF, which are off-chip capacitors. The magnitude characteristics of the LPF, HPF, BPF, BSF, and APF are shown in Figure 12. The simulated natural frequency (f o ) is around 81.47 Hz. It is worth mentioning that, due to the limited value of the output resistance of the TA, which is around 5.1 MΩ, the attenuations of the HPF and BPF are degraded at low frequencies. Therefore, if an application demands higher attenuation, then the output resistance could be increased, employing the MOS transistor self-cascode technique.  The universal filter in Figure 4 was simulated for C1 = C2 = 5 nF, which are off-chip capacitors. The magnitude characteristics of the LPF, HPF, BPF, BSF, and APF are shown in Figure 12. The simulated natural frequency (fo) is around 81.47 Hz. It is worth mentioning that, due to the limited value of the output resistance of the TA, which is around 5.1 MΩ, the attenuations of the HPF and BPF are degraded at low frequencies. Therefore, if an application demands higher attenuation, then the output resistance could be increased, employing the MOS transistor self-cascode technique. The BPF was tested by applying a sine wave signal Vin = 100 mVpp @ 81.47 Hz. The waveforms of the input and output voltages are shown in Figure 13a. The spectrum of the output signal is shown in Figure 13b, where the total harmonic distortion (THD) of the BPF output is 0.5%. The BPF was tested by applying a sine wave signal V in = 100 mV pp @ 81.47 Hz. The waveforms of the input and output voltages are shown in Figure 13a. The spectrum of the output signal is shown in Figure 13b, where the total harmonic distortion (THD) of the BPF output is 0.5%. 1 The BPF was tested by applying a sine wave signal Vin = 100 mVpp @ 81.47 Hz. The waveforms of the input and output voltages are shown in Figure 13a. The spectrum of the output signal is shown in Figure 13b, where the total harmonic distortion (THD) of the BPF output is 0.5%.  The simulation results showing the start of the oscillation and the steady state of the quadrature oscillator from Figure 5 are given in Figure 15. The oscillation frequency is 67 Hz, and the THD for outputs V 3 and V 4 are 1.2% and 1.29%, respectively. The simulation results showing the start of the oscillation and the steady state of the quadrature oscillator from Figure 5 are given in Figure 15. The oscillation frequency is 67 Hz, and the THD for outputs V3 and V4 are 1.2 % and 1.29 %, respectively. Finally, Table 5 provides the comparison of the proposed filter with others in the literature [23,41,42,44,46,47]. It is evident that the proposed filter offers the highest number of filtering functions with lowest power supply and power consumption, thanks to the innovative CMOS structure of the DDTA.  Finally, Table 5 provides the comparison of the proposed filter with others in the literature [23,41,42,44,46,47]. It is evident that the proposed filter offers the highest number of filtering functions with lowest power supply and power consumption, thanks to the innovative CMOS structure of the DDTA.

Conclusions
This paper presents an innovative structure of a DDTA capable of operating under an extremely low voltage supply of 0.3 V while offering a rail-to-rail input voltage swing. As an application, a universal filter and quadrature oscillator based on two DDTAs and two grounded capacitors are presented. The simulation results including Monte Carlo and PVT analysis confirm the good functionality of the proposed circuits.