An Impedance Readout IC with Ratio-Based Measurement Techniques for Electrical Impedance Spectroscopy

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 μW for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1°, respectively.


Introduction
Electrical or electrochemical impedance spectroscopy (EIS) is an analytical technique measuring the target impedance over a frequency range. It is widely used in a variety of applications, including ischemia detection [1][2][3], glucose sensing [4], lung monitoring [5,6], DNA analysis [7,8], common allergens detection [9], food pathogen detection [10], and battery monitoring [11]. This technique also has been applied to the early detection of cancers such as cervical cancer [12], prostate cancer [13,14], skin cancer [15], colorectal cancer [16], and breast cancer [17,18]. Since EIS allows for noninvasive, low-cost, effective monitoring of the target impedance with a small form factor [19][20][21], wearable implementation for the aforementioned applications would be greatly beneficial. For that purpose, it is important to design a robust, low-power circuit architecture for impedance measurements. Figure 1 shows an overall block diagram of the EIS system composed of a current generator and a readout integrated circuit (IC). The current generator typically consists of a signal generator, which creates a sinusoidal voltage waveform with variable frequencies, and a voltage-controlled current source (VCCS), which converts the voltage waveform into a current [22,23]. The current is applied across the target material, which has a complex impedance. The measurement IC typically amplifies the measured voltage signal across the target material by an instrumentation amplifier (IA) and then uses its demodulator to obtain the impedance information.  Figure 2 shows two impedance measurement structures with and without a reference resistor, respectively. In both structures, the VCCS transforms the input voltage signal, v in (t), to the output current signal, i in (t). Then, i in (t) is applied to the material, and the resulting voltage, V m (t), is measured. In the most basic structure shown in Figure 2a, i in (t) flows through the target impedance only. Inherently, the VCCS incurs delay and nonlinearity on i in (t), resulting in an error in the final measurement result. In order to solve this problem, a reference resistor can be added in series with the target impedance, as shown in Figure 2b ( [24]). The same i in (t) flows through both the target impedance and reference resistor together, generating two voltage outputs, v m (t) and v r (t). Since the impedance of resistors has a zero phase, the voltage signal across the reference resistor, v r (t), has the same phase as i in (t). Thus, v r (t) can serve as a reference of the phase and magnitude measurements, so the effects from the delay or nonlinearity of the VCCS can be avoided. Despite the advantages of the reference resistor, the conventional I/Q demodulators, which require quadrature signal generation, are mostly based on the structure of Figure 2a [17,20,[25][26][27]. As shown in Figure 3a, the I/Q demodulator structure obtains the real component of the target impedance by mixing the signal from the target impedance with v in (t) and the imaginary component by mixing it with a signal that is 90 • -phase-shifted from v in (t) [17,20,[25][26][27]. Since only the signal corresponding to the frequency of v in (t) is converted to the DC value, it is insensitive to noises at other frequencies. However, it requires the 90 • -shifted (quadrature) signal for variable frequencies. In order to utilize the reference resistor, it is necessary to delay the signal from the reference resistor by the time interval corresponding to 90 • of phase for variable frequencies in the demodulator. So, additional complex techniques with considerable hardware and power overhead should be used, such as an oversampling mixer employing an eight-phase local oscillator [28], direct digital synthesis (DDS) block [29], a large-area passive network [30], or an edge detector, which requires a 50-times-faster clock [17]. To avoid this complexity, the I/Q demodulator receives the 90 • -shifted signal from the current generator instead of the reference resistor. However, this makes the structure vulnerable to the phase error between v in (t) and the IA output caused by the delay of the VCCS and IA. Therefore, for high measurement accuracy, a phase-correction circuit is needed [31,32], inducing another power overhead and design complexity.
On the other hand, the polar demodulator structure is suitable for using the reference resistor. It measures the magnitude and phase components by using the measurements of both v m (t) and v r (t). Various magnitude measurement techniques have been demonstrated, such as adaptive sampling [32,33], peak detecting [34], and time-stamping schemes [35]. Among them, one of the most commonly used methods is the one based on a self-mixing full-wave rectifier, as shown in Figure 3b [24]. Since it does not suffer from the delays of the amplifier and VCCS, this method is robust over a wide frequency range compared to the other structures. On the contrary, the phase measurement in the polar structure typically requires complex and power-hungry circuit blocks to cover a wide frequency range [24,[32][33][34]. Figure 4 shows the phase-detection process when using a time-to-digital converter (TDC) or an integrator to measure the phase difference between v m (t) and v r (t). φ r (t) and φ m (t) are the zero-crossing comparison results of v r (t) and v m (t), respectively. By mixing φ r (t) and φ m (t), typically using an XNOR gate, φ p (t) is created. Then, the duty ratio of φ p (t) corresponds to the phase difference, and the pulse width of φ p (t) should be quantified. Since the pulse width of φ p (t) varies inversely proportional to the input frequency for the same phase difference, the comparator must cover a wide frequency range. When an integrator is used to measure the pulse width, it must quickly integrate φ p (t) with a large current to support high frequencies [36,37]. This fast integration, however, causes saturation of the integrator output at low frequencies, as shown in Figure 4b. In order to cover a wide frequency range without saturation, it is necessary to use a high-resolution analog-to-digital converter, resulting in high power consumption. When a TDC is used to measure the pulse width, it requires a high-speed clock to operate at high frequencies, thus increasing power consumption.
Alternatively, a low-pass filter (LPF) can be used to reduce power consumption and avoid design complexity [38]. It creates a DC value by averaging the signal φ p (t) regardless of the frequency. The DC output is proportional to the pulse width and hence to the phase of the target impedance. Due to its simplicity, this has been widely used not only for the phase measurement in this structure but also for the real, imaginary, and magnitude measurements in various architectures. Although the LPF can easily support a wide frequency range with low power consumption, it suffers from a long settling time, significantly slowing down the measurement speed. In this paper, we present an impedance readout IC that measures the real part and magnitude of the target impedance using a ratio-based detection technique. The proposed IC is based on the polar demodulator with the reference resistor, making the system robust to the errors originating from nonidealities of the VCCS. Whereas other polar demodulators measure the magnitude and phase, inherently suffering from complex circuits, high power consumption, and/or the throughput problem, the proposed one measures the magnitude and real component instead. The magnitude is obtained using a self-mixing full-wave rectifier to make it less susceptible to the delay of the IA. For the real-component measurement, another mixing process is performed in the magnitude measurement path. In this process, the signal from the target impedance is mixed with the signal from the comparator and IA connected to the reference resistor. Because the same IA is shared in this path, the IA's nonlinearity can be cancelled out. This also relaxes the bandwidth requirement of the IA, reducing the overall power consumption. Moreover, this architecture allows for obtaining the final impedance result by using the ratio of the results obtained in the paths, significantly improving the robustness and throughput. As a result, the proposed IC can easily achieve low power consumption and support a wide frequency range with low circuit complexity while providing fast settling.
The rest of the paper is organized as follows. The overall architecture of the proposed IC is explained in Section 2, and the detailed implementation is described in Section 3. Section 4 shows the simulation results, and Section 5 concludes the paper. Figure 5a shows the overall architecture of the proposed impedance readout IC consisting of two IAs, three passive mixers, two comparators and three LPFs to produce three final outputs (V mag , V re , and V mag,r ). These circuit blocks form two magnitude measurement paths (Mag-paths) for V mag and V mag,r and one real-component measurement path (Realpath) for V re . The sinusoidal input current signal (i in (t)), which is driven by the VCCS, flows through the target impedance (Z m ) and reference resistor (R REF ). The voltage signals across Z m and R REF (v m (t) and v r (t), respectively) are applied to the input of the readout IC. These voltages are expressed as:

Proposed Architecture
where A in is the amplitude of the IA, f in the frequency of i in (t), θ m the phase of Z m , and θ VCCS the phase error in the VCCS. These two signals are amplified by the two identical IAs and converted into square-wave signals, φ m (t) and φ r (t), by two zero-crossing comparators, as shown in Figure 5b. φ m (t) and φ r (t) correspond to the phase information of each signal. The amplified v m (t) and v r (t) pass through buffers, which replicate the delay in φ m (t) and φ r (t) by the comparators. These sinusoidal signals are mixed with φ m (t) and φ r (t) in the mixers. The buffers also reduce the kick-back noise from the mixer output to the comparator and IA. The resulting voltage signals from the demodulation, v mag (t), v re (t), and v mag,r (t), go through LPFs, generating the DC voltages, V mag , V re , and V mag,r . These DC outputs represent the magnitude and real part of the target impedance, and the magnitude of the reference resistor, respectively.

Magnitude Measurement Path
The magnitude information from Z m and R REF is extracted by two Mag-paths, composed of identical circuit components, as shown in Figure 5a. After v m (t) is amplified, the signal is processed by the comparator, producing φ m (t), which periodically repeats the values of V DD (= 1.8 V) and 0 V. A chopper switches the polarity of v m (t) when φ m (t) toggles. As a result, the chopper mixes the amplified v m (t) and φ m (t), generating v mag (t). The rectified signal, v mag (t), can be expressed as follows: where θ I A 1 , θ B 1 , and θ C 1 are the phase delays of the IA 1 , buffer, and comparator in the Z m Mag-path, respectively. The equation does not include the mixing results between v m (t) and the harmonics of φ m (t) because they are located at high frequencies and will be filtered out easily by the LPF. In addition, the second term located at the second harmonic frequency (cos(4π f in t + 2θ VCCS + 2θ I A1 + θ B + θ C1 + 2θ m )) is filtered out by the subsequent LPF. Then, the DC term of |Z m |A in A I A1 cos(θ C1 − θ B1 )/2 only remains after being multiplied by 2/π. Thus, the final output is a DC value expressed as: Note that V mag does not include the error terms related to θ VCCS and θ I A1 , which are cancelled out during the mixing operation. In addition, by adding the buffers between the IA and mixer and making θ C 1 and θ B 1 similar, the error caused by the comparator delay can be compensated. Now The magnitude value of the target impedance, |Z m |, can be found as: Note that |Z m | is not affected by phase delays of any circuit components. The equation still includes A in and A I A 1 , so |Z m | is affected by the nonlinearity and frequency response of the VCCS and IA like many other conventional impedance measurement circuits.
In our work, another Mag-path is added to achieve even higher accuracy and robustness. The R REF Mag-path is added to compensate for the nonlinearity of the VCCS and IA. In this path, the final output is produced using the same process as the Z m Mag-path. Then, V mag,r is given as: where θ B 2 and θ C 2 are the delays of the buffer and comparator in the R REF Mag-path, respectively. The final magnitude result, MAG(Z m ), is calculated by taking the ratio between the outputs from the two Mag-paths, which are described by Equations (3) and (6).
The error between the final magnitude result and actual impedance magnitude |Z m | can be found from the following equation: The error factor between the measured value (MAG(Z m )) and the actual value (|Z m |) , which is composed of ratios between circuit parameters of the two Mag-paths. It indicates that the magnitude measurement accuracy is only affected by the mismatch between the two Mag-paths instead of the nonlinearity and phase delays of the circuit components such as the VCCS, IAs, and comparators. Thanks to this ratio-based method, the proposed readout circuit becomes much less susceptible to the nonlinearity and gain-bandwidth variation of the VCCS and IA. In addition, the settling slope of the LPF output is similar in the two Mag-paths, so the ratio between V mag and V mag,r settles much faster than V mag or V mag,r themselves. This characteristic is explained and demonstrated in Section 4.

Real-Component Measurement Path
The real component of the target impedance can be obtained by demodulating v m (t) using φ r (t), which is derived from the reference resistor R REF , as shown in Figure 5a.
Assuming that the amplitude of the fundamental tone of φ r (t) is 1, the demodulated real component signal (v re (t)) is expressed as: where θ I A2 is the phase delay of IA 2 . In this equation, φ r (t) is assumed to be a pure-tone cosine waveform having the fundamental tone only, as in Equation (2). This is because the mixing results between v m (t) and the harmonics of φ m (t) are located at high frequencies and will be filtered out easily by the subsequent LPF. By low-pass filtering, the second term at 2 f in is filtered out, and only the DC term is left as: As shown in Equations (9) and (10), the VCCS delay is cancelled out by the mixing operation. In addition, the IA delays (θ I A 1 and θ I A 2 ) can also be cancelled out because IA 1 and IA 2 are identical, and their delays are close to each other. Thus, θ I A 1 and θ I A 2 are almost completely cancelled out each other as follows: The phase error term (θ B 1 − θ C 2 ) is also very small compared to θ m because the buffer is added to match the delay of the comparator. Thus, the equation can be written as: Based on this equation, Re[Z m ] can be found as: Similar to Equation (5), this result is prone to gain errors in the VCCS and IA because their gain terms are included in the calculation.
To address this issue, the final real-component result, RE(Z m ), can be obtained by using a ratio, as in Equation (7): As such, RE(Z m ) is calculated from the ratio between the two DC voltage outputs, multiplied by R REF . The deviation of RE(Z m ) from Re[Z m ] can be performed as follows: where θ e = θ B 1 − θ C 2 . As shown in Equation (15), the effects from the nonlinearity and delay of the VCCS and IA are canceled out.
The final phase measurement result, PH ASE(Z m ), can also be obtained from a ratio between the voltage outputs as follows: As shown in the equation, the phase output is affected by θ e , which is reduced by matching the comparator and buffer delays.
In the proposed impedance readout IC, the magnitude, real component, and phase of the target impedance are measured using ratio-based techniques. Thanks to this, the results are robust to the variations in circuit parameters. Moreover, the IAs do not need to have too wide bandwidths. The gain degradation of the IA at high frequencies is also compensated so that the IA can be designed to consume lower power.

Instrumentation Amplifier
As shown in Figure 6, the IAs consist of three op-amps, resistors, and capacitors including three reconfigurable capacitor banks (cap-banks). The first stage of the IA is composed of two differential-to-single-ended amplifiers while a fully differential amplifier is used for the second stage. Each cap-bank contains capacitors and switches, which are controlled by 4-bit digital words. By changing these capacitor values, the IA gain can be configured from 7 to 48.7 dB. The bandwidth of the IA is 225 kHz at the maximum gain mode, with gains of 41.4 dB and 41.9 dB at 10 Hz and 1 MHz, respectively. In the minimum gain mode, it has a bandwidth of 3.6 MHz, and the gains at 10 Hz and 1 MHz are 6.95 dB and 6.9 dB, respectively. Since the impedance measurement is performed by using the ratio between the magnitude and real values of the target impedance and R REF , even the 225-kHz IA bandwidth is sufficient to cover the 1 MHz input frequency range.  Figure 7 shows the detailed schematic diagrams of the first-and second-stage amplifiers. The first-stage amplifier is designed as a rail-to-rail folded-cascode amplifier to provide a wide input range and excellent stability when driving a large capacitor C 2 as a load. The two-stage op-amp shown in Figure 7b is used as the second-stage amplifier to support a large output swing range. It also employs a common-mode feedback to maintain the common-mode voltage stably.

Comparator
The comparator is implemented with the autozeroing scheme to remove the offset, as shown in Figure 8. To enhance the effect of the autozeroing technique, the comparator is designed as a single amplifier stage instead of cascading multiple stages of amplifiers. In addition, two Schmitt triggers are added after the comparator to make a glitch-free rectangular waveform. Two capacitors (C AZ ) and six switches are used for the autozeroing technique. In the first phase, the four S 1 switches are closed and the two S 2 switches are open. Then, the comparator offset is stored in the C AZ placed at the negative input of the comparator. This stored offset is used to cancel out the effect from the offset in the next phase when the S 2 switches are closed and the S 1 switches are open. Since the offset stored in C AZ discharges over time, it is important to perform the autozeroing periodically. The autozeroing can be performed in between each impedance measurement for different frequencies.  Thanks to the buffer, this delay is canceled out by the buffer delay (φ Bu f f er ). Figure 9b compares the delay of the comparator and the buffer as a function of the input amplitude. The comparator's delay varies over the input amplitude. As shown in the figure, the delay difference between the comparator and buffer is up to 7 ns, which is much smaller than the delay of the comparator of 14-25 ns. This reduces the phase error by more than 50%. To maximize the delay cancellation effect, the buffer is designed to have an average delay of the comparator delay. If the amplitude of the comparator input is 100-400 mV by configuring the gain of IA, the error is reduced to within 3.8 ns.  Figure 10 shows the schematic of the LPF. Four buffers are used to isolate the input and output signals, and they are implemented as the folded-cascode amplifier structure. The cut-off frequency of the LPF can be controlled by S LF1 and S LF2 switches to speed up the measurement time and reduce the ripple by sufficiently attenuating the high-frequency terms. R 1 , which has 10-times-greater resistance than R 2 , and C 2 , which has 100-timesgreater capacitance than C 1 , are used with these switches. There is also an additional switch, S 2 , which operates with the same clock for the autozeroing, to avoid additional settling time that occurs when C AZ stores the offset voltage.

Results
The proposed IC was designed in a TSMC 180 nm complementary metal-oxidesemiconductor (CMOS) process. As shown in Figure 5, simulations were performed by applying a sinusoidal current with the same amplitude (4 µA) to the target impedance and reference resistor for 11 points in the frequency range from 10 Hz to 1 MHz. The target impedance is based on a simplified cell model, which is composed of a 200 Ω resistor in series with a parallel combination of a 45 nF capacitor and a 5 kΩ resistor [24]. The R REF values of 500 Ω and 5 kΩ are used for the frequency ranges of 5 kHz-1 MHz and 10 Hz-5 kHz, respectively. The LPF cut-off frequency was adjusted so that the ripple was small enough for the applied frequency, and the IA gain was chosen according to the output DC value. Figure 11a,b shows the frequency response of the IA and the LPF. The IA covers the frequency from 30 Hz to 225 kHz for the maximum gain mode, and the frequency from 7 Hz to 3.7 MHz for the minimum gain mode, as shown in Figure 11a. In the simulation conducted using the impedance model, a gain mode of 33 dB was used up to 5 kHz, and a maximum gain mode was used for frequencies above that. Figure 11b plots the cut-off frequency variation of LPF. The maximum and minimum cut-off frequencies of the LPF are 64.6 Hz and 6.4 mHz, respectively. In order to remove the second-order harmonic components at 2 f in , which ranges from 20 Hz to 2 MHz, the cut-off frequency can be set to be low enough. The cut-off frequencies of 6.4 mHz, 64 mHz, 640 mHz, 6.4 Hz, and 64.6 Hz are used for the frequency ranges of 10-50 Hz, 50-500 Hz, 500 Hz-5 kHz, and 5 kHz-1 MHz, respectively. When the lowest input signal (10 Hz) is applied, the LPF attenuates the 20 Hz signal around 65 dB.   Figure 12a shows the output signals of the chopper (v + mag (t) and v − mag (t)) and the comparator (φ m (t)) when operating without the buffer and the offset cancellation.

Chopper and Comparator Operation
The comparator converts the IA outputs of sinusoidal waveform to a square waveform φ m (t), and the chopper operates at φ m (t), generating the rectified signal (v + mag (t) and v − mag (t)), which is fed to the LPF ( Figure 5). During this chopping operation, sparks are generated and this kick-back noise severely affects the IA outputs. Then, this again returns to the chopper clock, leading to an oscillating output at the comparator, as shown in Figure 12a. When there is no offset in the comparator, this is not a serious problem because the kick-back spark noises occur exactly at the crossing point every time. In contrast, when there is an offset or low-frequency noise at the comparator, it generates a kick-back phenomenon such as that shown in Figure 12a. To prevent this, a buffer is added between the IA and the choppers, as shown in Figure 5. This isolates the chopper from the comparator inputs (the IA outputs) and breaks the loop, preventing the sparks from returning. Figure 12b plots the signals with the buffers. Even with the offset, a neat square-waveform signal is generated without any kick-back phenomenon.
However, there is still the offset of 15 mV in the case of Figure 12b. Thus, φ m (t) is delayed from the exact zero-crossing point of v + mag (t) and v − mag (t). Therefore, in the proposed IC, the autozeroing technique operates periodically every 10 ms to remove the offset effectively. Figure 12c shows the signals after the offset cancellation. The transition point of φ m (t) and the crossing point of v + mag (t) and v − mag (t) are almost coincident. This shows that the autozeroing technique successfully removes the offset.

Settling-Time Reduction
For the V mag , V mag,r , and V real to reach the final DC value after LPF, the settling time is required. This consists of rising time as slew rate and the linear settling time. Since the slew rate is due to the limitations in the current system, V mag,r and V mag rise with the same slope.
On the other hand, the linear settling is related to the cut-off frequency ( f c ) in proportion to the final value as below: So, when it is measured as a ratio, the cut-off-frequency-dependent term (1 − e −2π f c t ) is canceled out, and accurate data can be obtained immediately after the slew section. Figure 13 shows (a) the final voltage outputs, V mag,r , V mag , V re , (b) the ratios, V mag /V mag,r , V re /V mag,r , and (c) the phase result, when f in = 100 kHz, i in = 4 µA pp , and A I A = 48.7 dB. Each final voltage output (V mag,r , V mag , and V re ) takes 16.3 ms to reach 99.9% accuracy. In contrast, for the ratio (V mag /V mag,r and V re /V mag,r ), the settling time to achieve the same 99.9% accuracy is only 2 ms, which is an 87.7% reduction from 16.3 ms. Note that V mag /V mag,r and V re /V mag,r reach this point with only 7.3% and 5% errors even at 350 µs, respectively. Using Equation (16), the phase result is calculated from the ratio value. As shown in Figure 13c, it also settles much faster than the voltage outputs.
In addition, as shown in the inset of Figure 13b, the ripple is only 0.08% of the final value. This means that the LPF sufficiently removes the high-frequency components, which are modulated up by the chopper. As shown using the proposed ratio detection, much shorter settling times can be achieved with very small ripples. Figure 13. Transient simulated waveforms of (a) the reference magnitude output (V mag,r ), measured magnitude output (V mag ), real output (V re ), (b) the ratio of them (V mag /V mag,r and V re /V mag,r ), and (c) the phase results, when f in = 100 kHz, i in = 4 µA pp , and A I A = 48.7 dB Figure 14 shows |Z m | and θ m results along with the errors. The target impedance shown in the inset of Figure 14a is used. In Figure 14a, the theoretical impedance values are shown as solid lines, and the simulation results are indicated as circles and triangles.

Impedance Readout Resuylts
The readout results well match with the theoretical values over the entire frequency range of 10 Hz-1 MHz. The magnitude, real and phase errors are shown in Figure 14b. The magnitude error calculated by Equation (5) is shown in red, and the error calculated by Equation (7) is shown in black. Since Equation (5) includes only the Z m Mag-path result, it is greatly affected by the nonlinearity of IA and the delay error term. Thus, the error tends to increase as the frequency increases. As a result, by measuring the magnitude with ratio detection, the maximum |Z m | error is reduced from 37.5% to 0.27%. The RE(Z m ) error also decreased from 37.3% to 0.68%. The |Z m | and θ m errors are within ±0.3% and ±2.1 • respectively. Figure 15 shows the effect of buffer on the RE(Z m ) accuracy. Since the real path has no loop including the chopper input and IA output, the errors of with and without buffer can be compared without kick-back phenomenon. The high-frequency signal has a short period, so the error caused by the comparator delay becomes significant. Thus, the compensation effect by the buffer is remarkable as frequency increases. In addition, since the RE(Z m ) is in cosine form of θ m , RE(Z m ) error of 1-10 kHz is larger due to the large θ m .   Table 1 summarizes the performances of the proposed IC and compares them with other state-of-the-art works. A time-stamp IC [34] can cover a 10-times-higher frequency range while consuming 55 times higher power. Other works cover a similar or lower frequency range with much higher power consumption. Therefore, the proposed work achieves one of the best power efficiencies while providing one of the highest |Z m | accuracies and widest frequency ranges.

Conclusions
We proposed the new impedance measurement IC for EIS to support a wide frequency range. In the proposed IC, the reference resistor and its magnitude-measurement path are implemented to compensate for the delay and nonlinearities of the VCCS and IA. The magnitude and real components are measured as a ratio to a reference magnitude, greatly enhancing the measurement speed by more than eight times. Thanks to this measurement method that significantly reduces the effect from many error sources, the frequency range up to 1 MHz can be supported by using the IA with a small bandwidth of 200 kHz, resulting in total power consumption of only 0.513 mW. Moreover, the autozeroing technique was employed to eliminate the offset, and buffers were used to prevent the kickback noise and to compensate for the error caused by the comparator delay. According to the simulation results, the real and magnitude accuracies of our proposed IC are 99.7% and 99.4%, respectively, over a wide frequency range of 10 Hz-1 MHz. The corresponding phase error is less than 0.6 • up to 500 kHz, and 2.1 • up to 1 MHz.