Improved Quasi-Z-Source High Step-Up DC–DC Converter Based on Voltage-Doubler Topology

The step-up DC–DC converter is widely used for applications such as IoT sensor nodes, energy harvesting, and photovoltaic (PV) systems. In this article, a new topological quasi-Z-source (QZ) high step-up DC–DC converter for the PV system is proposed. The topology of this converter is based on the voltage-doubler circuits. Compared with a conventional quasi-Z-source DC–DC converter, the proposed converter features low voltage ripple at the output, the use of a common ground switch, and low stress on circuit components. The new topology, named a low-side-drive quasi-Z-source boost converter (LQZC), consists of a flying capacitor (CF), the QZ network, two diodes, and a N-channel MOS switch. A 60 W laboratory prototype DC–DC converter achieved 94.9% power efficiency.


Introduction
Step-up DC-DC converters are widely used for applications that require high voltage converted from low input voltage, such as energy harvesting systems [1,2], IoT node operating systems on low-voltage battery cells [3], and photovoltaic (PV) systems for grid connection [4][5][6]. Although the necessary power and voltage for application is different, the same dc-dc converter topology is applicable and effective to these applications. The basic boost converter (BBC) is an established technique with a long history by which CR is determined by CR = 1/(1-D), where D is duty cycle. However, it has difficulty of control at high duty cycle when the duty ratio increases because of its nonlinear characteristics and narrow pulse width [7]. In addition, it suffers from the voltage stress on the semiconductor switches and conduction loss that is due to the long ON status of the switches during period D to hold the high CR status. Of course, the high CR can be simply obtained by the series connection of BBC, but it increases loss, cost, and volume; therefore, it is not smart option. To overcome these obstacles, alternative types of high step-up dc-dc converters have been proposed [8][9][10]. There are two approaches to achieve the high CR; one is the isolated type and the other is the non-isolated type. The isolated type obtained the high voltage by changing the secondary and primary turn ratios of the transformers. However, it produces inductor leakage and the necessity for the custom-made transformer, which additionally often requires measurements of unknown key electric and magnetic parameters. In addition, the bulky equipment is not suitable for the harvesting system and IoT node operation system. On the other hand, non-isolated converters are suitable for these applications because of both volume and cost. In this category, there are some promising converters introduced. R-J. Wai et al. [11], S-M. Chen et al. [12], and H-C. Liu et al. [13] proposed a coupled inductor type. However, it required the snubber circuits to suppress the leakage of inductors. In addition, the coupled inductors are not off-the-shelf componentsthe same as the transformer. Recently, a quasi-Z-source network has been installed in  [24]. (d) Key waveforms. Reprinted/adapted with permission from Ref. [24]. Copyright 2022, IEICE.  [7] and Conv. [17], Prop. [24] converters.

Topology Comparison of Converters
In this section, the topology difference between the conventional converter and proposed converter is described. Figure 3 shows the three converters. Figure 3a shows the voltage-doubler [27]. Figure 3b,c are the Mode1 and Mode2 operations of it, respectively. Figure 3d shows a conventional converter [17]. Figure 3e,f are the Mode1 and Mode2 operations of it, respectively. Figure 3g shows the proposed converter [24]. Figure 3h,i are the Mode1 and Mode2 operations of it, respectively. The conventional converter topology can be regarded as the QZ replaced from the S4 in the voltage doubler. Considering other variations, we found the new topology, as shown Figure 3g. The proposed converter can be regarded as the QZ replaced from the S3 in the voltage doubler. By this modification, the proposed converter improved the output ripple, power loss, and voltage stress.  [24]. (d) Key waveforms. Reprinted/adapted with permission from Ref. [24]. Copyright 2022, IEICE.
Mode1: The equivalent circuit for this mode of operation is depicted in Figure 1b. The diode D 1 and transistor M are turned ON and the diode D 2 and D 3 are turned OFF during this operation. The red circles denote the ON state of the switch transistor and diodes. Applying KVL to the closed loops, the following equations are obtained: Mode2: The equivalent circuit for this mode of operation is depicted in Figure 1c. The D 2 and D 3 are turned ON and diode D 1 and transistor M are turned OFF during this operation. Applying KVL to the closed loops, the following equations are obtained: Applying the volt-second balance to inductor L 1 using Equations (1) and (4), assume C 1 = C 2 : By substituting Equation (9) for Equation (6), and using Equation (3), V o /V g was obtained as follows: Equation (10) shows the same CR (=V o /V g ) as obtained by [17]. Figure 1d shows the key waveforms. Figure 2 shows the CR of the BBC and the proposed converter. To eliminate narrow pulse-width control difficulty, the conventional converter [17] and the proposed converter [24] are designed to operate in a range from 0 to 0.5 of D, unlike BBT. The CR of Conv. [17] and Prop. [24] is obtained as 6.00 but that of BBT [7] becomes only 1.67 at D = 0.4.

Topology Comparison of Converters
In this section, the topology difference between the conventional converter and proposed converter is described. Figure 3 shows the three converters. Figure 3a shows the voltage-doubler [27]. Figure 3b,c are the Mode1 and Mode2 operations of it, respectively. Figure 3d shows a conventional converter [17]. Figure 3e,f are the Mode1 and Mode2 operations of it, respectively. Figure 3g shows the proposed converter [24]. Figure 3h,i are the Mode1 and Mode2 operations of it, respectively. The conventional converter topology can be regarded as the QZ replaced from the S4 in the voltage doubler. Considering other variations, we found the new topology, as shown Figure 3g. The proposed converter can be regarded as the QZ replaced from the S3 in the voltage doubler. By this modification, the proposed converter improved the output ripple, power loss, and voltage stress. 6.00 1.67 Figure 2. CR of BBC [7] and Conv. [17], Prop. [24] converters.

Topology Comparison of Converters
In this section, the topology difference between the conventional converter and proposed converter is described. Figure 3 shows the three converters. Figure 3a shows the voltage-doubler [27]. Figure 3b,c are the Mode1 and Mode2 operations of it, respectively. Figure 3d shows a conventional converter [17]. Figure 3e,f are the Mode1 and Mode2 operations of it, respectively. Figure 3g shows the proposed converter [24]. Figure 3h,i are the Mode1 and Mode2 operations of it, respectively. The conventional converter topology can be regarded as the QZ replaced from the S 4 in the voltage doubler. Considering other variations, we found the new topology, as shown Figure 3g. The proposed converter can be regarded as the QZ replaced from the S 3 in the voltage doubler. By this modification, the proposed converter improved the output ripple, power loss, and voltage stress.

Output Voltage Ripple
The output voltage of the proposed converter is significantly reduced compared to the converter. The droop voltage of the output comes up when the output capacitor C o disconnects the source voltage V g . This situation occurs in Mode2 in the conventional converter that is shown in Figure 3f. Since the output capacitor C o connects to only the load current I o , the output voltage V o droops at the rate determined by V o = (C o /I o ) t. As the high step-up DC-DC converter operates generally less than D = 0.5, the period of the operation time of Mode2 shown Figure 3f is longer than that of Mode1 shown Figure 3d. On the other hand, in the proposed converter, the period of time disconnected from source voltage V g occurs in Mode1, as shown Figure 3h. This advantage results in that low EMI and the available small-output capacitor.

High Side Driver and Level Shifter
The switch S 3 in Figure 3d is given by the N-channel MOS transistor [17], where the drain terminal of the N-channel MOS transistor is connected to V g and the source terminal is connected to QZ. It means that this is necessary for the high-side driver and the level shift circuits for S 3 . The level shift circuits consume operating power, and some additional circuits are required for proper start-up of the DC-DC converter. In contrast, The LQZC is high-side driver-free because the source terminal of S 4 is terminated to GND, as shown in Figure 3g. It can improve the efficiency and reduce the cost and complex design of the converter.

Output Voltage Ripple
The output voltage of the proposed converter is significantly reduced compared to the converter. The droop voltage of the output comes up when the output capacitor Co disconnects the source voltage Vg. This situation occurs in Mode2 in the conventional converter that is shown in Figure 3f. Since the output capacitor Co connects to only the load current Io, the output voltage Vo droops at the rate determined by Vo = (Co/Io) t. As the high step-up DC-DC converter operates generally less than D = 0.5, the period of the operation time of Mode2 shown Figure 3f is longer than that of Mode1 shown Figure 3d. On the other hand, in the proposed converter, the period of time disconnected from source voltage Vg occurs in Mode1, as shown Figure 3h. This advantage results in that low EMI and the available small-output capacitor.

High Side Driver and Level Shifter
The switch S3 in Figure 3d is given by the N-channel MOS transistor [17], where the drain terminal of the N-channel MOS transistor is connected to Vg and the source terminal is connected to QZ. It means that this is necessary for the high-side driver and the level shift circuits for S3. The level shift circuits consume operating power, and some additional circuits are required for proper start-up of the DC-DC converter. In contrast, The LQZC is high-side driver-free because the source terminal of S4 is terminated to GND, as shown in Figure 3g. It can improve the efficiency and reduce the cost and complex design of the converter.

Voltage Stress
The proposed converter provides the reduction in voltage stress for the flying capacitor CF. The voltage stress of elements is shown in Table 1. In a conventional converter, the terminals of CF are applied by Vo and Vg as shown in Figure 3e. Using Equation (10), the terminal voltage across CF becomes: In contrast, the voltage stress of the CF applied only Vg. The voltage across CF is determined as follows:

Voltage Stress
The proposed converter provides the reduction in voltage stress for the flying capacitor C F . The voltage stress of elements is shown in Table 1. In a conventional converter, the terminals of C F are applied by V o and V g as shown in Figure 3e. Using Equation (10), the terminal voltage across C F becomes: In contrast, the voltage stress of the C F applied only V g . The voltage across C F is determined as follows: This is obvious from Figure 3h and Equation (3). Consequently, the proposed converter can mitigate the voltage stress of C F . The stress voltages of other elements, D 1 , D 2 , M, C 1 , and C 2 , are same as those of a conventional converter [17].  Table 2. Here all capacitors are film type.

Measurement Setup
connected the electric current load Array 3710 A, of which the output resistance Ro is set from 175 Ω to 500 Ω. The electrolytic capacitor CIN, 470 uF (200 V), is connected between the Vg and GND as an input filter. The waveform of the output voltage Vo and the flying capacitor CF are measured by a high-voltage differential probe, Textronix P5200A, on 50:1 attenuation, and the inductor current IL1 is measured by the current probe Textronix P6021A. The input voltage Vg and clock signal CLK are measured by the passive probe Textronix TPP0250 on 10:1 attenuation.

Components
Values and Main Parameters Parts No.    Figure 6 shows the steady-state measurement waveforms of IL1, Vo, VCF, and CLK when D = 0.3 and Ro = 500 Ω, and set to Vg = 20 V, 30 V, and 40 V, respectively. Figure 7 shows the relationship between the measured output voltage Vo and duty cycle D drawn together with the calculated gain by the dotted lines. The duty cycle D changed   Figure 6 shows the steady-state measurement waveforms of I L1 , V o , V CF , and CLK when D = 0.3 and R o = 500 Ω, and set to V g = 20 V, 30 V, and 40 V, respectively.  Figure 6 shows the steady-state measurement waveforms of IL1, Vo, VCF, and CLK when D = 0.3 and Ro = 500 Ω, and set to Vg = 20 V, 30 V, and 40 V, respectively. Figure 7 shows the relationship between the measured output voltage Vo and duty cycle D drawn together with the calculated gain by the dotted lines. The duty cycle D changed from 0.05 to 0.35 for input voltage Vg = 20 V, 30 V, and 40 V, respectively, on Ro = 500 Ω. The measurement results agree well with the calculated results. When the duty cycle D is small, the output voltage Vo is slightly low because of the forward voltage VF of D1. Figure 8 depicts the relationship between the output power Po and the efficiency η using the data of Figure 7. Figure 9 shows the efficiency versus the output power Po at Vg = 40 V and D = 0.2 when Ro varies from 500 Ω to 175 Ω by 25 Ω steps. The peak efficiency 94.9 % is obtained. Table 3 summarizes the performance comparison of Conv. [17] and this work.            Figure 9 shows the efficiency versus the output power P o at V g = 40 V and D = 0.2 when R o varies from 500 Ω to 175 Ω by 25 Ω steps. The peak efficiency 94.9 % is obtained. Table 3 summarizes the performance comparison of Conv. [17] and this work.

M. Veerachary ICSETS 2019 [11] This Work
High Side Driver and Level Shifter Necessary Unnecessary Efficiency N/A 94.9%

Discussion
In this section, the effect of the parasitic element of the proposed converter is discussed. Generally, the equivalent series resistance (ESR) of the capacitors is relatively smaller than the DC resistance (RDC) of the inductor [28][29][30]. So, we focus on the parasitic element of the inductors. Figure 10 shows the proposed converter, which includes the parasitic resistance depicted by the blue resistor symbol. Vg=40V Figure 9. Peak efficiency η. Table 3. Performance summaries.

Discussion
In this section, the effect of the parasitic element of the proposed converter is discussed. Generally, the equivalent series resistance (ESR) of the capacitors is relatively smaller than the DC resistance (R DC ) of the inductor [28][29][30]. So, we focus on the parasitic element of the inductors. Figure 10 shows the proposed converter, which includes the parasitic resistance depicted by the blue resistor symbol.
Considering the steady-state condition, the average current through a capacitor operating in a periodic steady state is zero and the average current through an inductor operating in a periodic steady state is zero [7]; therefore, the average inductor current I L1 can be written as follows.
By substituting Equation (10) with Equation (13) and using V g I g = V o I o , the following equation is obtained.
Equation (14) indicates that the inductor current I L1 is larger than the output current

Level Shifter
Necessary Unnecessary Efficiency N/A 94.9%

Discussion
In this section, the effect of the parasitic element of the proposed converter is discussed. Generally, the equivalent series resistance (ESR) of the capacitors is relatively smaller than the DC resistance (RDC) of the inductor [28][29][30]. So, we focus on the parasitic element of the inductors. Figure 10 shows the proposed converter, which includes the parasitic resistance depicted by the blue resistor symbol.  In Mode1, the voltage expressions obtained using KVL are: where V r = R DC × I L .
In Mode2, the voltage expressions obtained using KVL are: Applying the volt-second balance to inductor L: Compared to Equation (9), Equation (18) indicates that when the voltage of capacitor V c is reduced by V r , it results in reducing V o . This is attributed to the voltage across inductors V L being reduced in Mode1 by R DC .
By substituting Equation (18) for Equation (6), V CF = V g , V o /V g is obtained as follows: To verify Equation (19), the output voltage V o was checked by the PSIM [30] simulator when conditions changed. In the simulator circuit, the output resistance R o is set to 100Ω, and R DC are added to L 1 and L 2 , respectively, in Figure 11. In this situation, four cases are tested. Figure 12 shows the simulation results of output voltage V o in four cases. The blue line is output voltage V o , and the red line is input voltage V g . Table 4 shows the results of calculations and the simulation results.

Conclusions
This article has introduced a new high step-up DC-DC converter. The LQZC realizes a low output ripple, is free from the use of a level shifter and a high-side switch, and is plus the low stress on a flying capacitor C F . The proposed converter makes the following contributions: (i) by the low output ripple, a reliability and cost reduction for the DC-DC converter itself and the inverter circuit for the PV system because the low ripple voltage reduces the size of the capacitors and its aging. (ii) By omitting the level shifter circuit, the consuming loss is definitely reduced because the level shifter circuits and their accompanied circuits are not necessary. (iii) By reducing the voltage stress of the components, the equipment volume becomes small and reduces cost. The achieved efficiency of the converter was more than 94.9% in this prototype. Although the prototype design focuses on a PV application, the proposed architecture can be applied to applications that require the high step-up DC-DC converter, such as energy harvesting and low voltage battery systems for IoT sensor nodes, by power scaling down.