A Direct Feedback FVF LDO for High Precision FMCW Radar Sensors in 65-nm CMOS Technology

A direct feedback flipped voltage follower (FVF) LDO for a high-precision frequency-modulated continuous-wave (FMCW) radar is presented. To minimize the effect of the power supply ripple on the FMCW radar sensor’s resolution, a folded cascode error amplifier (EA) was connected to the outer loop of the FVF to increase the open-loop gain. The direct feedback structure enhances the PSRR while minimizing the power supply ripple path and not compromising a transient response. The flipped voltage follower with a super source follower forms a fast feedback loop. The stability and parameter variation sensitivity of the multi-loop FVF LDO were analyzed through the state matrix decomposition. We implemented the FVF LDO in TSMC 65 nm CMOS technology. The fabricated FVF LDO supplied a maximum load current of 20 mA with a 1.2 V power supply. The proposed FVF LDO achieved a full-spectrum PSR with a low-frequency PSRR of 66 dB, unity-gain bandwidth of 469 MHz, and 20 ns transient settling time with a load current step from 1 mA to 20 mA.


Introduction
Starting from military equipment, the FMCW radar sensor has broadened its application to an autonomous vehicle, a 3D imaging system, and a weather forecast. At the same time, the power management has become an integral part of the FMCW transceiver. To ensure the spatial and range resolution of the FMCW radar sensor, the power management circuit must supply stable and isolated supply voltages to each sensitive block, such as the PLL, mixer, and ADC [1][2][3][4][5][6][7][8][9][10]. With sawtooth modulation with T m = 2 ms, the time delay (τ) and the beat frequency (f b ) for the frequency-modulated received signal from a target at a distance of R is given as With K f of 500 GHz/s and a target range of 180 m, the maximum beat frequency is 600 kHz. Thus, the LDO should reject the low-frequency ripple from the supply to prevent it from degrading the phase noise of the PLL, which is the frequency modulation signal source. Moreover, even the power supply ripple of the frequency higher than the ADC sampling frequency may fold into the ADC in-band. Hence, it is essential for the LDO to reject a wide range of the power supply ripple, especially at the low-frequency range. We noticed that the FMCW frequency hopping approach [11] required an LDO to respond rapidly to the transient load variation. This is because the current consumption of the PLL changes relatively rapidly with the frequency hopping.
In order to achieve a high PSR across a wide frequency range, various analog circuit techniques have been introduced. A feedforward ripple cancellation achieves a high PSR by combining a feedback and feedforward signal path [12][13][14][15][16]. A bandgap reference (BGR) recursive configuration [17] and an output-supplied voltage reference [18] have been proposed to reduce the effect of a non-ideal PSR of the bandgap reference. A multi-loop structure [19][20][21][22][23] has been introduced to boost the unity-gain bandwidth and the transient response in various configurations. The flipped voltage follower (FVF) LDO [24] has become one of the most popular analog LDO approaches for the last decade. The FVF LDO has a local feedback loop that reduces output resistance. In addition, an independent control voltage generator can provide an adequate control voltage for the control transistor. However, the transient time of the local feedback loop is relatively slow due to the large pass transistor, and the unity-gain bandwidth of the LDO has been limited. A tri-loop FVF LDO with buffered FVF was proposed to achieve full-spectrum PSR and fast response time in [25]. Although additional loops through a tri-input EA provided more loop gain, the resulting low-frequency PSR was not sufficiently improved. A dual-loop FVF LDO was reported to provide full-spectrum PSR with high low-frequency PSR in [26]. As the control voltage regulating loop was removed, it created another power supply ripple path through the inverting stage, which necessitated an auxiliary LDO.
In this paper, a direct feedback FVF LDO was proposed. By constructing an error amplifier (EA) that directly controls the FVF local loop, the FVF LDO can eliminate the power supply ripple path, resulting in a high PSRR without the need for additional components. A local FVF loop with a super source follower realizes a fast transient response with a unity-gain bandwidth of 469 MHz, and an outer loop incorporating folded cascode EA enhanced a low-frequency PSR to 66 dB. State matrix decomposition [27] was applied to analyze the stability and parameter sensitivity of a multi-loop FVF LDO.
This paper is organized as follows. Section 2 introduces the proposed direct-feedback LDO. The PSRR and stability analysis of the FVF LDO was also presented. State matrix decomposition [27] was employed to analyze the stability and parameter sensitivity of the multi-loop FVF LDO. Section 3 shows the experimental result with a fabricated FVF LDO, and Section 4 follows with a conclusion. Figure 1 shows a schematic diagram of the proposed LDO regulator. The LDO consisted of a unity-gain buffer, an error amplifier (EA), an output capacitor, and transistors, M pass , M 1 , and M 2 . M pass , M 1 , and M 2 formed a flipped voltage follower. Fast and weak shunt-shunt feedback loop 1 in the flipped voltage follower enables the fast response of the LDO. The output of the error amplifier, V SET , sets the input level of the flipped voltage follower. The input of the EA was connected to the reference input (V REF ), and V OUT formed another feedback loop 2. This dramatically enhanced the open loop gain of the overall loop. Since V OUT was directly fed back into EA and the inverting stage was removed, we can eliminate the power supply ripple path without the need for an additional component. To enhance the transient performance, we needed to make the dominant pole of the fast loop 1 located at the output node. The output capacitor, C L , was connected to the output of the LDO to make the output node of the LDO dominant pole, and the capacitor, C 1 , was connected to the output of the error amplifier to stabilize loop 2. An additional compensation capacitor, C 2 , was enabled by a start-up pulse generator to guarantee more phase margin during the start-up situation. The unity-gain buffer was to drive the large power transistor, M pass . The size of the transistors, the capacitor values, and the load current (I L ) values are listed in Table 1.

Fast Loop 1 Analysis
At higher frequencies where loop 2 did not work, only loop 1 worked. Without loop 2, the LDO simply had the flipped voltage follower (FVF) used as the power stage. The proposed LDO without loop 2 is shown in Figure 2a. The input V SET sets the output voltage of the FVF, and any interference or noise in the V IN works as a disturbance for the system. The series-shunt feedback structure reduced the output impedance of the system, enabling a high-frequency operation. The noise or interference from the power source was reduced by the internal feedback loop. To perform the PSRR analysis of the proposed LDO, we established a small-signal block diagram of the LDO. The block diagram is shown in Figure 2b. The V SET works as a reference input of the FVF, and any interference or noise in V IN was a disturbance for the system. The open-loop gain and output of LDO is where g m1 is the transconductance of M 1 , r o1 and r o2 are the output resistance of M 1 and M 2 , respectively, C A is capacitance seen at node A, ω n is the natural frequency of the super source follower, ζ is the damping factor of the super source follower, g mP is the transconductance of the pass transistor, R L is the load resistance, r oP is the output resistance of the pass transistor, and C OUT is the capacitance seen at the output node. Supply noise is reduced approximately by G A at high frequency. The bandwidth of the super source follower was boosted due to the internal feedback structure, and the pole at node A was also at high frequency, as M 1 and M 2 were small. The output capacitor, C L , was set such that the pass transistor, M Pass , was the slowest working component, and the dominant pole of the controller gain, G A and G SSF , were placed at a higher frequency. Therefore, loop 1 suppressed the supply noise through a wide frequency range. The supply noise at a higher frequency was absorbed by the large C L . proposed LDO without loop 2 is shown in Figure 2a. The input VSET sets the output voltage of the FVF, and any interference or noise in the VIN works as a disturbance for the system. The series-shunt feedback structure reduced the output impedance of the system, enabling a high-frequency operation. The noise or interference from the power source was reduced by the internal feedback loop. To perform the PSRR analysis of the proposed LDO, we established a small-signal block diagram of the LDO. The block diagram is shown in Figure 2b. The VSET works as a reference input of the FVF, and any interference or noise in VIN was a disturbance for the system. The open-loop gain and output of LDO is where gm1 is the transconductance of M1, ro1 and ro2 are the output resistance of M1 and M2, respectively, CA is capacitance seen at node A, ωn is the natural frequency of the super source follower, ζ is the damping factor of the super source follower, gmP is the transconductance of the pass transistor, RL is the load resistance, roP is the output resistance of the pass transistor, and COUT is the capacitance seen at the output node. Supply noise is reduced approximately by GA at high frequency. The bandwidth of the super source follower was boosted due to the internal feedback structure, and the pole at node A was also at high frequency, as M1 and M2 were small. The output capacitor, CL, was set such that the pass transistor, MPass, was the slowest working component, and the dominant pole of the controller gain, GA and GSSF, were placed at a higher frequency. Therefore, loop 1 suppressed the supply noise through a wide frequency range. The supply noise at a higher frequency was absorbed by the large CL.

Slow Loop 2 Analysis
The folded cascode amplifier can drastically improve the closed-loop gain. Since V OUT was directly fed back into the EA and the inverting stage was removed, we could eliminate the power supply ripple path without the need for an additional component. Figure 3 shows the loop 2 feedback path. Breaking the loop at V SET gives where G EA is the voltage gain of the folded cascode amplifier. The PSRR is boosted approximately by G EA . Loop 1 is a unity-gain feedback network seen at node V SET , and the unity-gain bandwidth of loop 1 was far beyond that of the EA. Hence, we simply needed to compensate for the folded cascode EA. The folded cascode amplifier can be stabilized simply by adding the compensation capacitor, C 1 , to the output of the amplifier.

Slow Loop 2 Analysis
The folded cascode amplifier can drastically improve the closed-loop gain. Since VOUT was directly fed back into the EA and the inverting stage was removed, we could eliminate the power supply ripple path without the need for an additional component. Figure 3 shows the loop 2 feedback path. Breaking the loop at VSET gives where GEA is the voltage gain of the folded cascode amplifier. The PSRR is boosted approximately by GEA. Loop 1 is a unity-gain feedback network seen at node VSET, and the unity-gain bandwidth of loop 1 was far beyond that of the EA. Hence, we simply needed to compensate for the folded cascode EA. The folded cascode amplifier can be stabilized simply by adding the compensation capacitor, C1, to the output of the amplifier.

Overall Loop Analysis
Loop 1 and Loop 2 formed a combined global loop. The global loop had the largest closed-loop gain, making it critical for the phase margin design. Figure 4 shows the combined diagram of loop 1 and loop 2. By breaking the loop at the node VG, the output voltage is expressed as

Overall Loop Analysis
Loop 1 and Loop 2 formed a combined global loop. The global loop had the largest closed-loop gain, making it critical for the phase margin design. Figure 4 shows the combined diagram of loop 1 and loop 2. By breaking the loop at the node V G , the output voltage is expressed as  Here, the open-loop gain had a dominant pole at the output of the EA, and the second pole was at the output of the LDO. The (1 + G EA ) term in (11) made a quadratic zero near the unity-gain bandwidth of the EA. This zero was set to cancel out the second pole, which was below the unity-gain bandwidth of the LDO. It was noted that the LDO would be unstable without this zero. As a result, the (1 + G EA ) term boosted the unity-gain bandwidth of the LDO. Figure 5 shows the phase margin simulation result. The unitygain bandwidth of loop 1 was 507 MHz, and the phase margin was 37.3°. The unity-gain bandwidth of the loop 2 was 31.2 MHz, and the phase margin was 63.6°. The unity-gain bandwidth of the overall loop was 469 MHz, and the phase margin was 44.1°.

Effect of Non-Ideal PSRR of Each Component
There was more than one power supply ripple path in the FVF LDO. Circuit blocks with a non-ideal PSRR can provide an additional path for the power supply ripple. Figure  6 shows the effect of non-ideal components on PSRR. With the simplified model, the output of the LDO is given as Here, the open-loop gain had a dominant pole at the output of the EA, and the second pole was at the output of the LDO. The (1 + G EA ) term in (11) made a quadratic zero near the unity-gain bandwidth of the EA. This zero was set to cancel out the second pole, which was below the unity-gain bandwidth of the LDO. It was noted that the LDO would be unstable without this zero. As a result, the (1 + G EA ) term boosted the unity-gain bandwidth of the LDO. Figure 5 shows the phase margin simulation result. The unity-gain bandwidth of loop 1 was 507 MHz, and the phase margin was 37.3 • . The unity-gain bandwidth of the loop 2 was 31.2 MHz, and the phase margin was 63.6 • . The unity-gain bandwidth of the overall loop was 469 MHz, and the phase margin was 44.1 • . Here, the open-loop gain had a dominant pole at the output of the EA, and the second pole was at the output of the LDO. The (1 + G EA ) term in (11) made a quadratic zero near the unity-gain bandwidth of the EA. This zero was set to cancel out the second pole, which was below the unity-gain bandwidth of the LDO. It was noted that the LDO would be unstable without this zero. As a result, the (1 + G EA ) term boosted the unity-gain bandwidth of the LDO. Figure 5 shows the phase margin simulation result. The unitygain bandwidth of loop 1 was 507 MHz, and the phase margin was 37.3°. The unity-gain bandwidth of the loop 2 was 31.2 MHz, and the phase margin was 63.6°. The unity-gain bandwidth of the overall loop was 469 MHz, and the phase margin was 44.1°.

Effect of Non-Ideal PSRR of Each Component
There was more than one power supply ripple path in the FVF LDO. Circuit blocks with a non-ideal PSRR can provide an additional path for the power supply ripple. Figure  6 shows the effect of non-ideal components on PSRR. With the simplified model, the output of the LDO is given as

Effect of Non-Ideal PSRR of Each Component
There was more than one power supply ripple path in the FVF LDO. Circuit blocks with a non-ideal PSRR can provide an additional path for the power supply ripple. Figure 6 shows the effect of non-ideal components on PSRR. With the simplified model, the output of the LDO is given as where PSR SSF is the power supply rejection of the super source follower, PSR A is the power supply rejection of the FVF stage, and PSR EA is the power supply rejection of the folded cascode amplifier. The PSRR of the FVF stage and EA should be as low as possible. On the other hand, the super source follower with a poor PSRR helps the LDO reject the power supply ripple by working as a feedforward path.
where PSRSSF is the power supply rejection of the super source follower, PSRA is the power supply rejection of the FVF stage, and PSREA is the power supply rejection of the folded cascode amplifier. The PSRR of the FVF stage and EA should be as low as possible. On the other hand, the super source follower with a poor PSRR helps the LDO reject the power supply ripple by working as a feedforward path.

Stability Analysis of Proposed LDO
Since the proposed LDO has two feedback loops, state matrix decomposition [27] must be more suitable for analyzing the stability than a classical open-loop ac analysis. Without looking at each loop separately, the closed-loop analysis gives a state space model as The detailed closed-loop analysis is shown in the Appendix A. The LDO is asymptotically stable when all the real parts of the eigenvalues of matrix A are negative. The eigenvalues are given as λ 1 = -5.543 · 10 9 + j4.612 · 10 9 λ 2 = -5.543 · 10 9 − j4.612 · 10 9 λ 3 = -1.414 · 10 9 + j4.342 · 10 9 (16)

Stability Analysis of Proposed LDO
Since the proposed LDO has two feedback loops, state matrix decomposition [27] must be more suitable for analyzing the stability than a classical open-loop ac analysis. Without looking at each loop separately, the closed-loop analysis gives a state space model as The detailed closed-loop analysis is shown in the Appendix A. The LDO is asymptotically stable when all the real parts of the eigenvalues of matrix A are negative. The eigenvalues are given as λ 1 = −5.543 × 10 9 +j4.612 × 10 9 λ 2 = −5.543 × 10 9 − j4.612 × 10 9 λ 3 = −1.414 × 10 9 +j4.342 × 10 9 λ 4 = −1.414 × 10 9 − j4.342 × 10 9 λ 5 = −3.444 × 10 8 +j2.297 × 10 8 λ 6 = −3.444 × 10 8 − j2.297 × 10 8 (16) Since all the eigenvalues have negative real parts, the LDO was asymptotically stable. The parameters used in the analysis are given in Table 2. The parameters were extracted from the circuit simulation results, including parasitics. Figure 7 compares the PSRR simu-  λ 4 = -1.414 · 10 9 − j4.342 · 10 9 λ 5 = -3.444 · 10 8 + j2.297 · 10 8 λ 6 = -3.444 · 10 8 − j2.297 · 10 8 Since all the eigenvalues have negative real parts, the LDO was asymptotically stable. The parameters used in the analysis are given in Table 2. The parameters were extracted from the circuit simulation results, including parasitics. Figure 7 compares the PSRR simulation results from the circuit simulator and state space model. The state space model fits the circuit simulation result and can predict the pole/zero location of the transfer function.  The red line represents the simulation result with the state space model, and the blue line represents the simulation result with Cadence Spectre. We also identified the parameter variation sensitivity by computing the real part of the critical eigenvalue with variation in each parameter. Plotting the highest real part of the eigenvalues, the circuit should follow the conditions:  The red line represents the simulation result with the state space model, and the blue line represents the simulation result with Cadence Spectre. We also identified the parameter variation sensitivity by computing the real part of the critical eigenvalue with variation in each parameter. Plotting the highest real part of the eigenvalues, the circuit should follow the conditions:

Measurement Results
We implemented the LDO in TSMC 65 nm CMOS technology with an active area of 0.037 mm 2 , including a 350 pF on-chip output capacitor. Figure 9 shows a chip photograph of a fabricated FVF LDO. A 350 pF output capacitor was implemented on-chip using a MOM capacitor. We performed the on-chip probe measurements and the chip-on-board measurements. The power supply rejection ratio measurement setting is shown in Figure 10. The Analog Device ADA4870 OPAMP supplied the DC power and ac ripple at the frequency of fR to the LDO. The OPAMP was used to reduce the output impedance and combine the DC voltage with the ac ripple. A Keysight E36313A DC power supply sets the reference voltage and voltage bias for the OPAMP. A BK Precision BK4063B arbitrary signal

Measurement Results
We implemented the LDO in TSMC 65 nm CMOS technology with an active area of 0.037 mm 2 , including a 350 pF on-chip output capacitor. Figure 9 shows a chip photograph of a fabricated FVF LDO. A 350 pF output capacitor was implemented on-chip using a MOM capacitor. We performed the on-chip probe measurements and the chip-onboard measurements.

Measurement Results
We implemented the LDO in TSMC 65 nm CMOS technology with an active area of 0.037 mm 2 , including a 350 pF on-chip output capacitor. Figure 9 shows a chip photograph of a fabricated FVF LDO. A 350 pF output capacitor was implemented on-chip using a MOM capacitor. We performed the on-chip probe measurements and the chip-on-board measurements. The power supply rejection ratio measurement setting is shown in Figure 10. The Analog Device ADA4870 OPAMP supplied the DC power and ac ripple at the frequency of fR to the LDO. The OPAMP was used to reduce the output impedance and combine the DC voltage with the ac ripple. A Keysight E36313A DC power supply sets the reference voltage and voltage bias for the OPAMP. A BK Precision BK4063B arbitrary signal The power supply rejection ratio measurement setting is shown in Figure 10. The Analog Device ADA4870 OPAMP supplied the DC power and ac ripple at the frequency of f R to the LDO. The OPAMP was used to reduce the output impedance and combine the DC voltage with the ac ripple. A Keysight E36313A DC power supply sets the reference voltage and voltage bias for the OPAMP. A BK Precision BK4063B arbitrary signal generator provided the input ripple signal to the OPAMP. A Keysight B2902A SMU supplied I ref to bias the internal amplifiers and buffer. The biasing point was controlled by the SPI Module. A Keysight DSO-X oscilloscope was used to measure the input and output ripple. The PSRR was calculated using measured input and output. Figure 11 shows the PSRR measurement result. The fabricated FVF LDO achieved a full-spectrum PSR of 64.6 dB at 100 kHz and the worst measured PSRR of 10 dB at 200 MHz. generator provided the input ripple signal to the OPAMP. A Keysight B2902A SMU supplied Iref to bias the internal amplifiers and buffer. The biasing point was controlled by the SPI Module. A Keysight DSO-X oscilloscope was used to measure the input and output ripple. The PSRR was calculated using measured input and output. Figure 11 shows the PSRR measurement result. The fabricated FVF LDO achieved a full-spectrum PSR of 64.6 dB at 100 kHz and the worst measured PSRR of 10 dB at 200 MHz.  The load transient measurement setting is shown in Figure 12. A Keysight E36313A was used to supply VIN and VREF to the LDO, and a Keysight B2902A was used to input IREF to bias the internal amplifiers and buffer. The load control signal was given from the BK precision BK4064B arbitrary signal generator. The load current was stepped from minimum to maximum, with an edge time of 8 ns. The load transient measurement result  generator provided the input ripple signal to the OPAMP. A Keysight B2902A SMU supplied Iref to bias the internal amplifiers and buffer. The biasing point was controlled by the SPI Module. A Keysight DSO-X oscilloscope was used to measure the input and output ripple. The PSRR was calculated using measured input and output. Figure 11 shows the PSRR measurement result. The fabricated FVF LDO achieved a full-spectrum PSR of 64.6 dB at 100 kHz and the worst measured PSRR of 10 dB at 200 MHz.  The load transient measurement setting is shown in Figure 12. A Keysight E36313A was used to supply VIN and VREF to the LDO, and a Keysight B2902A was used to input IREF to bias the internal amplifiers and buffer. The load control signal was given from the BK precision BK4064B arbitrary signal generator. The load current was stepped from minimum to maximum, with an edge time of 8 ns. The load transient measurement result The load transient measurement setting is shown in Figure 12. A Keysight E36313A was used to supply V IN and V REF to the LDO, and a Keysight B2902A was used to input I REF to bias the internal amplifiers and buffer. The load control signal was given from the BK precision BK4064B arbitrary signal generator. The load current was stepped from minimum to maximum, with an edge time of 8 ns. The load transient measurement result is given in Figure 13. The maximum voltage droop was 30.3 mV, and the settling time was about 16 ns. Transient load regulation was 141 µV/mA. is given in Figure 13.    The line transient measurement setting was the same as the PSRR measurement setting, and the only difference was that the ripple signal, f R , was replaced with a square wave. The line transient measurement result is given in Figure 14. With the power supply voltage changing from 1.2 V to 1.4 V within 20 ns, the output voltage changed by about 25.7 mV. The settling time to the final value was about 40 ns. Table 3 summarizes the performance of the proposed FVF LDO with other state-of-theart LDOs. The proposed FVF LDO occupied a 0.037 mm 2 active area. The LDO output was 1 VDC with a supply voltage of 1.2 VDC. The maximum output current was 20 mA, and the quiescent current was 290 µA. An output capacitor of 350 pF was used. The worst-case load transient overshoot was 30.3 mV with a load current step of 8 ns edge time, and the output was settled within 16 ns. When the response time of the LDO is comparable to the edge time, the assumption in the simple response time equation [28] is no longer valid.
Assuming that the load current varies at a constant rate [29], the response time is given as   Table 3 summarizes the performance of the proposed FVF LDO with other state-ofthe-art LDOs. The proposed FVF LDO occupied a 0.037 mm 2 active area. The LDO output was 1 VDC with a supply voltage of 1.2 VDC. The maximum output current was 20 mA, and the quiescent current was 290 µA. An output capacitor of 350 pF was used. The worstcase load transient overshoot was 30.3 mV with a load current step of 8 ns edge time, and the output was settled within 16 ns. When the response time of the LDO is comparable to the edge time, the assumption in the simple response time equation [28] is no longer valid.
Assuming that the load current varies at a constant rate [29], the response time is given as   The shorter the response time, the better the performance is. The response time, calculated according to (18), is shown in Table 2. The response time of the LDO was 2.99 ns. Transient FoM [28] is given by where the smaller FoM represents better performance. The proposed FVF LDO achieved an FoM of 43.4 ps. The low-frequency PSRR of the FVF LDO was 66 dB, and the worstmeasured PSRR of the LDO was 10 dB at 200 MHz.

Discussion
The proposed FVF LDO was successfully implemented in 65 nm CMOS technology. The PSRR measurement results confirmed that the analytic model and simulation results corresponded quite well with the measured PSRR. Our work has demonstrated that a simple direct feedback structure could improve low-frequency PSRR without additional components. The proposed LDO operated stably with various line/load transient situations, and the output settled rapidly to the final value. For future research, current efficiency can be improved by using an efficient buffer structure or an adaptive bias scheme.

Conclusions
A direct feedback flipped voltage follower (FVF) LDO was proposed. Both the classical ac analysis and the state-space model of the LDO were performed, and the results were compared with the circuit simulations. The parameter variation sensitivity of the LDO was also investigated using the state matrix model. The local FVF loop achieved a fast response and a high unity-gain frequency, and the outer loop with the folded cascode error amplifier (EA) enhanced the low-frequency closed-loop gain. The proposed direct feedback structure had a less power supply ripple path without a complex design. Experimental results verified theoretical predictions.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

Appendix A
Let X 1 = v set /K EA be a state variable, and the gain of the error amplifier is Substituting v set = K EA X 1 into (A1) and identifying the numerator and the denominator, v re f − v out = X 1 + ( 1 /ω p1 + 1 /ω p2 ) ..
Let X 3 = v a /K A be a state variable, and the gain of the error amplifier is Substituting v a = K A X 3 into (A4) and identifying the numerator and the denominator, Let X 4 = v g /K SSF be a state variable, and the gain of the super source follower is G SSF = v g v a = K SSF 1+ 2ζ /ω n s+ 1 /ω 2 n s 2 . (A6) Substituting v g = K SSF X 4 into (A6) and identifying the numerator and the denominator, v a = K A X 3 = X 4 + 2ζ /ω n . X 4 + 1 /ω 2 n ..