Four Unity/Variable Gain First-Order Cascaded Voltage-Mode All-Pass Filters and Their Fully Uncoupled Quadrature Sinusoidal Oscillator Applications

This paper presents four new designs for a first-order voltage-mode (VM) all-pass filter (APF) circuit based on two single-output positive differential voltage current conveyors (DVCCs). The first two proposed VMAPFs with unity-gain, high-input (HI) impedance and low-output (LO) impedance use two DVCCs, a grounded capacitor, and a grounded resistor. The last two proposed first-order VMAPFs with HI impedance and variable-gain control are two resistors added to each of the first two VMAPFs. The last two proposed first-order VMAPFs with variable-gain control use two DVCCs, one grounded capacitor, and three grounded resistors and provide HI impedances, so that VMAPFs can be directly cascaded to obtain high-order filters without additional voltage buffers. The four implementation circuits based only on grounded passive components are particularly applicable for integrated circuits (ICs). To confirm the cascading characteristics, an application example of a fully-uncoupled quadrature sinusoidal oscillator (FQSO) is also proposed. PSpice simulation results have confirmed the feasibility of the proposed structures. VMAPF and FQSO circuits are also constructed from commercial AD8130 and AD844 ICs, and their experimentally measured time and frequency responses are compared to theoretical values. The supply voltages for both the AD8130 and AD844 ICs were ±5 V. The measured power dissipation of the proposed first-order VMAPF and second-order FQSO circuits is 0.6 W. The measured input 1-dB compression point for the four VMAPFs is about 19 dB. The measured total harmonic distortion of the four VMAPFs is less than 0.67% when the input voltage reaches 2.5 Vpp. The calculated figures of merit for the four VMAPFs are 628.2 × 103, 603.06 × 103, 516.53 × 103, and 496.42 × 103, respectively.


Basic Concept of Non-Inverting and Inverting VMAPF Functions
One way to implement the non-inverting and inverting VMAPF functions is to generate the difference functions V o (s) = V in (s) − 2V 1 (s) and V o (s) = 2V 1 (s) − V in (s), respectively, where V o (s) and V in (s) are the output and input voltages, and V 1 (s) is the internal node voltage. If the node voltage V 1 (s) realizes the non-inverting first-order low-pass filtering function with the minimum resistor R and capacitor C V 1 (s) = 1 RC s + 1 RC V in (s) (1) then the form of the non-inverting and inverting VMAPF functions can be realized as follows: Non-inverting VMAPF : Inverting VMAPF : In Equations (1)-(3), the product RC is the time constant of the non-inverting and inverting VMAPF functions. Based on Equations (2) and (3), when the frequency domain s = jω, and ω is the angular frequency, the gain and phase responses are given by Inverting VMAPF : Based on Equations (4) and (5), the VMAPF functions maintain a constant gain while shifting the phase of the input signal. The phase characteristic in Equation (4) provides a phase shift between 180 • and 0 • as the input frequency increases and has a phase shift value of 90 • at the pole angular frequency of ω o . The phase characteristic in Equation (5) provides a phase shift between 0 • and −180 • as the input frequency increases and has a phase shift value of −90 • at the pole angular frequency of ω o . Hence, the non-inverting VMAPF characteristic of the phase shift is a leading phase shifter, and the inverting VMAPF characteristic of the phase shift is a lagging phase shifter. The pole angular frequency ω o of the non-inverting and inverting AP filtering functions can be expressed as

Proposed Four VMAPF Circuits and Application Example
The circuit symbol of the DVCC+ and its behavioral model are shown in Figures 1a and 1b, respectively. DVCC+ can be used for a differential voltage and is a variant of current conveyor with a low impedance current input port X, a high impedance current output port Z+, and two high impedance voltage input ports Y 1 and Y 2 .  DVCC+ with differential input impedances is suitable for processing differential signals because it has two HI impedance terminals. The port relationships of the single-output DVCC+ is characterized by the following matrix [42]: According to Equation (7), the voltage Vx = VY1 − VY2 means that the voltage on port X is the differential sensor voltage for the input ports Y1 and Y2. The current IZ = IX means that the output current of port Z+ equals the input current of port X. The proposed circuits utilize two DVCCs and two/four grounded passive components. Figure 2a and 2b show the first two proposed VMAPF circuits, respectively, with HI impedance at the input voltage terminal and LO impedance at the output voltage terminal. In Figure 2a,b, the symbol Vin is the input voltage; the symbol V1 is the internal node voltage; the symbols Vo1 and Vo2 are the output voltages, and the symbols C1, C2, R1, and R4 are the capacitors and resistors. Each proposed VMAPF employs two DVCCs, one GC, and one GR, which can be directly cascaded for a higher-order filter without additional voltage buffers. Considering the proposed VMAPF in Figure 2a, the nodal equations can be obtained as: Solving Equations (8) and (9), the non-inverting APF transfer function can be obtained as: DVCC+ with differential input impedances is suitable for processing differential signals because it has two HI impedance terminals. The port relationships of the singleoutput DVCC+ is characterized by the following matrix [42]: According to Equation (7), the voltage Vx = V Y1 − V Y2 means that the voltage on port X is the differential sensor voltage for the input ports Y 1 and Y 2 . The current I Z = I X means that the output current of port Z+ equals the input current of port X. The proposed circuits utilize two DVCCs and two/four grounded passive components. Figures 2a and 2b show the first two proposed VMAPF circuits, respectively, with HI impedance at the input voltage terminal and LO impedance at the output voltage terminal. In Figure 2a,b, the symbol V in is the input voltage; the symbol V 1 is the internal node voltage; the symbols V o1 and V o2 are the output voltages, and the symbols C 1 , C 2 , R 1 , and R 4 are the capacitors and resistors. Each proposed VMAPF employs two DVCCs, one GC, and one GR, which can be directly cascaded for a higher-order filter without additional voltage buffers. Considering the proposed VMAPF in Figure 2a, the nodal equations can be obtained as:  DVCC+ with differential input impedances is suitable for processing differential signals because it has two HI impedance terminals. The port relationships of the single-output DVCC+ is characterized by the following matrix [42]: According to Equation (7), the voltage Vx = VY1 − VY2 means that the voltage on port X is the differential sensor voltage for the input ports Y1 and Y2. The current IZ = IX means that the output current of port Z+ equals the input current of port X. The proposed circuits utilize two DVCCs and two/four grounded passive components. Figure 2a and 2b show the first two proposed VMAPF circuits, respectively, with HI impedance at the input voltage terminal and LO impedance at the output voltage terminal. In Figure 2a,b, the symbol Vin is the input voltage; the symbol V1 is the internal node voltage; the symbols Vo1 and Vo2 are the output voltages, and the symbols C1, C2, R1, and R4 are the capacitors and resistors. Each proposed VMAPF employs two DVCCs, one GC, and one GR, which can be directly cascaded for a higher-order filter without additional voltage buffers. Considering the proposed VMAPF in Figure 2a, the nodal equations can be obtained as: Solving Equations (8) and (9), the non-inverting APF transfer function can be obtained as: Solving Equations (8) and (9), the non-inverting APF transfer function can be obtained as: Based on Equation (10), the non-inverting APF has a pole angular frequency ω o as follows: When the capacitor C 1 = C and resistor R 1 = R, the gain and phase responses of the non-inverting APF are the same as given in Equation (4).
Considering the proposed VMAPF in Figure 2b, the nodal equations can be obtained as: Solving Equations (12) and (13), the inverting APF transfer function can be obtained as: According to Equation (14), the pole angular frequency of the inverting APF is ω o = 1/C 2 R 4 . When the capacitor C 2 = C and resistor R 4 = R, the gain and phase responses of the inverting APF are the same as given in Equation (5).
According to Equations (10) and (14), both the non-inverting APF and the inverting APF have unity-gain. By adding two GRs to the first two VMAPFs in Figures 2a and 2b, respectively, two other first-order VMAPFs with HI impedance and variable-gain control were realized, as shown in Figures 3a and 3b, respectively. In Figure 3a,b, the symbol V in is the input voltage; the symbols V o3 and V o4 are the output voltages, and the symbols C 1 , C 2 , R 1 , R 2 , R 3 , R 4 , R 5 , and R 6 are capacitors and resistors. Based on Equation (10), the non-inverting APF has a pole angular frequency ωo as follows: When the capacitor C1 = C and resistor R1 = R, the gain and phase responses of the non-inverting APF are the same as given in Equation (4).
Considering the proposed VMAPF in Figure 2b, the nodal equations can be obtained as: Solving Equations (12) and (13), the inverting APF transfer function can be obtained as: According to Equation (14), the pole angular frequency of the inverting APF is ωo = 1/C2R4. When the capacitor C2 = C and resistor R4 = R, the gain and phase responses of the inverting APF are the same as given in Equation (5).
According to Equations (10) and (14), both the non-inverting APF and the inverting APF have unity-gain. By adding two GRs to the first two VMAPFs in Figure 2a and 2b, respectively, two other first-order VMAPFs with HI impedance and variable-gain control were realized, as shown in Figure 3a and 3b, respectively. In Figure 3a,b, the symbol Vin is the input voltage; the symbols Vo3 and Vo4 are the output voltages, and the symbols C1, C2, R1, R2, R3, R4, R5, and R6 are capacitors and resistors.  The analysis of Figure 3a leads to the non-inverting APF transfer function as follows:  The analysis of Figure 3a leads to the non-inverting APF transfer function as follows: Based on Equation (15), the non-inverting APF has the following pole angular frequency ω 1 and variable-gain control k 1 : Similarly, the analysis of Figure 3b leads to the inverting APF transfer function as follows: Based on Equation (17), the inverting APF has the following pole angular frequency ω 2 and variable-gain control k 2 : Thus, each structure proposed in Figure 3a,b has variable-gain control without affecting the pole angular frequency. Since the circuits of Figure 3a,b have HI impedance, the VM FQSO can be easily implemented by cascading the proposed non-inverting VMAPF and inverting VMAPF circuits without adding additional different circuit structures. To confirm the cascading characterizing of Figure 3a,b, the VM FQSO is implemented using variable-gain control of the proposed non-inverting and inverting APFs. Figure 4 shows the application of the proposed VMAPFs to synthesize a VM FQSO by cascading a noninverting APF transfer function and an inverting APF transfer function with variable-gain control into the feedback loop. Figure 4. Block diagram of a FQSO by cascading a variable-gain control non-inverting APF transfer function and an inverting APF transfer function.
Based on the cascaded non-inverting and inverting APF transfer functions of Figure 4, the characteristic equation (CE) can be obtained.
where ω 1 = 1 , ω 2 = 1 R 4 C 2 , k 1 = R 3 R 2 , and k 2 = R 6 R 5 . According to Equation (19), the frequency of oscillation (FO) and the condition of oscillation (CO) are Examining Equations (20) and (21), FO and CO are fully decoupled. Therefore, FO can be independently adjusted by R 1 and R 4 , and CO can be independently adjusted by R 2 , R 3 , R 5 , and R 6 . Using the oscillator building blocks in Figure 4, Figure 5 shows how the noninverting and inverting APFs of Figure 3a,b can be cascaded to synthesize the VM FQSO, CE, FO, and CO derived from Figure 5 are the same as Equations (19), (20), and (21), respectively.
Examining Equations (20) and (21), FO and CO are fully decoupled. Therefore, FO can be independently adjusted by R1 and R4, and CO can be independently adjusted by R2, R3, R5, and R6. Using the oscillator building blocks in Figure 4, Figure 5 shows how the non-inverting and inverting APFs of Figure 3a,b can be cascaded to synthesize the VM FQSO, CE, FO, and CO derived from Figure 5 are the same as Equations (19), (20), and (21), respectively.
The quadrature sinusoidal oscillator based on cascading a non-inverting APF and an inverting APF with variable-gain control.

Simulation Results
To validate the theoretical analyses, simulations were performed using PSpice, and experimental measurements were performed using AD8130 [43,44] and AD844 [45] commercially available components to determine the feasibility and accuracy of the proposed first-order VMAPFs and second-order FQSO. The supply voltages for both the AD8130 and AD844 were ±5 V. Figure 6 shows a possible equivalent implementation using Analog Devices AD8130 and AD844 ICs instead of DVCC+. To obtain fo = 62.41 kHz, a grounded capacitor of 510 pF and a grounded resistance of 5 kΩ were chosen in Figure 2a

Simulation Results
To validate the theoretical analyses, simulations were performed using PSpice, and experimental measurements were performed using AD8130 [43,44] and AD844 [45] commercially available components to determine the feasibility and accuracy of the proposed first-order VMAPFs and second-order FQSO. The supply voltages for both the AD8130 and AD844 were ±5 V. Figure 6 shows a possible equivalent implementation using Analog Devices AD8130 and AD844 ICs instead of DVCC+. To obtain f o = 62.41 kHz, a grounded capacitor of 510 pF and a grounded resistance of 5 kΩ were chosen in Figure 2a   A single grounded capacitor of 510 pF and three equal grounded resistors of 5 and the last two proposed variable-gain control non-inverting and inverting VMAP cuits, shown in Figure 3a,b, were designed for fo = 62.41 kHz. To verify the last two posed variable-gain control non-inverting and inverting VMAPF circuits in Figure  Figures 9 and 10 show the frequency domain simulations of the non-inverting and in ing VMAPFs with an ideal pole frequency of 62.41 kHz, respectively. For a non-inve VMAPF pole frequency with a theoretical phase shift of 90°, the simulated pole frequ in Figure 9 is 60.3 kHz with an offset of −2.11 kHz. For an inverting VMAPF pole frequ with a theoretical phase shift of −90°, the simulated pole frequency in Figure 10 is kHz, and the offset is −1.91 kHz.   A single grounded capacitor of 510 pF and three equal grounded resistors of 5 and the last two proposed variable-gain control non-inverting and inverting VMAP cuits, shown in Figure 3a,b, were designed for fo = 62.41 kHz. To verify the last two posed variable-gain control non-inverting and inverting VMAPF circuits in Figure  Figures 9 and 10 show the frequency domain simulations of the non-inverting and in ing VMAPFs with an ideal pole frequency of 62.41 kHz, respectively. For a non-inve VMAPF pole frequency with a theoretical phase shift of 90°, the simulated pole frequ in Figure 9 is 60.3 kHz with an offset of −2.11 kHz. For an inverting VMAPF pole frequ with a theoretical phase shift of −90°, the simulated pole frequency in Figure 10 is kHz, and the offset is −1.91 kHz. A single grounded capacitor of 510 pF and three equal grounded resistors of 5 kΩ, and the last two proposed variable-gain control non-inverting and inverting VMAPF circuits, shown in Figure 3a

Experimental Results
To measure the gain and phase responses of the first-order VMAPF in the frequ domain, the receiver resolution bandwidth of the Keysight E5061B-3L5 network ana was fixed at 100 Hz. To measure circuits in time-domain input/output waveforms Tektronix AFG1022 signal generator applied 2.5 VPP to the first-order VMAPF circuits used an oscilloscope Tektronix DPO 2048B to measure. The Keysight-Agilent N9000A nal analyzer evaluated third-order intermodulation distortion (IMD3), third-order i cept (TOI), phase noise (PN), total harmonic distortion (THD), spurious-free dyn range (SFDR), and 1-dB compression point (P1dB) analysis. Figure 11 shows photogr of the top and bottom views of the non-inverting and inverting first-order VMAPF FQSO printed circuit board (PCB) hardware implementation. Figure 12 shows the ph graph of the hardware setup used to experimentally verify the performance of the posed circuits and shows the gain and phase responses in the frequency of the non-in ing VMAPF as a test case. The supply voltages for both the AD8130 and AD844 are ± The measured power dissipation of the proposed first-order VMAPF and second-o FQSO circuits is 0.6 W.

Experimental Results
To measure the gain and phase responses of the first-order VMAPF in the frequ domain, the receiver resolution bandwidth of the Keysight E5061B-3L5 network anal was fixed at 100 Hz. To measure circuits in time-domain input/output waveforms Tektronix AFG1022 signal generator applied 2.5 VPP to the first-order VMAPF circuits used an oscilloscope Tektronix DPO 2048B to measure. The Keysight-Agilent N9000A nal analyzer evaluated third-order intermodulation distortion (IMD3), third-order i cept (TOI), phase noise (PN), total harmonic distortion (THD), spurious-free dyn range (SFDR), and 1-dB compression point (P1dB) analysis. Figure 11 shows photogr of the top and bottom views of the non-inverting and inverting first-order VMAPF FQSO printed circuit board (PCB) hardware implementation. Figure 12 shows the ph graph of the hardware setup used to experimentally verify the performance of the posed circuits and shows the gain and phase responses in the frequency of the non-in ing VMAPF as a test case. The supply voltages for both the AD8130 and AD844 are ± The measured power dissipation of the proposed first-order VMAPF and second-o FQSO circuits is 0.6 W.

Experimental Results
To measure the gain and phase responses of the first-order VMAPF in the frequency domain, the receiver resolution bandwidth of the Keysight E5061B-3L5 network analyzer was fixed at 100 Hz. To measure circuits in time-domain input/output waveforms, the Tektronix AFG1022 signal generator applied 2.5 V PP to the first-order VMAPF circuits and used an oscilloscope Tektronix DPO 2048B to measure. The Keysight-Agilent N9000A signal analyzer evaluated third-order intermodulation distortion (IMD3), third-order intercept (TOI), phase noise (PN), total harmonic distortion (THD), spurious-free dynamic range (SFDR), and 1-dB compression point (P1dB) analysis. Figure 11 shows photographs of the top and bottom views of the non-inverting and inverting first-order VMAPFs or FQSO printed circuit board (PCB) hardware implementation. Figure 12 shows the photograph of the hardware setup used to experimentally verify the performance of the proposed circuits and shows the gain and phase responses in the frequency of the non-inverting VMAPF as a test case. The supply voltages for both the AD8130 and AD844 are ± 5 V. The measured power dissipation of the proposed first-order VMAPF and second-order FQSO circuits is 0.6 W.  To obtain fo = 62.41 kHz, a grounded capacitor of 510 pF and a grounded resistanc of 5 kΩ were chosen in Figure 2a,b. Figures 13 and 14 show the measured gain and phas frequency responses of the first two proposed circuits for the unity-gain of the non-inver ing VMAPF and the inverting VMAPF in Figure 2a and 2b, respectively. For the non-in verting VMAPF pole frequency with a theoretical phase shift of 90°, the measured pol frequency in Figure 13 is 65.29 kHz with an offset of 2.88 kHz. For the inverting VMAP pole frequency with a theoretical phase shift of −90°, the measured pole frequency in Fig  ure 14 is 65.09 kHz with an offset of 2.68 kHz. Figures 15 and 16 show the measured time domain input/output waveforms of the non-inverting and inverting VMAPF circuits o Figure 2a and 2b, respectively. At the pole frequency shown in Figure 15, the theoretica phase shift of the first-order non-inverting VMAPF is 90°; the measured phase shift i 89.81°, and the phase error is −0.19°. At the pole frequency shown in Figure 16, the theo retical phase shift of the first-order inverting VMAPF is −90°; the measured phase shift i  To obtain fo = 62.41 kHz, a grounded capacitor of 510 pF and a grounded resistanc of 5 kΩ were chosen in Figure 2a,b. Figures 13 and 14 show the measured gain and phas frequency responses of the first two proposed circuits for the unity-gain of the non-inver ing VMAPF and the inverting VMAPF in Figure 2a and 2b, respectively. For the non-in verting VMAPF pole frequency with a theoretical phase shift of 90°, the measured pol frequency in Figure 13 is 65.29 kHz with an offset of 2.88 kHz. For the inverting VMAP pole frequency with a theoretical phase shift of −90°, the measured pole frequency in Fig  ure 14 is 65.09 kHz with an offset of 2.68 kHz. Figures 15 and 16 show the measured time domain input/output waveforms of the non-inverting and inverting VMAPF circuits o Figure 2a and 2b, respectively. At the pole frequency shown in Figure 15, the theoretica phase shift of the first-order non-inverting VMAPF is 90°; the measured phase shift i 89.81°, and the phase error is −0.19°. At the pole frequency shown in Figure 16, the theo retical phase shift of the first-order inverting VMAPF is −90°; the measured phase shift i To obtain f o = 62.41 kHz, a grounded capacitor of 510 pF and a grounded resistance of 5 kΩ were chosen in Figure 2a,b. Figures 13 and 14 show the measured gain and phase frequency responses of the first two proposed circuits for the unity-gain of the noninverting VMAPF and the inverting VMAPF in Figures 2a and 2b, respectively. For the non-inverting VMAPF pole frequency with a theoretical phase shift of 90 • , the measured pole frequency in Figure 13 is 65.29 kHz with an offset of 2.88 kHz. For the inverting VMAPF pole frequency with a theoretical phase shift of −90 • , the measured pole frequency in Figure 14 is 65.09 kHz with an offset of 2.68 kHz. Figures 15 and 16 show the measured time-domain input/output waveforms of the non-inverting and inverting VMAPF circuits of Figures 2a and 2b, respectively. At the pole frequency shown in Figure 15, the theoretical phase shift of the first-order non-inverting VMAPF is 90 • ; the measured phase shift is 89.81 • , and the phase error is −0.19 • . At the pole frequency shown in Figure 16, the theoretical phase shift of the first-order inverting VMAPF is −90 • ; the measured phase shift is −88.15 • , and the phase error is 1.85 • .         A single grounded capacitor of 510 pF and three equal grounded resistors of 5 kΩ and the last two proposed variable-gain control non-inverting and inverting VMAPF circuits shown in Figure 3a A single grounded capacitor of 510 pF and three equal grounded resistors of 5 kΩ and the last two proposed variable-gain control non-inverting and inverting VMAPF ci cuits shown in Figure 3a,b, are designed for fo = 62.41 kHz. To verify the last two propose variable-gain control non-inverting and inverting VMAPF circuits in Figure 3a,b, Figure  17 and 18 show the frequency domain measurements of the non-inverting and invertin VMAPFs with an ideal pole frequency of 62.41 kHz, respectively. For a non-invertin VMAPF pole frequency with a theoretical phase shift of 90°, the measured pole frequenc in Figure 17 is 62.22 kHz with an offset of −0.19 kHz. For an inverting VMAPF pole fre quency with a theoretical phase shift of −90°, the measured pole frequency in Figure 18 63.78 kHz, and the offset is 1.37 kHz. Figures 19 and 20 show input/output waveforms i the time domain for the non-inverting and inverting VMAPF circuits of Figure 3a and 3b respectively. At the pole frequency shown in Figure 19, the theoretical phase shift of th first-order non-inverting VMAPF is 90°; the measured phase shift is 88.48°, and its phas error is −1.52°. At the pole frequency shown in Figure 20, the theoretical phase shift of th first-order inverting VMAPF is −90°; the measured phase shift is −93.26°, and its phas error is −3.26°.   Figure 3a with the starting frequency range from 1 kHz to 1 MHz. Figure 17. The frequency domain of the non-inverting VMAPF in Figure 3a with the starting fre quency range from 1 kHz to 1 MHz. Figure 18. The frequency domain of the inverting VMAPF in Figure 3b with the starting frequenc range from 1 kHz to 1 MHz. To evaluate the THD, SFDR, IMD3, TOI, PN, and P1dB analysis of the propose VMAPFs, the proposed paper investigated linearity, dynamic range, harmonic conten mixed, intermodulation linearity, phase noise analysis, and input power range. Figure  21 and 22 show the frequency spectrum of Figure 2a and 2b, respectively. In Figure 21, th calculated THD and measured SFDR values are 0.23% and 57.73 dB, respectively. In Fig  ure 22, the calculated THD and measured SFDR values are 0.29% and 55.59 dB, respec tively. Figures 23 and 24 show the THD analysis measured by the operating frequency o 62.41 kHz and the varying input voltage in Figure 2a and 2b, respectively. As shown i Figures 23 and 24, the measured THD is less than 1.13% when the input voltage signa reaches 3.5 Vpp. Figures 25 and 26 show the frequency spectrum of Figure 3a and 3b, re spectively. In Figure 25, the calculated THD and measured SFDR values are 0.5% an 49.81 dB, respectively. In Figure 26, the calculated THD and measured SFDR values ar To evaluate the THD, SFDR, IMD3, TOI, PN, and P1dB analysis of the propose VMAPFs, the proposed paper investigated linearity, dynamic range, harmonic conten mixed, intermodulation linearity, phase noise analysis, and input power range. Figure  21 and 22 show the frequency spectrum of Figure 2a and 2b, respectively. In Figure 21, th calculated THD and measured SFDR values are 0.23% and 57.73 dB, respectively. In Fig  ure 22, the calculated THD and measured SFDR values are 0.29% and 55.59 dB, respec tively. Figures 23 and 24 show the THD analysis measured by the operating frequency o 62.41 kHz and the varying input voltage in Figure 2a and 2b, respectively. As shown i Figures 23 and 24, the measured THD is less than 1.13% when the input voltage signa reaches 3.5 Vpp. Figures 25 and 26 show the frequency spectrum of Figure 3a and 3b, re spectively. In Figure 25, the calculated THD and measured SFDR values are 0.5% an 49.81 dB, respectively. In Figure 26, the calculated THD and measured SFDR values ar To evaluate the THD, SFDR, IMD3, TOI, PN, and P1dB analysis of the proposed VMAPFs, the proposed paper investigated linearity, dynamic range, harmonic content, mixed, intermodulation linearity, phase noise analysis, and input power range. Figures 21 and 22 show the frequency spectrum of Figures 2a and 2b, respectively. In Figure 21, the calculated THD and measured SFDR values are 0.23% and 57.73 dB, respectively. In Figure 22, the calculated THD and measured SFDR values are 0.29% and 55.59 dB, respectively. Figures 23 and 24 show the THD analysis measured by the operating frequency of 62.41 kHz and the varying input voltage in Figures 2a and 2b, respectively. As shown in Figures 23 and 24, the measured THD is less than 1.13% when the input voltage signal reaches 3.5 V pp . Figures 25 and 26 show the frequency spectrum of Figures 3a and 3b, respectively. In Figure 25, the calculated THD and measured SFDR values are 0.5% and 49.81 dB, respectively. In Figure 26, the calculated THD and measured SFDR values are 0.67% and 46.7 dB, respectively. Figures 27 and 28 show the measured THD analysis at an operating frequency of 62.41 kHz versus the varying input voltage in Figures 3a and 3b, respectively. As shown in Figures 27 and 28, the measured THD is less than 1.6% when the input voltage signal reaches 3.5 V pp . Figures 29-32 show the intermodulation linearity of the two-tone tests with f 1 = 61.41 kHz for the low-frequency tone and f 2 = 63.41 kHz for the high-frequency tone, respectively. In Figure 29, the measured IMD3 and TOI of Figure 2a are −57.42 dBc and 33.18 dBm, respectively. In Figure 30, the measured IMD3 and TOI of Figure 2b are −63.91 dBc and 35.18 dBm, respectively. In Figure 31, the measured IMD3 and TOI of Figure 3a are −65.69 dBc and 36.45 dBm, respectively. In Figure 32, the measured IMD3 and TOI of Figure 3b are −52.12 dBc and 31.1 dBm, respectively. Figures 33-36 show the PN analysis of approximately 11.6 dBm input carrier power. In Figure 33, the PN measured of Figure 2a at an offset of 100 Hz is −88.61 dBc/Hz. In Figure 34, the PN measured of Figure 2b at an offset of 100 Hz is −89.07 dBc/Hz. In Figure 35, the PN measured of Figure 3a at an offset of 100 Hz is −84.38 dBc/Hz. In Figure 36, the PN measured of Figure 3b at an offset of 100 Hz is −82.68 dBc/Hz. Figures 37-40 show the input power range for P1dB, respectively. In Figure 37, the input P1dB of Figure 2a is 19.6 dBm. In Figure 38, the input P1dB of Figure 2b is 19.4 dBm. In Figure 39, the input P1dB of Figure 3a is 19 dBm. In Figure 40, the input P1dB of Figure 3b is 19.6 dBm.  Figure 39, the input P1dB of Figure  3a is 19 dBm. In Figure 40, the input P1dB of Figure 3b is 19.6 dBm.   Figure 39, the input P1dB of Figure  3a is 19 dBm. In Figure 40, the input P1dB of Figure 3b is 19.6 dBm.                                     To evaluate the performance of the proposed VMAPF, the figure of merit (FoM) is defined as [42] According to Equation (22), the FoM of the VMAPFs presented in Figure 2a, Figure 2b, Figure 3a, and Figure 3b are 628.2 × 10 3 , 603.06 × 10 3 , 516.53 × 10 3 , and 496.42 × 10 3 , respectively. The summary performance of the proposed VMAPFs is given in Table 2. Table 2. Performance parameters of the proposed VMAPFs.  To confirm the cascading characteristics, an application example of FQSO in Figure 5 was also studied. The FQSO in Figure 5 was designed with equal capacitor of value 510 pF, R 1 = R 2 = R 4 = R 5 = R 6 = 5 kΩ, and R 3 = 6.2 kΩ. Figure 41 shows the time domain measurements of the quadrature sinusoidal outputs V o1 and V o2 , and the measured oscillation frequency is 59.05 kHz, which is close to the theoretical value of 62.41 kHz. The Fourier spectrum of the quadrature outputs is shown in Figures 42a and 42b, respectively. In Figure 42a, the calculated THD and measured SFDR of V o1 output value are 0.8% and 42.88 dB, respectively. In Figure 42b, the calculated THD and measured SFDR of V o2 output value are 0.5% and 45.6 dB, respectively. The PN measured of FQSO is shown in Figures 43a and 43b, respectively. At an offset of 100 Hz, the measured V o1 and V o2 PN are −32.32 dBc/Hz and −32.98 dBc/Hz, respectively. Figure 44 shows the experimental results of the oscillation frequencies of Figure 5 by varying the values of R 1 = R 4 with the equal capacitor of value 510 pF, R 2 = R 5 = R 6 = 5 kΩ, and R 3 = R 6 = 6.2 kΩ. To confirm the cascading characteristics, an application example of FQSO in Figure  5 was also studied. The FQSO in Figure 5 was designed with equal capacitor of value 510 pF, R1 = R2 = R4 = R5 = R6 = 5 kΩ, and R3 = 6.2 kΩ. Figure 41 shows the time domain measurements of the quadrature sinusoidal outputs Vo1 and Vo2, and the measured oscillation frequency is 59.05 kHz, which is close to the theoretical value of 62.41 kHz. The Fourier spectrum of the quadrature outputs is shown in Figure 42a and 42b, respectively. In Figure  42a, the calculated THD and measured SFDR of Vo1 output value are 0.8% and 42.88 dB, respectively. In Figure 42b, the calculated THD and measured SFDR of Vo2 output value are 0.5% and 45.6 dB, respectively. The PN measured of FQSO is shown in Figure 43a and 43b, respectively. At an offset of 100 Hz, the measured Vo1 and Vo2 PN are −32.32 dBc/Hz and −32.98 dBc/Hz, respectively. Figure 44 shows the experimental results of the oscillation frequencies of Figure

Comparison of VMAPF Theoretical, Simulation, and Experimental Results
To demonstrate the theoretical study of the four VMAPFs, the theoretical analysis of Equations (10), (14), (15) and (17) Figure 11. Figures 45 and 46 show the theoretical analysis in Matlab and the simulated and measured responses of the first two proposed non-inverting and inverting VMAPF circuits, respectively. Figures 47 and 48 show the simulation and measurement responses of the last two proposed variable-gain control non-inverting and inverting VMAPF circuits, as well as the theoretical analysis in Matlab. In order to illustrate the adjustable features of circuits in Figure 3a,b, R 3 and R 6 were changed to 3.15 kΩ, 6.3 kΩ, 10 kΩ, and 15.8 kΩ to obtain −4 dB, 2 dB, 6 dB, and 10 dB corresponding gains, while maintaining C 1 = C 2 = 510 pF and R 1 = R 2 = R 4 = R 5 = 5kΩ. Figures 49 and 50 show the theoretical analysis in Matlab and the simulated and measured variable-gain control without affecting the phase responses in Figures 3a and 3b, respectively. In order to illustrate the adjustable characteristics of the structure displayed, R 1 in Figure 3a and R 4 in Figure 3b were changed to 2.5 kΩ, 4 kΩ, 7.5 kΩ, and 15 kΩ to obtain 124.82 kHz, 78.43 kHz, 41.6 kHz, and 20.8 kHz corresponding to f o , while maintaining C 1 = C 2 = 510 pF and R 2 = R 3 = R 5 = R 6 = 5 kΩ. Figures 51 and 52 show the theoretical analysis in Matlab and the simulated and measured tunable phase response without affecting the gain in Figures 3a and 3b, respectively. These results show that each structure proposed in Figure 3a,b has variable-gain control without affecting the pole frequency. The experimental and simulation results show that Figures 45 and 52 are in good agreement with the predicted theory, confirming the feasibility of the four proposed VMAPF configurations. However, the differences among the theoretical, simulated, and measured results of the four proposed VMAPFs mainly come from the parasitic impedance effects of active components, passive component tolerances, and PCB circuit layout. To evaluate the difference in the phase shift results of the active and passive components, the sensitivity of the pole angular frequency ω o and gain k parameters of the VMAPF with respect to the passive components of R and C were analyzed using the sensitivity definitions. The sensitivity is defined as [28]

Conclusions
In 2022, Abaci et al. proposed two VMAPFs based on single-modified DDCC−. The first proposed VMAPF uses a modified DDCC−, two grounded capacitors, and a floating resistor, while the second one uses a grounded capacitor, a grounded resistor, and a floating resistor. Both proposed VMAPFs have HI impedance, but they require passive component matching conditions to achieve the VMAPFs and do not offer variable-gain control and LI impedance. In this paper, four new designs for a first-order VMAPF circuit based on two DVCCs are presented. The four proposed VMAPF circuits offer the following attractive features simultaneously: (i) Only GC and GR are used to absorb shunt parasitic capacitances and resistances. (ii) The HI impedance is easily cascaded with other VM circuits without the need for an input voltage buffer. (iii) Inverting APF and non-inverting APF functions do not require matching conditions for passive components. In addition the first two proposed VMAPFs with LO impedance are beneficial for output cascading and the latter two proposed VMAPFs with variable-gain control are beneficial for filtergain controllability. Furthermore, the application as FQSO by cascading the inverting APF and non-inverting APF techniques is discussed. The measured input 1-dB compression point of the four VMAPFs is about 19 dB. The measured THD of the four VMAPFs is less than 0.67% when the input voltage reaches 2.5 Vpp. The calculated figures of merit for the four VMAPFs are 628.2 × 10 3 , 603.06 × 10 3 , 516.53 × 10 3 , and 496.42 × 10 3 , respectively. The simulation and measurement results are consistent with theoretical predictions.

Conclusions
In 2022, Abaci et al. proposed two VMAPFs based on single-modified DDCC−. The first proposed VMAPF uses a modified DDCC−, two grounded capacitors, and a floating resistor, while the second one uses a grounded capacitor, a grounded resistor, and a float ing resistor. Both proposed VMAPFs have HI impedance, but they require passive com ponent matching conditions to achieve the VMAPFs and do not offer variable-gain contro and LI impedance. In this paper, four new designs for a first-order VMAPF circuit based on two DVCCs are presented. The four proposed VMAPF circuits offer the following at tractive features simultaneously: (i) Only GC and GR are used to absorb shunt parasitic capacitances and resistances. (ii) The HI impedance is easily cascaded with other VM cir cuits without the need for an input voltage buffer. (iii) Inverting APF and non-inverting APF functions do not require matching conditions for passive components. In addition the first two proposed VMAPFs with LO impedance are beneficial for output cascading and the latter two proposed VMAPFs with variable-gain control are beneficial for filter gain controllability. Furthermore, the application as FQSO by cascading the inverting APF and non-inverting APF techniques is discussed. The measured input 1-dB compression point of the four VMAPFs is about 19 dB. The measured THD of the four VMAPFs is less than 0.67% when the input voltage reaches 2.5 Vpp. The calculated figures of merit for the four VMAPFs are 628.2 × 10 3 , 603.06 × 10 3 , 516.53 × 10 3 , and 496.42 × 10 3 , respectively. The simulation and measurement results are consistent with theoretical predictions. In Equation (23), F represents one of the pole angular frequencies ω o ; the gain is k, and x represents the passive component of resistor R or capacitor C. Based on Equation (23), the low passive sensitivity of the four VMAPFs is calculated as Non-inverting unity-gain VMAPF : Inverting unity-gain VMAPF : S ω o R 4 = S ω o C 2 = −1 (25) Non-inverting variable-gain VMAPF : Inverting variable-gain VMAP : S ω o R 4 = S ω o C 2 = −1, S k R 5 = −1, S k R 6 = 1 (27) According to Equations (24)- (27), the four proposed VMAPFs have a low passive sensitivity.

Conclusions
In 2022, Abaci et al. proposed two VMAPFs based on single-modified DDCC−. The first proposed VMAPF uses a modified DDCC−, two grounded capacitors, and a floating resistor, while the second one uses a grounded capacitor, a grounded resistor, and a floating resistor. Both proposed VMAPFs have HI impedance, but they require passive component matching conditions to achieve the VMAPFs and do not offer variable-gain control and LI impedance. In this paper, four new designs for a first-order VMAPF circuit based on two DVCCs are presented. The four proposed VMAPF circuits offer the following attractive features simultaneously: (i) Only GC and GR are used to absorb shunt parasitic capacitances and resistances. (ii) The HI impedance is easily cascaded with other VM circuits without the need for an input voltage buffer. (iii) Inverting APF and non-inverting APF functions do not require matching conditions for passive components. In addition, the first two proposed VMAPFs with LO impedance are beneficial for output cascading, and the latter two proposed VMAPFs with variable-gain control are beneficial for filter-gain controllability. Furthermore, the application as FQSO by cascading the inverting APF and non-inverting APF techniques is discussed. The measured input 1-dB compression point of the four VMAPFs is about 19 dB. The measured THD of the four VMAPFs is less than 0.67% when the input voltage reaches 2.5 V pp . The calculated figures of merit for the four VMAPFs are 628.2 × 10 3 , 603.06 × 10 3 , 516.53 × 10 3 , and 496.42 × 10 3 , respectively. The simulation and measurement results are consistent with theoretical predictions.