A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.


Introduction
For low-power applications, a Successive Approximation Register (SAR) analogto-digital converter (ADC) is a good choice to obtain successive digital code from an analog input by using the binary search algorithm. Due to its simplicity and power efficiency, SAR ADC is more popular and favorable for comparison with other types of ADCs [1][2][3]. Traditionally, pipeline ADCs have been frequently used for high-speed and medium-resolution data converters. However, the down-scaling of CMOS technologies and reduction in the power supply voltages arouses some significant obstacles for the power-efficient design of pipeline ADCs, because pipeline ADCs have need for high-gain operational amplifiers, which increases the power consumption of pipeline ADCs. In addition to this, it also degrades the swing of amplifiers, which results in the reduction of the Signal-to-Noise Ratio (SNR) for the provided sampling capacitance value. Additionally, the operational amplifier needs to have high DC gain, which lowers the power efficiency because of the low output resistance from short-channel-length devices. On the other hand, SAR ADCs abolish the requirement for an operational amplifier and can attain magnificent power efficiency [4,5]. According to the present trend, SAR ADC provides a sampling speed

Proposed ADC Architecture
The proposed single-ended asynchronous SAR ADC topology is designed and fabricated for a 10-bit resolution with a sampling speed of 1 MS/s, and the architecture is presented in Figure 1. The proposed SAR ADC contains a binary weighted capacitive DAC, a bootstrap switch, dynamic comparator, asynchronous SAR logic with an internal comparator clock generator, and a bandgap reference generator. A dual-path bootstrap switch is presented that overcomes the sampling nonlinearity. The VCM-based switching sequence is proposed, which reduces the capacitive DAC's total capacitance by half due to the additional reference of VCM. Owing not only to the reduced capacitance, but also to the reduced switching step size as well as the removed switching-back operation, the VCM-based CDAC switching achieves excellent energy efficiency. The capacitive DAC is controlled by the digital output code, which is stored by asynchronous SAR logic and the decision made by the comparator. In the proposed single-ended asynchronous SAR ADC, a reference voltage of 0.6 V is generated by the error amplifier (EA)-based bandgap reference voltage generator. The 10-bit capacitive DAC provides the reference voltage DACP to the one input of the comparator, and the other input comparator has common-mode voltage (VCM). The sampling and hold operation is conducted by the sampling switch and capacitive DAC capacitors. The sampling signal, DACP<9:0>, CCLK, and SSAM are the control signals generated from the asynchronous SAR logic. The CCLK signal is provided to the comparator for the fast comparison of the comparator. For high speed and power efficiency, we implemented a two-stage dynamic latch comparator. In addition to this, for practical use, we implemented an on-chip bandgap reference voltage generator that provides better stability and reduced offset voltage distribution. a reference voltage of 0.6 V is generated by the error amplifier (EA)-based bandgap reference voltage generator. The 10-bit capacitive DAC provides the reference voltage DACP to the one input of the comparator, and the other input comparator has common-mode voltage (VCM). The sampling and hold operation is conducted by the sampling switch and capacitive DAC capacitors. The sampling signal, DACP<9:0>, CCLK, and SSAM are the control signals generated from the asynchronous SAR logic. The CCLK signal is provided to the comparator for the fast comparison of the comparator. For high speed and power efficiency, we implemented a two-stage dynamic latch comparator. In addition to this, for practical use, we implemented an on-chip bandgap reference voltage generator that provides better stability and reduced offset voltage distribution.

Bootstrap Switching
Nowadays, for linear sampling, a bootstrap switch is frequently used, and its nonidealities have become pronounced; thus, its linearity is seriously degrading. Several techniques have been used to improve the performance of the bootstrap switch, such as modifying the circuit network or incorporating fast-turn-on circuits [13]. In Figure 2, we propose a technique to improve the linearity of the bootstrap switch. Ideally, to achieve the constant switch on-conductance, the Vgs of the sampling transistor M10 is independent of and constant with the input. The proposed technique integrates the dual-path bootstrap switch to improve the sampling nonlinearity, and operates at the sampling rate of 1 MS/s, with a 50% duty cycle and peak-to-peak voltage of 600 mV, as shown in Figure 2. This technique creates two paths for the signal; one is the main path, which contains M2 and C2, and the other is an auxiliary path, which contains M1 and C1. In the auxiliary path, the PMOS transistor's M1, M2, and M4's bulk terminals are connected to the VX node, which prevents forward biasing. By the proposed dual-path bootstrap switching technique, the nonlinear capacitance drives through the auxiliary path, while the gate of the sampling switch propagates the input signal, and hence the nonlinear capacitance is not directly being loaded into the main path. In this way, we can maximize the drive strength

Bootstrap Switching
Nowadays, for linear sampling, a bootstrap switch is frequently used, and its nonidealities have become pronounced; thus, its linearity is seriously degrading. Several techniques have been used to improve the performance of the bootstrap switch, such as modifying the circuit network or incorporating fast-turn-on circuits [13]. In Figure 2, we propose a technique to improve the linearity of the bootstrap switch. Ideally, to achieve the constant switch on-conductance, the Vgs of the sampling transistor M10 is independent of and constant with the input. The proposed technique integrates the dual-path bootstrap switch to improve the sampling nonlinearity, and operates at the sampling rate of 1 MS/s, with a 50% duty cycle and peak-to-peak voltage of 600 mV, as shown in Figure 2. This technique creates two paths for the signal; one is the main path, which contains M2 and C2, and the other is an auxiliary path, which contains M1 and C1. In the auxiliary path, the PMOS transistor's M1, M2, and M4's bulk terminals are connected to the V X node, which prevents forward biasing. By the proposed dual-path bootstrap switching technique, the nonlinear capacitance drives through the auxiliary path, while the gate of the sampling switch propagates the input signal, and hence the nonlinear capacitance is not directly being loaded into the main path. In this way, we can maximize the drive strength and signal linearity by independently optimizing the auxiliary path and the main path. The formula for voltage transfer to V g from VIN and its phase are expressed as follows: where R 4 = 1/G4, G4 is the on conductance of transistor M4, and Cg is the gate capacitance of transistor M10. By the proposed bootstrap switch, G4 is more linear because, instead of the supply voltage VDD, the bulk of M4 is connected to the nonlinear voltage V X . Therefore, the square root of the error of nonlinear voltage V X is directly proportional to G4. Hence, to improve the nonlinearity, the nonlinear voltage V X goes through the bulk of M4, and nonlinear parasitic capacitance from the main path is removed by C2.
where R4 = 1/G4, G4 is the on conductance of transistor M4, and Cg is the gate capacitance of transistor M10. By the proposed bootstrap switch, G4 is more linear because, instead of the supply voltage VDD, the bulk of M4 is connected to the nonlinear voltage VX. Therefore, the square root of the error of nonlinear voltage VX is directly proportional to G4. Hence, to improve the nonlinearity, the nonlinear voltage VX goes through the bulk of M4, and nonlinear parasitic capacitance from the main path is removed by C2.

Capacitive DAC
Various circuit techniques could further enhance the low power advantage of SAR ADCs. A large amount of research has been conducted to save the CDAC's switching power consumption. Unlike the traditional SAR ADC architecture with two voltage references, the VCM-based switching scheme proposed could reduce the total capacitance of the CDAC by half due to the additional reference of VCM. It does not only reduce the overall CDAC capacitance, but also reduces the switching step size. With the removed switching-back operation, the VCM-based CDAC switching could achieve excellent energy efficiency and become popular for low-power designs. One drawback of the VCMbased switching scheme might be the difficulty in designing low-resistance switches for

Capacitive DAC
Various circuit techniques could further enhance the low power advantage of SAR ADCs. A large amount of research has been conducted to save the CDAC's switching power consumption. Unlike the traditional SAR ADC architecture with two voltage references, the VCM-based switching scheme proposed could reduce the total capacitance of the CDAC by half due to the additional reference of VCM. It does not only reduce the overall CDAC capacitance, but also reduces the switching step size. With the removed switching-back operation, the VCM-based CDAC switching could achieve excellent energy efficiency and become popular for low-power designs. One drawback of the VCM-based switching scheme might be the difficulty in designing low-resistance switches for VCM. The monotonic switching technique can eliminate the need for VCM by the asymmetric CDAC switching, but this scheme has a varying common-level problem [14,15]. The energysaving switching technique could implement VCM-based-like switching behavior without utilizing VCM by splitting each capacitor in half. The improved process controllability of advanced CMOS technologies also contributed to reducing the CDAC switching power consumption by decreasing the minimum unit capacitor values without the need for a dedicated process for capacitor implementation.
The proposed CDAC switching with the binary weighted array used in the singleended SAR ADC is depicted in Figure 3. In the sampling phase, the bottom plates of all capacitors are connected to the VCM and the top plates are connected to the VIN. Thus, the input voltage is sampled on the binary weighted capacitor array, and we obtain the first signed bit without consuming any switching energy. Depending on the first signed bit, the next conversion cycle is either charged to VDD or discharged to VSS from VCM. Hence, the MSB capacitor is not required in the proposed switching scheme. The sensitivity due to the capacitor mismatch, dynamic, and static performance of the proposed capacitive DAC switching scheme is checked based upon the behavioral simulation in MATLAB. The fast Fourier transform (FFT) spectrum of the behavioral model-level simulation is evaluated in MATLAB ® for the proposed switching architecture with 1% unit capacitor mismatch, as shown in Figure 4. The static performance metrics, differential non-linearity (DNL), and the integral non-linearity (INL) of the proposed switching with 1% unit capacitor mismatch are shown in Figure 5a,b respectively. switching power consumption by decreasing the minimum unit capacitor values without the need for a dedicated process for capacitor implementation.
The proposed CDAC switching with the binary weighted array used in the singleended SAR ADC is depicted in Figure 3. In the sampling phase, the bottom plates of all capacitors are connected to the VCM and the top plates are connected to the VIN. Thus, the input voltage is sampled on the binary weighted capacitor array, and we obtain the first signed bit without consuming any switching energy. Depending on the first signed bit, the next conversion cycle is either charged to VDD or discharged to VSS from VCM. Hence, the MSB capacitor is not required in the proposed switching scheme. The sensitivity due to the capacitor mismatch, dynamic, and static performance of the proposed capacitive DAC switching scheme is checked based upon the behavioral simulation in MATLAB. The fast Fourier transform (FFT) spectrum of the behavioral model-level simulation is evaluated in MATLAB ® for the proposed switching architecture with 1% unit capacitor mismatch, as shown in Figure 4. The static performance metrics, differential non-linearity (DNL), and the integral non-linearity (INL) of the proposed switching with 1% unit capacitor mismatch are shown in Figure 5a,b respectively.       Figure 6 shows the output of the capacitive DAC (DACP) settling of input signals according to the clock signal. An end-of-conversion (EOC) signal will be generated after the completion of the conversion cycle based on the asynchronous SAR logic.     Figure 6 shows the output of the capacitive DAC (DACP) settling of input signals according to the clock signal. An end-of-conversion (EOC) signal will be generated after the completion of the conversion cycle based on the asynchronous SAR logic.

Two-Stage Dynamic Comparator
In the proposed two-stage dynamic latched comparator, two inverters are added to make the V i node's voltage strong by providing a higher regeneration speed, as shown in Figure 7. The proposed architecture of the two-stage dynamic latch comparator provides high speed and power efficiency, and lowers the input-referred offset compared with conventional comparator architecture [16][17][18]. When the clock signal CCLK is turned off, the PMOS transistors M11 and M12 are on, then the V i nodes are charged to VDD, and VB i nodes are discharged to VSS during the reset phase. Consequently, there is no static power dissipation and static path due to charge sharing, and no DC flows in the static state of the proposed comparator. The NMOS transistors M9 and M10 drain, and output nodes charge to VDD, while the PMOS transistors of the regeneration stage turn on, and the VB i nodes discharge to VSS.
In the evaluation phase, when the clock signal CCLK increases, the V i nodes discharge to VSS depending on the input voltage through the input transistors M13 and M14, and the tail transistor M15. The VB i nodes are charged from VSS to VDD, while the V i nodes are discharged to VSS in the evaluation phase. Other transistors will be turned on when the NMOS transistors M9 and M10 are turned on in the second stage and either of the VBi nodes reaches the threshold voltage V th . Consequently, the latch is activated and regenerates the digital voltage at the output. make the Vi node's voltage strong by providing a higher regeneration speed, as shown in Figure 7. The proposed architecture of the two-stage dynamic latch comparator provides high speed and power efficiency, and lowers the input-referred offset compared with conventional comparator architecture [16][17][18]. When the clock signal CCLK is turned off, the PMOS transistors M11 and M12 are on, then the Vi nodes are charged to VDD, and VBi nodes are discharged to VSS during the reset phase. Consequently, there is no static power dissipation and static path due to charge sharing, and no DC flows in the static state of the proposed comparator. The NMOS transistors M9 and M10 drain, and output nodes charge to VDD, while the PMOS transistors of the regeneration stage turn on, and the VBi nodes discharge to VSS. In the evaluation phase, when the clock signal CCLK increases, the Vi nodes discharge to VSS depending on the input voltage through the input transistors M13 and M14, and the tail transistor M15. The VBi nodes are charged from VSS to VDD, while the Vi nodes are discharged to VSS in the evaluation phase. Other transistors will be turned on when the NMOS transistors M9 and M10 are turned on in the second stage and either of the VBi nodes reaches the threshold voltage Vth. Consequently, the latch is activated and regenerates the digital voltage at the output.

Asynchronous SAR Logic and Comparator Clock Generator
To achieve faster bit conversion with an efficient time sequence, asynchronous SAR ADC is more popular [19,20]. Asynchronous SAR logic with an internally generated clock avoids the requirement for the high-frequency external clock, as all conversions are carried out in a single clock cycle. Asynchronous SAR control logic is implemented for a shorter critical path.
A clock generator for SAR control logic is proposed, as shown in Figure 8a. The asynchronous clock generator consists of a delay cell, variable delay, an edge counter, delay adjust block, and logic gates. VCOMP or VCOMN are low, which allows VI to decrease after the decision of the comparator. Then, after the variable delay, VO is also low, which makes the CCLK decrease, and the SAR logic controller is triggered. The comparator starts the comparison when the reset of the comparator is completed, and VI, VO, and CCLK increase. To maximize the sampling period of conversion and to adjust the time delay, the delay adjust block and counter are used in feedback.
CCLK provides the reset time of the comparator and more time for DAC settling, as shown in Figure 8b. The proposed clock generator eliminates the memory effect in the comparator and speeds up the bit conversion. Hence, it also helps to improve the ADC robustness. The timing diagram of the proposed clock generator is shown in Figure 8b. The comparator's decision time and reset time are represented as T1 and T2, respectively. D1 and D2 are the delay time, and unequal D1 and D2 can be obtained by the variable delay cell, as depicted in Figure 9. The variable delay cell is composed of an inverter array, implemented to achieve the desired variable delay. The arrangement of the inverter array leads the delay D1 to be small for the falling edge from VI to VO and delay D2 to be large for the rising edge.
ADC is more popular [19,20]. Asynchronous SAR logic with an internally generated clock avoids the requirement for the high-frequency external clock, as all conversions are carried out in a single clock cycle. Asynchronous SAR control logic is implemented for a shorter critical path.
A clock generator for SAR control logic is proposed, as shown in Figure 8a. The asynchronous clock generator consists of a delay cell, variable delay, an edge counter, delay adjust block, and logic gates. VCOMP or VCOMN are low, which allows VI to decrease after the decision of the comparator. Then, after the variable delay, VO is also low, which makes the CCLK decrease, and the SAR logic controller is triggered. The comparator starts the comparison when the reset of the comparator is completed, and VI, VO, and CCLK increase. To maximize the sampling period of conversion and to adjust the time delay, the delay adjust block and counter are used in feedback. CCLK provides the reset time of the comparator and more time for DAC settling, as shown in Figure 8b. The proposed clock generator eliminates the memory effect in the comparator and speeds up the bit conversion. Hence, it also helps to improve the ADC robustness. The timing diagram of the proposed clock generator is shown in Figure 8b. The comparator's decision time and reset time are represented as T1 and T2, respectively. D1 and D2 are the delay time, and unequal D1 and D2 can be obtained by the variable delay cell, as depicted in Figure 9. The variable delay cell is composed of an inverter array, implemented to achieve the desired variable delay. The arrangement of the inverter array leads the delay D1 to be small for the falling edge from VI to VO and delay D2 to be large for the rising edge.

Error Amplifier-Based Bandgap Reference Voltage Generator
Reference voltage generators are required to stabilize the overall PVT variation, and also need to be implemented without modifying the fabrication process [21][22][23]. The bandgap reference voltage generator (BGR) is a popular reference voltage generator that successfully achieves the requirements [24,25]. Low power and low voltage operation are the characteristics of reference voltage generators. The error amplifier feedback keeps the same voltage level at both inputs of EA, and R3 generates the voltage difference between the two BJTs, as represented in Figure 10. A Soft-Start circuit is added to the output; when the power signal is high, a current starts to flow through the PMOSs, M11, M12, and M13 connected in diode fashion. To prevent the BGR peak voltage, it slowly charges the capacitor C3, and the BGR output voltage rises. The output of the error amplifier controls the gate of transistors M1 and M3 so that the input voltages of the error amplifier are equal. The positive feedback and negative feedback improve the loop stability of the proposed error amplifier. A detailed schematic of the error amplifier-based BGR circuit is shown in Figure 11a. VB1, VB2, and VB3 are the biasing voltages provided by the bias circuit to the cascaded error amplifier. We assume that the transistors M15-M18 and M23 are matched in terms of their aspect ratios, and the drain current of M18 is represented as:

Error Amplifier-Based Bandgap Reference Voltage Generator
Reference voltage generators are required to stabilize the overall PVT variation, and also need to be implemented without modifying the fabrication process [21][22][23]. The bandgap reference voltage generator (BGR) is a popular reference voltage generator that successfully achieves the requirements [24,25]. Low power and low voltage operation are the characteristics of reference voltage generators. The error amplifier feedback keeps the same voltage level at both inputs of EA, and R3 generates the voltage difference between the two BJTs, as represented in Figure 10. A Soft-Start circuit is added to the output; when the power signal is high, a current starts to flow through the PMOSs, M11, M12, and M13 connected in diode fashion. To prevent the BGR peak voltage, it slowly charges the capacitor C3, and the BGR output voltage rises. The output of the error amplifier controls the gate of transistors M1 and M3 so that the input voltages of the error amplifier are equal. The positive feedback and negative feedback improve the loop stability of the proposed error amplifier. A detailed schematic of the error amplifier-based BGR circuit is shown in Figure 11a. VB1, VB2, and VB3 are the biasing voltages provided by the bias circuit to the cascaded error amplifier. We assume that the transistors M15-M18 and M23 are matched in terms of their aspect ratios, and the drain current of M18 is represented as: same voltage level at both inputs of EA, and R3 generates the voltage difference between the two BJTs, as represented in Figure 10. A Soft-Start circuit is added to the output; when the power signal is high, a current starts to flow through the PMOSs, M11, M12, and M13 connected in diode fashion. To prevent the BGR peak voltage, it slowly charges the capacitor C3, and the BGR output voltage rises. The output of the error amplifier controls the gate of transistors M1 and M3 so that the input voltages of the error amplifier are equal. The positive feedback and negative feedback improve the loop stability of the proposed error amplifier. A detailed schematic of the error amplifier-based BGR circuit is shown in Figure 11a. VB1, VB2, and VB3 are the biasing voltages provided by the bias circuit to the cascaded error amplifier. We assume that the transistors M15-M18 and M23 are matched in terms of their aspect ratios, and the drain current of M18 is represented as: Figure 10. Schematic of BGR.   m16  m24  18  17  15  16  24  THn  ds23  THp   g  g  I  I  I  I  I

VBGR
Initially, Voff caused the output offset current Ioff of the proposed error amplifier cir-   Initially, V off caused the output offset current I off of the proposed error amplifier circuit shown in Figure 11b. Between the feedback stage and cascade stage output, OUT triggers the two opposite currents. The offset currents I 18 and I 20 are the positive feedback path and negative feedback path, respectively, and act contrary to each other. Therefore, the output offset current I off is expressed as follows: where V ov is the overdrive voltage; V ov = OUT − V TH and I 20 = g m V off /2. By carefully setting the overdrive voltage V ov and transconductance g m , we can alleviate the output offset current I off , as estimated by Equation (5). We assume that all transistors' transconductance is the same; then Equation (5) can be expressed as: Equation (6) represents that we can reduce the output offset current I off by adjusting the V ov22 to V ov16 + V off . This type of reduction in the output offset current I off can be achieved by inducing the intentional feedback loop in the proposed error amplifier. The Monte Carlo simulation of the proposed error amplifier-based bandgap reference voltage generator is depicted in Figure 12. An on-chip voltage generator with a standard deviation of less than 1 LSB is used in the proposed ADC architecture.
Equation (6) represents that we can reduce the output offset current Ioff by adjusting the Vov22 to Vov16 + Voff. This type of reduction in the output offset current Ioff can be achieved by inducing the intentional feedback loop in the proposed error amplifier. The Monte Carlo simulation of the proposed error amplifier-based bandgap reference voltage generator is depicted in Figure 12. An on-chip voltage generator with a standard deviation of less than 1 LSB is used in the proposed ADC architecture.

Measurement Results
The proposed SAR ADC architecture with VBGR was implemented and tested with TSMC 130 nm CMOS technology. Figure 13 represents a die photograph of the asynchronous SAR ADC with VBGR. The measured dynamic performance of the ADC at 153.32 kHz and 450.19 kHz input frequencies with a sampling rate of 1 MS/s is presented in Figure 14a,b, respectively. The proposed SAR ADC architecture achieved 9.49-bit ENOB and 58.88 dB SNDR with an input frequency of 153.32 kHz, as shown in Figure 14a, and 8.94bit ENOB and SNDR of 55.62 db with an input frequency of 450.19 kHz at 1 MS/s sampling speed, as shown in Figure 14b.

Measurement Results
The proposed SAR ADC architecture with VBGR was implemented and tested with TSMC 130 nm CMOS technology. Figure 13 represents a die photograph of the asynchronous SAR ADC with VBGR. The measured dynamic performance of the ADC at 153.32 kHz and 450.19 kHz input frequencies with a sampling rate of 1 MS/s is presented in Figure 14a,b, respectively. The proposed SAR ADC architecture achieved 9.49-bit ENOB and 58.88 dB SNDR with an input frequency of 153.32 kHz, as shown in Figure 14a, and 8.94-bit ENOB and SNDR of 55.62 db with an input frequency of 450.19 kHz at 1 MS/s sampling speed, as shown in Figure 14b.
TSMC 130 nm CMOS technology. Figure 13 represents a die photograph of the asynchronous SAR ADC with VBGR. The measured dynamic performance of the ADC at 153.32 kHz and 450.19 kHz input frequencies with a sampling rate of 1 MS/s is presented in Figure 14a,b, respectively. The proposed SAR ADC architecture achieved 9.49-bit ENOB and 58.88 dB SNDR with an input frequency of 153.32 kHz, as shown in Figure 14a, and 8.94bit ENOB and SNDR of 55.62 db with an input frequency of 450.19 kHz at 1 MS/s sampling speed, as shown in Figure 14b.  To check the linearity or the static performance of the proposed SAR ADC, the measured DNL and INL results are presented in Figure 15. The measured DNL and INL were −0.57/0.58 LSB and −0.72/0.55 LSB, respectively. The ENOB trend of the proposed ADC with an on-chip EA-based bandgap reference voltage generator is depicted in Figure  16a,b, representing the power breakdown of the proposed EA-based bandgap reference voltage generator. Table 1 summarizes the performance of the proposed SAR ADC architecture and compares it with the other state-of-the-art SAR ADC architectures. The figure of Merit (FOM) is generally used to check the overall performance of ADC, and the FOM can be evaluated as below: where the sampling rate is presented as FS, bandwidth of ADC is denoted as BW, and power consumed by the proposed ADC is represented as PowerADC. The proposed SAR ADC architecture achieved a FOM of 66.25 fJ/conv-step.  To check the linearity or the static performance of the proposed SAR ADC, the measured DNL and INL results are presented in Figure 15. The measured DNL and INL were −0.57/0.58 LSB and −0.72/0.55 LSB, respectively. The ENOB trend of the proposed ADC with an on-chip EA-based bandgap reference voltage generator is depicted in Figure 16a,b, representing the power breakdown of the proposed EA-based bandgap reference voltage generator. Table 1 summarizes the performance of the proposed SAR ADC architecture and compares it with the other state-of-the-art SAR ADC architectures. The figure of Merit (FOM) is generally used to check the overall performance of ADC, and the FOM can be evaluated as below: FOM = Power ADC min(F S , 2 × BW)2 ENOB (7) where the sampling rate is presented as F S , bandwidth of ADC is denoted as BW, and power consumed by the proposed ADC is represented as Power ADC . The proposed SAR ADC architecture achieved a FOM of 66.25 fJ/conv-step. To check the linearity or the static performance of the proposed SAR ADC, the measured DNL and INL results are presented in Figure 15. The measured DNL and INL were −0.57/0.58 LSB and −0.72/0.55 LSB, respectively. The ENOB trend of the proposed ADC with an on-chip EA-based bandgap reference voltage generator is depicted in Figure  16a,b, representing the power breakdown of the proposed EA-based bandgap reference voltage generator. Table 1 summarizes the performance of the proposed SAR ADC architecture and compares it with the other state-of-the-art SAR ADC architectures. The figure of Merit (FOM) is generally used to check the overall performance of ADC, and the FOM can be evaluated as below: where the sampling rate is presented as FS, bandwidth of ADC is denoted as BW, and power consumed by the proposed ADC is represented as PowerADC. The proposed SAR ADC architecture achieved a FOM of 66.25 fJ/conv-step.

Conclusions
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous SAR ADC with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance several, techniques have been proposed. A dual-path bootstrap switch is proposed to increase the linearity sampling. The VCM-based CDAC switching technique has been implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve the faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement for a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides stable reference voltages to the ADC for practical implementation. The measurement results of the proposed SAR ADC including an onchip bandgap reference voltage generator showed an ENOB of 9.49 bits and SNDR of 58.88 dB with 1.2 V of power supply and operation with a sampling rate of 1 MS/s.

Conclusions
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous SAR ADC with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance several, techniques have been proposed. A dual-path bootstrap switch is proposed to increase the linearity sampling. The VCM-based CDAC switching technique has been implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve the faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement for a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides stable reference voltages to the ADC for practical implementation. The measurement results of the proposed SAR ADC including an on-chip bandgap reference voltage generator showed an ENOB of 9.49 bits and SNDR of 58.88 dB with 1.2 V of power supply and operation with a sampling rate of 1 MS/s.