Miniature Wide-Band Noise-Canceling CMOS LNA

In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs a CC-based approach to obtain wide-band input matching without the need for bulky inductances, allowing broadband performance with a very small area used. The NC technique is applied by subtracting the input transistor’s noise contribution to the output and achieves a noise figure (NF) reduction from 4.8 dB to 3.2 dB. The NC LNA is implemented in a UMC 65-nm CMOS process and occupies an area of only 160 × 80 μm2. It achieves a stable frequency response from 0 to 6.2 GHz, a maximum gain of 15.3 dB, an input return loss (S11) < −10 dB, and a remarkable IIP3 of 7.6 dBm, while consuming 18.6 mW from a ±1.2 V DC supply. Comparisons with similar works prove the effectiveness of this new implementation, showing that the circuit obtains a noteworthy performance trade-off.


Introduction
A low-noise amplifier (LNA) is one of the key elements in a wide-band receiver. As the first element in the receiving chain, its noise figure (NF) and gain have a greater impact than other modules on the overall performance. Source impedance matching is also required to limit reflections. Conventional broadband LNA designs, such as resistive-loaded common source (CS) or common gate (CG) amplifiers, have proven difficult to meet the above requirements [1]. On the other hand, amplifiers employing a global negative feedback can achieve low NF with good input matching, but they are prone to becoming unstable [2]. Other alternatives, such as distributed amplifiers (DAs) [3] or cascode amplifiers with LC broadband input-matching networks [4][5][6], provide good impedance matching and high gain in a larger frequency range, but they need several inductors. Another topology used to design broadband LNAs is based on the use of current conveyors (CC) [7][8][9]. Although they have many advantages, such as good input matching, high linearity, and low power consumption, they suffer from the drawback of having a relatively high NF. In this paper we explore the use of noise-canceling techniques [10][11][12] to obtain a significant reduction in the NF of CC-based broadband LNAs. The goal is to present an amplifier topology that combines the advantages of a CC-based circuit with the possibility of reducing the NF at the output of the circuit.
The organization of the paper is as follows. In Section 2, a wide-band amplifier based on CC is discussed. In Section 3, the noise-canceling technique of a CG amplifier is presented. The CC-based amplifier with noise cancelation is introduced in Section 4.
Section 5 reports the simulation results of the proposed LNA implemented in a UMC 65-nm CMOS process. Finally, conclusions of this work are drawn in Section 6.

CMOS Current Conveyor Based LNA
The basic topology of a CC-based amplifier using CMOS technology is shown in Figure 1. It consists of an input CG gain stage (M1), followed by a source follower stage (M2) [8].
ensors 2022, 22, x FOR PEER REVIEW 5 reports the simulation results of the proposed LNA implemented in a CMOS process. Finally, conclusions of this work are drawn in Section 6.

CMOS Current Conveyor Based LNA
The basic topology of a CC-based amplifier using CMOS technology is ure 1. It consists of an input CG gain stage (M1), followed by a source follow [8]. The DC gain (G), bandwidth (f −3dB ), and noise factor (F) can be calcul by (1), (2), and (3), respectively, where gm1 and gm2 are the M1 and M2 trans CT represents the total parasitic capacitance at the output node, and γ is th factor, which is a constant that depends on the transistor size.
The circuit's input and output impedances can be easily computed as There is a trade-off between gm1 and gm2 and, consequently, between sizes and bias currents. Current I01 affects the gain through gm1, but has n The DC gain (G), bandwidth ( f −3dB ), and noise factor (F) can be calculated as shown by (1), (2), and (3), respectively, where g m1 and g m2 are the M1 and M2 transconductances, C T represents the total parasitic capacitance at the output node, and γ is the excess noise factor, which is a constant that depends on the transistor size. (1) The circuit's input and output impedances can be easily computed as There is a trade-off between g m1 and g m2 and, consequently, between the transistor sizes and bias currents. Current I 01 affects the gain through g m1 , but has no effect on the bandwidth, while I 02 controls the gain and bandwidth through g m2 (if I 02 is increased, the Sensors 2022, 22, 5246 3 of 8 bandwidth increases, but the gain is decreased). On the other hand, when g m1 increases, F decreases, as shown in (3). This can be done by increasing the size of M1 or the current I 01 . Likewise, if M2 and M4 are either smaller or biased with a lower I 02 , F decreases. Finally, the input and output impedances are directly related to their associated transistors and bias currents. For example, through I 01 , Z in can be matched to the source impedance without resorting to matching networks, allowing for a much smaller circuit when compared to conventional topologies. This is one of the main advantages of this approach. Following this discussion, the bias currents I 01 and I 02 are selected as 1 mA and 200 µA, respectively, to maintain a reasonable power consumption.
The complete implementation of the circuit schematic is shown in Figure 2, where the ideal current sources have been replaced by current mirrors. The high number of transistors certainly affects the performance of the circuit, especially bandwidth, noise, and power consumption. Due to the low output conductance of transistors in deep submicron technologies, the input impedance also deviates from the conventional 1/g m value. This, rather than being a problem, can be useful to isolate the input-matching condition from the noise-canceling one, providing a degree of freedom in the input-matching design [12]. to conventional topologies. This is one of the main advantages of this approach. Following this discussion, the bias currents I01 and I02 are selected as 1 mA and 200 μA, respectively to maintain a reasonable power consumption. The complete implementation of the circuit schematic is shown in Figure 2, wher the ideal current sources have been replaced by current mirrors. The high number of tran sistors certainly affects the performance of the circuit, especially bandwidth, noise, and power consumption. Due to the low output conductance of transistors in deep submicron technologies, the input impedance also deviates from the conventional 1/gm value. This rather than being a problem, can be useful to isolate the input-matching condition from the noise-canceling one, providing a degree of freedom in the input-matching design [12]

Noise-Canceling Technique Applied to a CG Stage
Equation (3) shows that the input common-gate transistor (M1) is the main noise con tributor. Various architectures can be found in the literature to cancel the noise of thi topology [10][11][12]. The simplified diagram of a common-gate stage with noise cancelation is depicted in Figure 3. With this technique, the noise of the input transistor passe through two different paths (transistors MX and MY), and is canceled at the output, whil the input signal is boosted. This can be seen better in the inset of Figure 4, where the nois and the signals are plotted on the schematic. Transistor M1 is the main noise contributor and a noise source (inoise) represents its contribution in the circuit. This source generates voltage at the source of M1 and a fully correlated voltage at the drain with the same mag nitude and opposite sign. The noise reaches the output through two different paths, and thanks to the CS inverting stages composed by transistors MX and MY, it is canceled a the output. In contrast, the input signal is amplified through the same paths thanks to th CS-CG inverting amplifier (transistors M1 and MY) and the CS inverting amplifier (MX and is amplified at the output instead of being canceled.
To achieve perfect noise cancelation, the two noise paths should have the same gain Therefore, transistors MX and MY must be independently biased. It is important to not that transistors MX and MY also introduce noise into the circuit, so they must be carefully designed. Thus, the key to achieve a low overall NF has now shifted to a low noise imple

Noise-Canceling Technique Applied to a CG Stage
Equation (3) shows that the input common-gate transistor (M1) is the main noise contributor. Various architectures can be found in the literature to cancel the noise of this topology [10][11][12]. The simplified diagram of a common-gate stage with noise cancelation is depicted in Figure 3. With this technique, the noise of the input transistor passes through two different paths (transistors MX and MY), and is canceled at the output, while the input signal is boosted. This can be seen better in the inset of Figure 4, where the noise and the signals are plotted on the schematic. Transistor M1 is the main noise contributor, and a noise source (i noise ) represents its contribution in the circuit. This source generates a voltage at the source of M1 and a fully correlated voltage at the drain with the same magnitude and opposite sign. The noise reaches the output through two different paths, and thanks to the CS inverting stages composed by transistors MX and MY, it is canceled at the output. In contrast, the input signal is amplified through the same paths thanks to the CS-CG inverting amplifier (transistors M1 and MY) and the CS inverting amplifier (MX) and is amplified at the output instead of being canceled.

LNA Based on CC with Noise Canceling
To better understand the improvements introduced by the noise-canceling technique, two different implementations were developed with the same sizing and bias currents. On the one hand, a current conveyor-based LNA is implemented following the schematic depicted in Figure 2. On the other hand, a second implementation of the LNA applying the noise cancelation technique is developed following the schematic shown in Figure 4.
The circuits are developed using UMC 65-nm CMOS technology with a ±1.2 V DC supply voltage. A summary of the device sizing information is given in Table 1, where the length of all the MOSFETs is fixed to the minimum allowed value of 65 nm. Note that the bias currents I01 and I02 are selected as 1 mA and 200 μA, respectively, and the DC voltages VBF and VBX are 0.35 V each. In addition, the resistor RY is selected as 220 ohms. The schematic of the proposed noise-canceling LNA based on CC is presented in Figure 4. This circuit combines the CC-based approach shown in Figure 2 with the noise-canceling technique presented in Section 3. As explained above, the input transistor generates a noise contribution of equal magnitude but opposite phase at its drain and source terminals. These two noise signals pass through two inverting paths and are canceled at the output. On the contrary, the input signal has the same sign on the drain and source terminals of the input transistor, so it passes through the two inverting paths, and it is added at the output. In the design of this circuit, the size of the input stage should be determined to obtain a good broadband input impedance match. The noise-canceling stage must be designed to achieve broadband noise cancelation while introducing as little noise as possible

LNA Based on CC with Noise Canceling
To better understand the improvements introduced by the noise-canceling technique, two different implementations were developed with the same sizing and bias currents. On the one hand, a current conveyor-based LNA is implemented following the schematic depicted in Figure 2. On the other hand, a second implementation of the LNA applying the noise cancelation technique is developed following the schematic shown in Figure 4.
The circuits are developed using UMC 65-nm CMOS technology with a ±1.2 V DC supply voltage. A summary of the device sizing information is given in Table 1, where the length of all the MOSFETs is fixed to the minimum allowed value of 65 nm. Note that the bias currents I01 and I02 are selected as 1 mA and 200 μA, respectively, and the DC voltages VBF and VBX are 0.35 V each. In addition, the resistor RY is selected as 220 ohms. The schematic of the proposed noise-canceling LNA based on CC is presented in Figure 4. This circuit combines the CC-based approach shown in Figure 2 with the noise-canceling technique presented in Section 3. As explained above, the input transistor generates a noise contribution of equal magnitude but opposite phase at its drain and source terminals. These two noise signals pass through two inverting paths and are canceled at the output. On the contrary, the input signal has the same sign on the drain and source terminals of the input transistor, so it passes through the two inverting paths, and it is added at the output. In the design of this circuit, the size of the input stage should be determined to obtain a good broadband input impedance match. The noise-canceling stage must be designed to achieve broadband noise cancelation while introducing as little noise as possible To achieve perfect noise cancelation, the two noise paths should have the same gain. Therefore, transistors MX and MY must be independently biased. It is important to note that transistors MX and MY also introduce noise into the circuit, so they must be carefully designed. Thus, the key to achieve a low overall NF has now shifted to a low noise implementation in the noise-canceling stage.

LNA Based on CC with Noise Canceling
To better understand the improvements introduced by the noise-canceling technique, two different implementations were developed with the same sizing and bias currents. On the one hand, a current conveyor-based LNA is implemented following the schematic depicted in Figure 2. On the other hand, a second implementation of the LNA applying the noise cancelation technique is developed following the schematic shown in Figure 4.
The circuits are developed using UMC 65-nm CMOS technology with a ±1.2 V DC supply voltage. A summary of the device sizing information is given in Table 1, where the length of all the MOSFETs is fixed to the minimum allowed value of 65 nm. Note that the bias currents I 01 and I 02 are selected as 1 mA and 200 µA, respectively, and the DC voltages V BF and V BX are 0.35 V each. In addition, the resistor R Y is selected as 220 ohms. The schematic of the proposed noise-canceling LNA based on CC is presented in Figure 4. This circuit combines the CC-based approach shown in Figure 2 with the noise-canceling technique presented in Section 3. As explained above, the input transistor generates a noise contribution of equal magnitude but opposite phase at its drain and source terminals. These two noise signals pass through two inverting paths and are canceled at the output. On the contrary, the input signal has the same sign on the drain and source terminals of the input transistor, so it passes through the two inverting paths, and it is added at the output. In the design of this circuit, the size of the input stage should be determined to obtain a good broadband input impedance match. The noise-canceling stage must be designed to achieve broadband noise cancelation while introducing as little noise as possible and degrading gain, bandwidth, power consumption, and input matching as little as possible. Using a CC-based LNA as the input stage instead of a simple CG stage gives a degree of freedom in satisfying the input-matching conditions.

Simulation Results and Analysis
The simulated performance comparison of the LNA based on CC (CC) and the proposed LNA based on CC with noise cancelation (CCNC) is shown in Figure 5. The proposed technique reduces the noise figure from 4.85 dB to 3.25 dB at 1 GHz. At frequencies below 6 GHz, both circuits present a reasonable input matching, with an input return loss (S11) < −10 dB. However, at higher frequencies the input matching deteriorates slightly. This can be solved by simply increasing the bias current I 02 , but at the expense of increasing the power consumption. and degrading gain, bandwidth, power consumption, and input matching as little as possible. Using a CC-based LNA as the input stage instead of a simple CG stage gives a degree of freedom in satisfying the input-matching conditions.

Simulation Results and Analysis
The simulated performance comparison of the LNA based on CC (CC) and the proposed LNA based on CC with noise cancelation (CCNC) is shown in Figure 5. The proposed technique reduces the noise figure from 4.85 dB to 3.25 dB at 1 GHz. At frequencies below 6 GHz, both circuits present a reasonable input matching, with an input return loss (S11) < −10 dB. However, at higher frequencies the input matching deteriorates slightly. This can be solved by simply increasing the bias current I02, but at the expense of increasing the power consumption. The layout of the proposed LNA is shown in Figure 6. To reduce the circuit area, the BIAS-T inductor needed to bias the MX transistor is replaced by a large resistor, which is implemented in practice by the large leakage resistance of a reverse-biased p-n junction of a diode-connected MOS transistor operating in the cutoff region (2 × 0.5 μm). Note that the exact value of this resistance or its temperature and voltage dependence are not relevant, provided that it remains large enough not to influence the circuit operation at the lowest frequency required. As no inductor is present, the LNA core occupies an area of only 160 × 80 μm 2 , which is among the smallest designs available in the literature.
Linearity is a very important feature of an LNA since a higher 1-dB compression point means a larger capability of receiving weak signals in the presence of strong ones. This technique presents the advantage of significantly boosting the circuit's linearity, since the same mechanism leading to noise cancelation can also cancel partially the nonlinear distortions [13]. The simulation results shown in Figure 7 demonstrate an input 1-dB compression point of -2 dBm. Finally, the power dissipation of the circuit is 18.57 mW, with a The layout of the proposed LNA is shown in Figure 6. To reduce the circuit area, the BIAS-T inductor needed to bias the MX transistor is replaced by a large resistor, which is implemented in practice by the large leakage resistance of a reverse-biased p-n junction of a diode-connected MOS transistor operating in the cutoff region (2 × 0.5 µm). Note that the exact value of this resistance or its temperature and voltage dependence are not relevant, provided that it remains large enough not to influence the circuit operation at the lowest frequency required. As no inductor is present, the LNA core occupies an area of only 160 × 80 µm 2 , which is among the smallest designs available in the literature. The performance of the proposed LNA is compared in Table 2 with recently reported LNAs available in the literature. To fairly compare the proposed CCNC LNA with the other designs, we have defined the following figure of merit (FoM), which considers a positive contribution of amplifier gain, bandwidth, and IIP3, and a negative contribution of power consumption, noise factor, and active area: The proposed CCNC LNA presents the highest FoM value among the reported designs. This is because the proposed technique achieves a high bandwidth and IIP3 values using a very small area, while the gain and NF are within the average. The price to pay is a slightly higher power consumption than most of the other designs in the comparison.  Linearity is a very important feature of an LNA since a higher 1-dB compression point means a larger capability of receiving weak signals in the presence of strong ones. This technique presents the advantage of significantly boosting the circuit's linearity, since the same mechanism leading to noise cancelation can also cancel partially the nonlinear distortions [13]. The simulation results shown in Figure 7 demonstrate an input 1-dB compression point of -2 dBm. Finally, the power dissipation of the circuit is 18.57 mW, with a DC supply of ±1.2 V. The performance of the proposed LNA is compared in Table 2 with recently reported LNAs available in the literature. To fairly compare the proposed CCNC LNA with the other designs, we have defined the following figure of merit (FoM), which considers a positive contribution of amplifier gain, bandwidth, and IIP3, and a negative contribution of power consumption, noise factor, and active area: The proposed CCNC LNA presents the highest FoM value among the reported designs. This is because the proposed technique achieves a high bandwidth and IIP3 values using a very small area, while the gain and NF are within the average. The price to pay is a slightly higher power consumption than most of the other designs in the comparison.  The performance of the proposed LNA is compared in Table 2 with recently reported LNAs available in the literature. To fairly compare the proposed CCNC LNA with the other designs, we have defined the following figure of merit (FoM), which considers a positive contribution of amplifier gain, bandwidth, and IIP3, and a negative contribution of power consumption, noise factor, and active area: The proposed CCNC LNA presents the highest FoM value among the reported designs. This is because the proposed technique achieves a high bandwidth and IIP3 values using a very small area, while the gain and NF are within the average. The price to pay is a slightly higher power consumption than most of the other designs in the comparison.

Conclusions
A wide-band CMOS noise-canceling current conveyor-based LNA is proposed in this paper and is implemented in a standard 65-nm CMOS process. The design exploits a noise-canceling technique consisting of an amplifying stage based on a CC that provides input impedance matching, and a noise-canceling stage composed of two transistors in CS configuration that subtracts the input transistor noise contribution while adding the signal contributions. The simulation results show that the proposed CCNC LNA achieves wide-band input impedance matching (0-6.2 GHz), with high gain (15.3 dB) and low noise (4.8 dB), in a very small area (160 × 80 µm 2 ). The circuit presents a power dissipation of 18.57 mW from a DC supply of ±1.2 V. In addition, the proposed noise-canceling technique also improves the linearity because it is capable of partially canceling nonlinear distortions. The proposed circuit achieves a remarkable IIP3 of 7.6 dB and an input P 1dB of -2 dBm. The price to pay with this approach is the additional power dissipation introduced by the auxiliary amplifier in the noise-canceling path. As shown in the comparison with similar works, the proposed circuit presents the highest FoM value among the reported designs.