A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power

This paper proposes a 2.4-GHz fully-integrated single-frequency multi-channel RF energy harvesting (RFEH) system with increased harvested power density. The RFEH can produce an output power of ~423-μW in harvesting ambient RF energy. The front-end consists of an on-chip impedance matching network with a stacked rectifier concurrently matched to a 50 Ω input source. The circuit mitigates the “dead-zone” by enhancing the pumping efficiency, achieved through the increase of Vgs drivability of the proposed internal gate boosting 6-stage low-input voltage charge pump and the 5-stage shared-auxiliary-biasing ring-voltage-controlled-oscillator (VCO) integrated to improve the start-up. The RFEH system, simulated in 180-nm complementary metal–oxide–semiconductor (CMOS), occupies an active area of 1.02 mm2. Post-layout simulations show a peak power conversion efficiency(PCE) of 21.15%, driving a 3.3-kΩ load at an input power of 0 dBm and sensitivity of −14.1 dBm corresponding to an output voltage, Vout,RFEH of 1.25 V.


Introduction
Ubiquitous wireless sensor nodes (WSNs), body sensor nodes (BSN), and portable health monitoring devices will require energy harvesting (EH) to achieve battery-less or long-term battery-assist operation. RF Energy Harvesting (RFEH) [1][2][3][4][5][6][7] is gaining interest due to its continuous availability in urban environments compared to other renewable energy sources like solar, thermal, and piezo EH. In an indoor environment, the RF signal is concentrated, and in the outdoor environment the weather, season, and illumination have less impact around 0.0001 to 0.004 dB/m as propagation attenuation of EM waves [2]. In addition, the RFEH system conciliates well with existing wireless systems with a standard 50-Ω impedance matching network, requiring only an antenna as a transducer [8]. Most modern communication devices enable Wi-Fi or Bluetooth low-energy (BLE), hence, RF energy is abundant and the 2.4-GHz frequency band is of interest to achieve a small physical form factor as well as a low-cost solution for RFEH [8]. According to the International Telecommunication Union (ITU), global Wi-Fi growth increased by 80% after the first quarter of 2020 [9]. Hence, the power density of the wireless frequency in this channel [10] increased and we can drain it to overcome the limitation due to the low input power density of the RFEH in improving the system's energy reliability. In complementing the RFEH, the The usage of multi-channel RFEHS not only has the potential to improve the performance of the harvester but also increases the harvesting sensitivity [17], and supports a multiple-input multiple-output (MIMO) system [18,19].
Various multi-channel, multi-band RFEH systems adopting discrete elements require off-chip components [1,4,10,[17][18][19][20], which include Schottky diodes [15] and rectenna [21]. Figure 1 presents the simple block diagram of the proposed RFEH system, which includes an on-chip impedance matching network (IMN), a stacked rectifier, and a chargepump-based DC-to-DC converter with the developed shared-auxiliary-biasing ring-voltagecontrolled-oscillator (SAB-RVCO). The array of antennas receives the available RF energy from the free space environment. The rectifier converts the time-varying electromagnetic RF signal to a DC voltage. The impedance matching network (IMN) interfaces the antenna (typically 50 Ω) and rectifiers to reduce impedance mismatch which in turn minimizes the power reflection. However, the physical form factor of the discrete components occupies a huge space, this limits the EH in the targeted WSN, BSN, and health care application. To overcome the aforementioned challenges, recent research directions changed towards solutions on-chip or with full integration. The primary scope of the proposed work is to increase the higher power density with higher power conversion efficiency and higher sensitivity for an on-chip solution. power density of the RFEH in improving the system's energy reliability. In complementing the RFEH, the power consumption of various portable devices operates within the hundreds of μW range for the detection of symptomatic patterns in audio biological signals [11], ECG [12,13], and other health monitoring [14]. Table 1 shows the typical range of the power consumption of various electronic devices.  [15,16].  [12,13] Active RFID, Miniature FM receiver, Health monitoring [14] The usage of multi-channel RFEHS not only has the potential to improve the performance of the harvester but also increases the harvesting sensitivity [17], and supports a multiple-input multiple-output (MIMO) system [18,19].

Power
Various multi-channel, multi-band RFEH systems adopting discrete elements require off-chip components [1,4,10,[17][18][19][20], which include Schottky diodes [15] and rectenna [21]. Figure 1 presents the simple block diagram of the proposed RFEH system, which includes an on-chip impedance matching network (IMN), a stacked rectifier, and a chargepump-based DC-to-DC converter with the developed shared-auxiliary-biasing ring-voltage-controlled-oscillator (SAB-RVCO). The array of antennas receives the available RF energy from the free space environment. The rectifier converts the time-varying electromagnetic RF signal to a DC voltage. The impedance matching network (IMN) interfaces the antenna (typically 50 Ω) and rectifiers to reduce impedance mismatch which in turn minimizes the power reflection. However, the physical form factor of the discrete components occupies a huge space, this limits the EH in the targeted WSN, BSN, and health care application. To overcome the aforementioned challenges, recent research directions changed towards solutions on-chip or with full integration. The primary scope of the proposed work is to increase the higher power density with higher power conversion efficiency and higher sensitivity for an on-chip solution. Challenges of the on-chip IMN solution: IMN in RFEHS is built with capacitors and high Q-inductors for voltage amplification and maximum power transfer [22][23][24][25][26][27][28]. However, designing a high Q-inductor in complementary metal-oxide-semiconductor (CMOS) technology has its limitations and trade-offs in attaining maximum power conversion efficiency [29].
To overcome the aforementioned challenges of an on-chip IMN design, we present the following findings: (1) Through the investigation of the on-chip impedance matching technique for the RFEH system [30,31], this work proposes a design strategy that adopts the variation of the rectifier input impedance and devises a technique for the area reduction along with performance enhancement. (2) To increase the sensitivity of the RFEH system, we also put forward a low-power, non-overlap-clock shared-auxiliary-biasing ring-voltage-controlled-oscillator (SAB-RVCO) and the proposed internal gate biasing Challenges of the on-chip IMN solution: IMN in RFEHS is built with capacitors and high Q-inductors for voltage amplification and maximum power transfer [22][23][24][25][26][27][28]. However, designing a high Q-inductor in complementary metal-oxide-semiconductor (CMOS) technology has its limitations and trade-offs in attaining maximum power conversion efficiency [29].
To overcome the aforementioned challenges of an on-chip IMN design, we present the following findings: (1) Through the investigation of the on-chip impedance matching technique for the RFEH system [30,31], this work proposes a design strategy that adopts the variation of the rectifier input impedance and devises a technique for the area reduction along with performance enhancement. (2) To increase the sensitivity of the RFEH system, we also put forward a low-power, non-overlap-clock shared-auxiliary-biasing ring-voltagecontrolled-oscillator (SAB-RVCO) and the proposed internal gate biasing charge pump. By using a novel body-biasing technique, the SAB-RVCO can generate a non-overlap clock at low supply headroom and improve the pumping efficiency of the charge pump. The design of the proposed SAB-RVCO uses a dual-input RFEH system achieving single-chip integration and an overall low-power consumption for the harvester.
This paper reports a dual-channel fully-integrated RFEH system that consumes a total chip area of 1.02-mm 2 in 180-nm CMOS. With the proposed dual-channel scheme, the circuit exhibits a higher power density of 423 µW at 0-dBm input power. Section 2 describes the overview of the proposed fully-integrated RFEH system. Section 3 presents the IMN design strategy and circuit-level design of the SAB-RVCO along with the charge-pump circuits. We also discuss the control circuit adopted in the RFEHS. Section 4 highlights the post-layout simulation results of the RFEHS and Section 5 concludes the work. Figure 2 outlines the conceptual block diagram of a fully-integrated dual-input RFEH system. Two differential antennas configured at the same frequency will scavenge RF power to increase the harvesting input density. The integrated rectifier has a highlyefficient differential drive similar to [32]. The proposed rectifier is cascaded in a 3 × 3 stage to achieve high efficiency and low input impedance. An on-chip differential LC-matching is adopted and realized in a fully-integrated system. This activates the PPP in which the control unit selects switch S1 (HIGH) to turn on and S2 (LOW) to turn off. This in turn increases the PCE of the RFEH system during the high power mode. Similarly, if the comparator weighs in Vrec to be lower than the Vref, the voltage Vcmp becomes high and inverter output is low, hence the control unit switches S1 to turn-off and S2 to turn-on. This operation activates the SPP of the RFEHS. In short, this mode benefits in increasing the sensitivity of the RFEH system through the proposed charge pump. The proposed system consists of two power paths controlled by the control unit incorporating two MOSFET switches, an inverter, and a common-gate input comparator. Figure 2 shows the primary power path (PPP) as well as the secondary power path (SPP) which harvests high power directly to the load unit and low power to the storage unit in extending the lifetime of the battery. The comparator weighs the rectifier output voltage (V rec ) and the reference voltage (V ref ). As long as V rec is greater than V ref , the comparator output voltage V cmp is low and the inverter output will be high.

System Architecture
This activates the PPP in which the control unit selects switch S 1 (HIGH) to turn on and S 2 (LOW) to turn off. This in turn increases the PCE of the RFEH system during the high power mode. Similarly, if the comparator weighs in V rec to be lower than the V ref , the voltage V cmp becomes high and inverter output is low, hence the control unit switches S 1 to turn-off and S 2 to turn-on. This operation activates the SPP of the RFEHS. In short, this mode benefits in increasing the sensitivity of the RFEH system through the proposed charge pump.

Rectifier
The proposed RFEH system uses a customized differential cross-coupled (DCC) [33] rectifier with three-stage series with three parallel stages to achieve impedance transformation, which is discussed in detail in Section 3.2. The proposed rectifier attains higher PCE at low input power compared to the conventional diode-connected single-ended rectifier topology. The rectifier is configured with the transistors M DP1 , M DP2 , M DN1 , and M DN2 which are actively biased with differential signals V RF+ and V RF-as shown in Figure 3. When V RF+ is negative and V RF-is in a positive cycle, the transistor M DN1 is forward biased due to the positive gate voltage from V RF-which reduces the on-resistance of M DN1 . Alternately, when V RF+ is positive and V RF-is in a negative cycle, M DN1 is reverse biased by a decrease in the gate voltage, and thus reduces the reverse leakage current. Previously-reported work on the fully-integrated RFEHS adopts a single-ended rectifier due to the size constraint of the on-chip inductor. The proposed RFEH system in this work is the first to couple the DCC rectifier with an on-chip matching network. In order to reduce the switching losses, an optimal number of fixed rectifier stages are used instead of reconfigurable stages. size constraint of the on-chip inductor. The proposed RFEH system in this work is the first to couple the DCC rectifier with an on-chip matching network. In order to reduce the switching losses, an optimal number of fixed rectifier stages are used instead of reconfigurable stages.

Impedance Matching Network
The design of the IMN network aims to match the rectifier to a standard 50 Ω source impedance. The equivalent model of the IMN circuit is shown in Figure 4. The voltage source with an amplitude of VAnt is an integrated series with the antenna resistance RAnt,

Impedance Matching Network
The design of the IMN network aims to match the rectifier to a standard 50 Ω source impedance. The equivalent model of the IMN circuit is shown in Figure 4. The voltage source with an amplitude of V Ant is an integrated series with the antenna resistance R Ant , and with an IMN that consists of inductor L M1 , L M2 , and capacitor C M1 . In addition to impedance transformation to attain maximum power transfer, the IMN is also utilized for passive voltage amplification.

Impedance Matching Network
The design of the IMN network aims to match the rectifier to a standard 50 Ω source impedance. The equivalent model of the IMN circuit is shown in Figure 4. The voltage source with an amplitude of VAnt is an integrated series with the antenna resistance RAnt, and with an IMN that consists of inductor LM1, LM2, and capacitor CM1. In addition to impedance transformation to attain maximum power transfer, the IMN is also utilized for passive voltage amplification.  The proposed IMN network introduces an impedance reduction technique, which consequently improves the Q-factor of the inductor. The realization of the IMN is evaluated through the input reflection coefficient, S 11 , which is defined as, where Z Rect = R Rec + X Rec is the impedance of the rectifier and Z * Ant is the complex conjugate of Z Ant , where Z Ant = R Ant + X Ant is the impedance of the antenna or source. The amount of power reflected is calculated through Equation (2), The passive voltage gain A v is directly proportional to the Q L -factor of the inductor [30], Based on Equation (3), Q L is a defining factor for voltage gain, which is directly proportional to the PCE of the RFEH system. At the operating frequency of 2.4 GHz in the 180-nm CMOS platform, the inductor quality (Q) factor is in the range of 8 to 1 for 6 nH to 22 nH of inductance. The Q-factor is limited beyond the defined range of inductance with the silicon chip area increasing proportionally with the inductor value. The conventional IMN design strategy is based on the rectifier's optimal number of stages, hence the rectifier input impedance is fixed. The balanced or symmetry impedance matching is used to derive the circuit with the same impedance and effect of the signal traveling in both directions of the port.
An on-chip LC-match IMN is adopted as shown in Figure 5. The value of C m and L m can be approximated by [34], where ωRF represents the input RF frequency. The ideal simulated input impedance of the 3-stage series rectifier is 16 (3) and reduces A v and the PCE of the system. The proposed system aims to improve the voltage gain by increasing the Q of the inductor. In the proposed RFEHS, a 3-stage series rectifier is connected in parallel to reduce rectifier impedance, thus reducing inductance and improving the Q factor as well as the passive voltage gain which concurrently improves the PCE and achieves a smaller silicon area. Figure 5 shows the impedance reduction scheme with a single 3-stage series rectifier, 2-parallel-3-stage series rectifier, and 3-parallel-3-stage series rectifier. The input impedance of the rectifier with 2 and 3 parallel stages is 9.78 − j246.68 Ω and 7.59 − j165.08 Ω, respectively. This reduction of impedance improves the inductor Q value to~6 for two parallel stage rectifiers and 8 for 3-parallel stage rectifiers in the technology of choice. Similarly, a two-channel symmetrical system is designed with an on-chip impedance matching network.

Proposed SAB-RVCO
A step-up DC-DC converter is an essential unit in attaining high sensitivity for RFEHS. The capacitive-based step-up DC-DC converter or charge pump (CP) is best suited for an on-chip implementation in contrary to the inductor-based DC-DC converter which requires bulky off-chip components which is unfavorable for miniaturization of the device. The monolithic ring-voltage control oscillator (R-VCO) is the main peripheral of the charge pump, where low-power and low start-up will be the key performance parameter for the RFEHS [30].
The primary bottleneck in designing a charge pump for the EH system is to achieve a low-power, low-startup RVCO as well as a non-overlap clock unit. In addition, the

Proposed SAB-RVCO
A step-up DC-DC converter is an essential unit in attaining high sensitivity for RFEHS. The capacitive-based step-up DC-DC converter or charge pump (CP) is best suited for an on-chip implementation in contrary to the inductor-based DC-DC converter which requires bulky off-chip components which is unfavorable for miniaturization of the device. The monolithic ring-voltage control oscillator (R-VCO) is the main peripheral of the charge pump, where low-power and low start-up will be the key performance parameter for the RFEHS [30].
The primary bottleneck in designing a charge pump for the EH system is to achieve a low-power, low-startup RVCO as well as a non-overlap clock unit. In addition, the RVCO must be able to operate with a minimum supply voltage (V DD , min ), lower than the threshold voltage (V th ) of the transistor. These limitations are dependent on the subthreshold swing (S S ) of the CMOS process. The range of Ss is between 70 to 100 mV/decade with the advanced CMOS process node can achieve nearer to the Meindl limits [35]. The oscillation of RVCO must exhibit a rail-to-rail output with higher current drivability to drive the pumping capacitor of the CP. However, when V rec is less than V th , the device limits the current flow due to weak inversion between source and drain channel, reducing the RVCO drivability. In a higher process node technology, the V th of the device decreases, however, this, in turn, increases the production cost. Alternatively, the body bias technique favorably reduces the V th and increases the device inversion region in lower process technology.
The V th of an N-channel metal-oxide-semiconductor (NMOS) is expressed as [36], where γ is the body-effect coefficient, φ F is the Fermi potential, V th and V th0 are the threshold voltage and threshold voltage at zero source-to-bulk voltage (V sb ), respectively. The deep-well technology enables the body bias technique which varies the V th and allows a low voltage headroom operation. To minimize the V th of the transistor, the V sb is sourced with a higher voltage than the V ss for NMOS and alternately sourced with a lower voltage than the V dd for a P-channel metal-oxide-semiconductor (PMOS) device. This reduces the depletion region and increases the near saturation region operation, which in turn increases the saturation current and concurrently reduces the propagation delay. The commonly used body biasing technique includes the dynamic threshold-voltage MOSFET (DTMOS) [37], swapped body bias (SBB) [38], and auxiliary transistor [39]. In the DTMOS configuration, the gate terminal is connected to the body or bulk of the PMOS and is similar to an NMOS transistor. Hence, the V th of the transistor changes dynamically concerning the gate-source voltage (V gs ) of the inverter. Assuming a single-stage inverter with DTMOS applied between the supply voltage (V dd ) and ground, if V gs is low, then the bulk of both PMOS and NMOS should be low. Hence, V bs of the PMOS and NMOS are driven to forward bias (V bsp = −V dd ) and zero-bias (V bsn = 0), respectively. If V gs = V dd , then the bulk of both the PMOS and NMOS should be high, hence V bs of the PMOS and NMOS are driven to zero-bias (V bsp = 0) and forward bias (V bsn = V dd ), respectively. In the SBB configuration, the bulk of the PMOS are connected to ground whereas the bulk of the NMOS transistors are connected to V dd , so that V bs of both the PMOS and NMOS are driven to forward bias with V bsp = −V dd and V bsn = V dd , respectively.
In an auxiliary transistor body biasing configuration, the bulk of the PMOS and NMOS transistor is connected with the drain voltage of the auxiliary NMOS and PMOS, respectively. This achieves a higher biasing voltage magnitude compared to other body biasing techniques. However, the additional transistor increases the size as well as the effect of the inherent parasitic, which causes a mismatch in the phase shifters and tends to degrade the CP pumping efficiency at low voltage [40].
The architecture of the proposed SAB-RVCO is shown in Figure 6a. With n representing the stage number, the core circuitry of the RVCO shown in Figure 6b consists of the transistor M Pn and M Nn , two-phase shifters comprising of M SPn , M SNn , M CPn , and M CNn , which generate two-phase clocks Φ 1 Φ 1 and Φ 2 . In the transistor's weak-inversion region, the parasitic dominates, and the clock signals (Φ 1 and Φ 2 ) overlap, which degrades the CP performance. To overcome this problem, transistors M PBn and M NBn are integrated to establish bulk-biasing for the RVCO and phase shifters. The bulk-biasing through M PBn and M NBn ensures Φ 1 and Φ 2 are non-overlap clock signals which improve the pumping efficiency of the charge pump when V DD is low. The minimum size of the device is maintained to achieve lower V th in RVCO while the dimension of the buffer is maximized by a systematic transistor sizing strategy [41] to drive the CP pumping capacitance approximating to 60 pF as well to minimize the rise-time and fall-time edge of the clock generation.  Figure 7 shows the schematic of the SAB-RVCO with two parallel phase shifter circuits. The number of stages (N) of the RVCO is attained based on the study of an effective number of stages relations with the frequency (fOsc) [42], power consumption (Pc) [43], and losses of CP [30]. The oscillation of frequency and power is given by [42,43], where the N is inversely proportional to the frequency and directly proportional to the power consumption [42]. It is worth noting that the frequency is directly proportional to the power consumption. Based on the inference from [30], higher frequency causes switching losses in the CP circuit. It is worth noting that switching losses are inversely proportional to the conduction loss. Hence the optimal 5-stages of the proposed RVCO achieve lower startup and higher efficiency, with lower parasitics effect, where N is the odd number of inverters (N = 5). The oscillation frequency of the RVCO is dependent on the time delay of each inverter stage, where the operation is shown in Figure 8a. Referring to Figure  7, in the SAB-RVCO, the bulk terminal of MP1 and MN1 are biased by the drain voltage of the auxiliary transistor MNB1 and MPB1, respectively. MNB1 provides the initial voltage for the parasitic capacitance of the transistor MP1 (Cdb-p1, Csb-p1) and MNB1 (Cgd-nb1, Cdb-nb1), where the parasitics of MOSFET are descriptively shown in Figure 8b. When Vg of MP1 is low, the drain voltage of MNB1 pulls Vb-p1(t) to the ground. This satisfies the initial condition of the bulk of MP1.  Figure 7 shows the schematic of the SAB-RVCO with two parallel phase shifter circuits. The number of stages (N) of the RVCO is attained based on the study of an effective number of stages relations with the frequency (f Osc ) [42], power consumption (P c ) [43], and losses of CP [30]. The oscillation of frequency and power is given by [42,43], where the N is inversely proportional to the frequency and directly proportional to the power consumption [42]. It is worth noting that the frequency is directly proportional to the power consumption. Based on the inference from [30], higher frequency causes switching losses in the CP circuit. It is worth noting that switching losses are inversely proportional to the conduction loss. Hence the optimal 5-stages of the proposed RVCO achieve lower startup and higher efficiency, with lower parasitics effect, where N is the odd number of inverters (N = 5). The oscillation frequency of the RVCO is dependent on the time delay of each inverter stage, where the operation is shown in Figure 8a. Referring to Figure 7, in the SAB-RVCO, the bulk terminal of M P1 and M N1 are biased by the drain voltage of the auxiliary transistor M NB1 and M PB1 , respectively. M NB1 provides the initial voltage for the parasitic capacitance of the transistor M P1 (C db-p1 , C sb-p1 ) and M NB1 (C gd-nb1 , C db-nb1 ), where the parasitics of MOSFET are descriptively shown in Figure 8b. When V g of M P1 is low, the drain voltage of M NB1 pulls V b-p1(t) to the ground. This satisfies the initial condition of the bulk of M P1 .
When Vd(t) falls too low, Vb-p1(t) reduces below zero and reaches a negative value due to the discharge of capacitance Cdb-p1 and Cgd-nb1. Alternately, when Vd(t) reaches a high value, then Vb-p1 increases from a negative voltage to zero due to the charging of capacitance Cdb-p1 and Cgd-nb1. During the process of charging and discharging the internal capacitance, Vb-p1(t) is lesser than the source voltage of MNB1, and no current flows between drain to source of MNB1, hence, MNB1 acts as capacitor Cgd-nb1. MPB1 provides the initial voltage for the parasitic capacitance of the transistor MN1 (Cdb-n1, Csb-n1) and MPB1 (Cgd-pb1,Cdb-pb1). When Vg of MN1 is high, the drain voltage of MPB1 drives Vb-n1(t) to Vdd. This satisfies the initial condition of the bulk of MN1.
When Vd(t) is high, Vb-n1(t) increases above Vdd and reaches a positive value due to the charging of Cdb-n1 and Cgd-pb1. Alternatively, when Vd(t) reaches a low value, Vb-n1 reduces When Vd(t) falls too low, Vb-p1(t) reduces below zero and reaches a negative value due to the discharge of capacitance Cdb-p1 and Cgd-nb1. Alternately, when Vd(t) reaches a high value, then Vb-p1 increases from a negative voltage to zero due to the charging of capacitance Cdb-p1 and Cgd-nb1. During the process of charging and discharging the internal capacitance, Vb-p1(t) is lesser than the source voltage of MNB1, and no current flows between drain to source of MNB1, hence, MNB1 acts as capacitor Cgd-nb1. MPB1 provides the initial voltage for the parasitic capacitance of the transistor MN1 (Cdb-n1, Csb-n1) and MPB1 (Cgd-pb1,Cdb-pb1). When Vg of MN1 is high, the drain voltage of MPB1 drives Vb-n1(t) to Vdd. This satisfies the initial condition of the bulk of MN1.
When Vd(t) is high, Vb-n1(t) increases above Vdd and reaches a positive value due to the charging of Cdb-n1 and Cgd-pb1. Alternatively, when Vd(t) reaches a low value, Vb-n1 reduces When V d(t) falls too low, V b-p1(t) reduces below zero and reaches a negative value due to the discharge of capacitance C db-p1 and C gd-nb1 . Alternately, when V d(t) reaches a high value, then V b-p1 increases from a negative voltage to zero due to the charging of capacitance C db-p1 and C gd-nb1 . During the process of charging and discharging the internal capacitance, V b-p1(t) is lesser than the source voltage of M NB1 , and no current flows between drain to source of M NB1 , hence, M NB1 acts as capacitor C gd-nb1 . M PB1 provides the initial voltage for the parasitic capacitance of the transistor M N1 (C db-n1 , C sb-n1 ) and M PB1 (C gd-pb1 ,C db-pb1 ). When V g of M N1 is high, the drain voltage of M PB1 drives V b-n1(t) to V dd . This satisfies the initial condition of the bulk of M N1 .
When V d(t) is high, V b-n1(t) increases above V dd and reaches a positive value due to the charging of C db-n1 and C gd-pb1 . Alternatively, when V d(t) reaches a low value, V b-n1 reduces from a higher positive value to V dd due to discharging of capacitor C db-n1 and C gd-pb1 . During the process of charging and discharging the internal capacitance, V b-n1(t) is higher than the source voltage of M PB1 and there is no current flow between drain to source of M PB1 , hence the transistor M PB1 acts as capacitor C gd-pb1 .
The auxiliary transistor acts as a capacitor during the charging and discharging phase that provides |V bs-n1 | ≥ V dd and |V bs-p1 | ≤ 0 compared to DTMOS and SBB, then RVCO operates in the sub-threshold region, the transistor current has an exponential relation with V bs and a linear relation concerning the aspect ratio. By reducing the aspect ratio, the subsequent stage of the transistor's internal capacitance (C o ) should be smaller, which requires less drain to the source current which assists to maintain low power dissipation.
The auxiliary transistor biasing technique shows improvement in the performance of the RVCO, phase shifter, and buffer circuit. However, the design technique doubles the area by the ratio of 1:1 (Primary transistor: Auxiliary transistor), increasing the parasitics and leading to mismatch at the phase of the clock which is unfavorable for low voltage CP below 250 mV [40,44]. To reduce the inherent parasite and improve the area efficiency of the clock generation unit, a single set of the auxiliary biasing transistors is shared between the parallel stage of inverters which operates with similar logic behavior in a configuration as the 3rd and 2nd stages of the phase shifter cell are connected with the 3rd stage of the RVCO inverter cell. Through this vertical sharing bias technique, our work achieves an area reduction in a ratio of 3:1 without compromising the functionality. In addition, the proposed SAB-RVCO achieves a similar drain to source current with lower input voltage due to the higher biasing voltage magnitude.

Charge-Pump Realization
The capacitive charge pump (CP) is well adapted for monolithic implementation compared to the bulky inductor-based boost converter. In addition, the capacitive CP has a good driving capability, minimal parasitic effect, and low complexity well fitted for energy harvesting applications. The CP performance at low voltage relies on the charge transfer switching resistance, particularly in the Dickson CP operation. The NMOS is driven in the triode region, and for a latched CP configuration, both the NMOS and PMOS transistor are driven in the triode region. For simplicity of the expression, the on-resistance (R on ) of the NMOS transistor is given neglecting the short channel effect, (11) where µ is the mobility of the electron/holes and C ox is the oxide capacitance which is a technology-dependent parameter. The CP resistance can be reduced by increasing the gate-to-source voltage (V gs ). The internal gate enhances overdrive voltage [45] and external clock boosting topology can provide 2 folds [46,47] or 3 folds [48] of input voltage for low voltage CP application. However, in most cases, the clock signal is equal to V dd , therefore, increasing the V gs to greater than the V dd is a tangible solution observed from Equation (9). The proposed CP provides clock amplitude equal to 2V gs and achieves the primary goal of a CP circuit. Figure 9 shows the proposed 6-stage CP with the operation of each cycle described as follows. Each stage of the proposed CP consists of PMOS (M P1i , M P2i , B P1i , B P2i ), NMOS (M N1i , M N2i , B N1i , B N2i ), pumping capacitor (CP), and the boosting capacitor or (C p1 ) where "i" represents the number of stages (i = 1,2, . . . n).
The bulk terminal of both the PMOS and NMOS transistors are connected to the respective source terminal to eliminate the body effect. The clock signals (Φ 1, and Φ 2 ) which have a clock amplitude up to V dd , are applied to the complementary CP pumping capacitors of branch 1 (B 1 ) and branch 2 (B 2 ). These branches are connected in parallel to the supply and output nodes. In response to Φ 1 and Φ 2 signals, the pumping capacitors in B 1 and B 2 charge alternately with V dd, in a repetitive process as the charges are stored in the capacitors and transferred to the output V OUT,CP . The bulk terminal of both the PMOS and NMOS transistors are connected to the respective source terminal to eliminate the body effect. The clock signals (Φ1, and Φ2) which have a clock amplitude up to Vdd, are applied to the complementary CP pumping capacitors of branch 1 (B1) and branch 2 (B2). These branches are connected in parallel to the supply and output nodes. In response to Φ1 and Φ2 signals, the pumping capacitors in B1 and B2 charge alternately with Vdd, in a repetitive process as the charges are stored in the capacitors and transferred to the output VOUT,CP.
The gate voltages of (MN12, BN22), (MN22, BN12), (MP12, BP22), and (MP22, BP12) are connected to the boosting capacitor through the nodes N23, N13, N21, and N11, respectively. In stage 2, the NMOS transistors are connected with the output node N23, N13 of the next immediate stage of the CP, and PMOS transistors are connected with the output node N21, N11 of the previous stage CP. This pattern of connection continues to the (n − 1) th stage. In the first stage, the gate voltage of the PMOS transistor is connected to the clock from the output node N21, N11 complimentary branches, due to the absence of a former stage. Besides, the nth stage has an additional pair of transistors with minimally sized capacitance to provide gate voltage for the n th stage NMOS transistor. To reduce leakage in the higher stage, the last three stages of the CP is constructed with thick oxide transistors, and the first three stages adopt nominal transistor for better conduction.
A performance comparison with the prior art is shown in Figure 10 where the charge pump output voltage is plotted versus time. However, to justify the performance, the conventional cross-coupled charge pump (CCCP) and the transistor-based Dickson charge pump (DCP) are recreated and simulated under the same test conditions by using similar transistor sizing, pumping capacitance, and other design parameters. It is evident that the proposed solution achieves the highest performance in the adopted lower technology node.  12 ) are connected to the boosting capacitor through the nodes N 23 , N 13 , N 21 , and N 11 , respectively. In stage 2, the NMOS transistors are connected with the output node N 23 , N 13 of the next immediate stage of the CP, and PMOS transistors are connected with the output node N 21 , N 11 of the previous stage CP. This pattern of connection continues to the (n − 1)th stage. In the first stage, the gate voltage of the PMOS transistor is connected to the clock from the output node N 21 , N 11 complimentary branches, due to the absence of a former stage. Besides, the nth stage has an additional pair of transistors with minimally sized capacitance to provide gate voltage for the nth stage NMOS transistor. To reduce leakage in the higher stage, the last three stages of the CP is constructed with thick oxide transistors, and the first three stages adopt nominal transistor for better conduction.
A performance comparison with the prior art is shown in Figure 10 where the charge pump output voltage is plotted versus time. However, to justify the performance, the conventional cross-coupled charge pump (CCCP) and the transistor-based Dickson charge pump (DCP) are recreated and simulated under the same test conditions by using similar transistor sizing, pumping capacitance, and other design parameters. It is evident that the proposed solution achieves the highest performance in the adopted lower technology node.

Control Circuit
The control circuit design is mandatory in the proposed architecture due to the configuration of two power paths. S1 and S2 are controlled by the common-gate comparator [49,50] and an inverter where the comparator is the main block in the control unit, which is shown in Figure 11. Yet, under low power mode, the device works in the sub-threshold region, where the current has an exponential relation respective to Vref, indicating that it is negligible. As the adopted 180-nm CMOS is enabled via the long-channel device, this feature favorably results in a lower current consumption deviating from the low-current conduction of the transistor.

Post-Layout Simulation Results and Comparison
The proposed stack rectifier technique implemented along with the SAB-RVCO and charge pump is adopted in a fully integrated dual-input RF energy harvesting system and implemented in a 180-nm CMOS process shown in Figure 12, where the post-layout simulation result includes parasitic extraction of the parasitic capacitance, parasitic resistance,

Control Circuit
The control circuit design is mandatory in the proposed architecture due to the configuration of two power paths. S 1 and S 2 are controlled by the common-gate comparator [49,50] and an inverter where the comparator is the main block in the control unit, which is shown in Figure 11. Yet, under low power mode, the device works in the sub-threshold region, where the current has an exponential relation respective to V ref , indicating that it is negligible. As the adopted 180-nm CMOS is enabled via the long-channel device, this feature favorably results in a lower current consumption deviating from the low-current conduction of the transistor.

Control Circuit
The control circuit design is mandatory in the proposed architecture due to the configuration of two power paths. S1 and S2 are controlled by the common-gate comparator [49,50] and an inverter where the comparator is the main block in the control unit, which is shown in Figure 11. Yet, under low power mode, the device works in the sub-threshold region, where the current has an exponential relation respective to Vref, indicating that it is negligible. As the adopted 180-nm CMOS is enabled via the long-channel device, this feature favorably results in a lower current consumption deviating from the low-current conduction of the transistor.

Post-Layout Simulation Results and Comparison
The proposed stack rectifier technique implemented along with the SAB-RVCO and charge pump is adopted in a fully integrated dual-input RF energy harvesting system and implemented in a 180-nm CMOS process shown in Figure 12, where the post-layout simulation result includes parasitic extraction of the parasitic capacitance, parasitic resistance, Figure 11. Common-gate comparator.

Post-Layout Simulation Results and Comparison
The proposed stack rectifier technique implemented along with the SAB-RVCO and charge pump is adopted in a fully integrated dual-input RF energy harvesting system and implemented in a 180-nm CMOS process shown in Figure 12, where the post-layout simulation result includes parasitic extraction of the parasitic capacitance, parasitic resistance, and parasitic inductance to create an accurate model of the circuit. Table 2 shows the transistor sizing of the proposed system. The active chip area of the entire system is 1.02 mm 2 while the proposed SAB-RVCO consumes an active silicon area of 0.037 mm 2 . and parasitic inductance to create an accurate model of the circuit. Table 2 shows the transistor sizing of the proposed system. The active chip area of the entire system is 1.02 mm 2 while the proposed SAB-RVCO consumes an active silicon area of 0.037 mm 2 .  The PCE of the RFEH system can be calculated as PCEsys(%), with the general formula given as: where Pout,main is the output power delivered to the load system, and Pin,imn is the input power received at IMN. However, the PCE of the primary path is sufficient to benchmark with the other reported work. In other words, the system PCE is predominantly determined by the efficiency of IMN (ηIMN), rectifier (ηrec), and PMU (ηPMU).
The input power versus the load in the main path is shown in Figure 13a-e with the corresponding contour plots of Vout,rec, PCE, Pout, and transient response of the RFEH system. Figure 13a shows the contour plot of the primary power path output voltage respective to the load, RL. A maximum Vout of 1.64 V is observed at Pin of 5 dBm and the optimal Vout respective to the PCE is shown in the green band. Figure 13b shows the contour plot of PCE, where the proposed system achieves a peak PCE of 21.15% with a 3.3 KΩ load at 0 dBm of input power and obtains a 5 dB wide dynamic range with a PCE of over 16%.  The PCE of the RFEH system can be calculated as PCE sys (%), with the general formula given as: PCE sys (%) = P out,main P in,imn × 100 = V 2 out,main /R L P in,imn × 100 (12) where P out,main is the output power delivered to the load system, and P in,imn is the input power received at IMN. However, the PCE of the primary path is sufficient to benchmark with the other reported work. In other words, the system PCE is predominantly determined by the efficiency of IMN (η IMN ), rectifier (η rec ), and PMU (η PMU ).
The input power versus the load in the main path is shown in Figure 13a-e with the corresponding contour plots of V out,rec , PCE, P out, and transient response of the RFEH system. Figure 13a shows the contour plot of the primary power path output voltage respective to the load, R L . A maximum V out of 1.64 V is observed at P in of 5 dBm and the optimal V out respective to the PCE is shown in the green band. Figure 13b shows the contour plot of PCE, where the proposed system achieves a peak PCE of 21.15% with a 3.3 KΩ load at 0 dBm of input power and obtains a 5 dB wide dynamic range with a PCE of over 16%. Figure 13c observes an output power of 423 µW at peak PCE and a maximum power of 1 mW at 5 dBm of input power. Figure 13d shows the reflection coefficient (|S 11 |)  V out,cp(ideal) (14) where V out,cp(actual) is the actual output DC voltage of the CP and V out,cp(ideal) is the ideal output DC voltage of the CP. The CP pumping efficiency is 99.23% at an input voltage of 0.2 V or V rec . This shows the proposed CP works well for lower supply voltage, which is preferred in a fully-integrated application. The proposed RVCO achieves a start-up at V rec = 70 mV. The power consumption of RVCO is 953 pW at 0.2-V of input voltage and is well fitted for RF energy harvesting systems. Table 3 summarizes the performance comparison with state-of-art RFEH systems [14,[22][23][24][25][26][27][28][29]. The proposed fully integrated RFEH system has a unique feature that incorporates dual-channel on-chip IMN, rectifier, capacitive DC-DC converters, and PMU. This allows two separate power path operations, one is connected with the appropriate load and the other helps to provide battery assist operation. In addition, the proposed RFEH system has a higher output power of 423 µW at peak PCE, compared to other recent reported work in Table 3 The RFEHs in [22][23][24] have better PCE, but they require off-chip components, which increase the physical form factor to more than 10 times the size of the proposed system, and these bottlenecks in the miniaturization of the device. Further, the RFEH systems [24][25][26]28] require to be fabricated at a cost-ineffective higher process node such as 65 nm/130 nm. In comparison to the on-chip integrated RFEH solutions in [25][26][27][28][29], the proposed work achieves higher sensitivity, PCE, and output power.

Conclusions
We presented a fully integrated multi-channel RF energy harvesting implemented in 180-nm CMOS. It adopted a shared-auxiliary-biasing technique to obtain V th reduction which yields an improved pumping efficiency of 99.23% for the CP circuit. The CP contains a SAB-RVCO, a buffer, and a charge-pump circuit designed and implemented in an integrated dual-input RFEH system. This work proposed a rectifier stacking technique to reduce the impedance and concurrently improve the quality factor Q achieving a 2.4 GHz multi-channel fully integrated RFEH system with 423 µW output power at a peak PCE system of 21.15% and a proposed charge pump support to reach a sensitivity of −14.1 dBm.