Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios

A reconfigurable gm-boosted, image-rejected downconversion mixer is presented in this paper using the SiGe 8 HP technology. The proposed mixer operates within 0.9–13.5 GHz that is suitable for software-defined radio applications. The conversion mixer comprises of resistive biased radio frequency (RF) section, double balanced Gilbert cell mixer core sections divided as per I and Q stages for image-rejection purpose, inductively peaked gm-boosting section and tunable filter section, respectively. In comparison to previous works in the scientific literature, the design shows enhanced conversion gain (CG), noise figure (NF), and image-rejection ratio (IRR). For the entire band of operation, the mixer attains a good return loss |S11| of <−10 dB. Additionally, the design accomplishes an excellent CG of 22 dB, NF of 2.5 dB, and an image-rejection ratio of 30.2 dB at maximum frequency. Finally, a third-order intercept point (IP3) of −3.28 dBm and 1 dB compression point (CP1) of −13 dBm, respectively, shows moderate linearity performance.


Introduction
Wireless communications have become increasingly popular due to the wide range of potential applications. In recent years, this industry has experienced tremendous development leading to many wireless standards. Therefore, it is desired to have a radio front end that is capable of handling multiple standards and applications [1][2][3]. For developing such receiver circuits, especially within high-frequency bands, proper radio frequency (RF) and baseband blocks must be available to perform downconversion operation. Ideally, distinct radio front ends can be used for different standards and applications. However, this is not possible due to frequency sensitivity [4,5]. Hence, RF-front-ends are compatible with distinct standards operating at specific frequencies. In addition, one must develop advanced systems with modern blocks with the emergence of the latest wireless standards. Reconfigurable blocks can be reused to accommodate multiple wireless standards, and thus lower development time and cost [6]. Software-defined radios (SDRs) offer this flexibility by allowing multiple band operations inside a single circuitry [7,8], whereas cognitive radios (CRs) take care of spectrum crowding and congestion hurdles [9,10]. Although most of the research is based on single-band cognitive radio, multiband cognitive radio has greater potential in the efficient implementation of cognitive networks. It is expected that multiband cognitive radios improve the throughput and lower handoff frequency for better channel maintenance. However, wideband front end and access to multiband spectrum present several challenges [11]. Thus, the best is to have CR with SDR features, which can sense the electromagnetic spectrum environment, tracking and responding to the variations and findings in a smart way. Moreover, the cost and power consumption are significant while talking about reconfigurable receiver architectures [12]. Earlier receivers were using analog-to-digital converters. Signal processing is carried out in the digital domain that Hence, for proper reconfiguration to occur, it is important to have perfect tuning based on the above-mentioned approaches.
Gilbert mixer is quite common among SDR receiver architectures as they can provide high bandwidth and broadband performance without degradation in the performance parameters [31]. Several mixer designs have been discussed in [32][33][34][35][36][37]. As in [38], improved Gilbert mixer design is proposed that attains reasonable CG and high port isolation while operating within a wideband. Likewise, in [39] a reconfigurable Gilbert mixer is proposed that employs a passive switchable network (a combination of switched capacitor and inductors) for tuning purposes, resulting in a highly flexible design. The design attained high CG, moderate IP3 at the expense of NF. To overcome the issues within the abovementioned designs, a joint LNA + mixer-based design can be used. The proposed design maintains a small chip size and consumes less power [40]. Noise-cancelling plays an important role for such a front-end topology. However, it depends on the proper metric matching based on I/Q mixer topology. Another common approach is to use partial noise-cancelling with a folding mixer architecture with no current reuse, specifically for wideband and low power operation. In this case, g m -boosting is the better option, which is independent of performance metrics matching as used in LNA section. Finally, in [5], a g mboosted technique is employed in the RF stage of the mixer that helps in CG improvement with low power consumption.
Based on the above-mentioned approaches, a novel Gilbert mixer is proposed that employs g m -boosting technique with high image rejection. For tuning purposes, the ninthorder tunable resonator has been developed using varactors and inductors, where the varactors are responsible for providing tuning behavior within the mixer. In this paper, we discuss the design and analysis of the mixer achieving tunable input-output matching from 0.9 GHz to 13.5 GHz. The rest of the paper is organized as follows: Section 2 focuses on motivation. Section 3 presents the mixer design, followed by the analyses of the proposed mixer in Section 4. Section 5 discusses about the simulation results and the layout of the proposed mixer. The proposed mixer's reliability performance is analyzed using Relxpert software as discussed in Section 6 and finally Section 7 concludes the paper.

Motivation
A merged LNA and mixer circuitry is shown in Figure 1. It consists of g m -boosting section, and a source inductor at the input end. At the output end capacitors and inductors (ignoring parasitic resistance) are connected to the LNA section. LNA and mixer employ g m -boosting and current bleeding techniques, which makes the design capable of attaining high CG, low NF, and low power consumption. The design also employs the current peaking approach for wideband operation [40]. Therefore, the input and output impedance can be expressed using a small signal model as shown in Figure 2.
Input impedance, Z in can be expressed as: where C gs1 refers to the gate to source capacitance at the input end. G m -boosting helps in overall gain improvement as it improves the overall transconductance in the stage to which it is connected by the factor (−A) as shown in Figure 1. Upon analysis, it can be expressed as where G m1 refers to g m -boosting term; g m1 , r 01 , and Z L refer to the transconductance, transistor impedance, and load impedance, respectively. Similarly, the output impedance, Z L can be expressed as: where C 1 , C 2 refers to the interstage parasitic capacitance. g m3 and g m4 refer to the transconductance of M 3 and M 4 transistors. As per the input network, the resonant frequency depends on C gs1 and L 1 . The resonant frequency at which the input impedance, Z in will be real can be defined as Therefore, to attain the tunable frequency, f 0 and input impedance, it is desired for Z in to use the tunable filter components. This will enhance not only the overall chip area and power consumption but also the performance metrics such as noise figure. In this paper, we propose an active mixer with a tunable filter, comprising of variable capacitors and inductors. Therefore, in order to attain the minimum return loss, S 11 at each centered frequency, the input impedance can be varied with the variation in the current. To improve the performance of the circuitry, the design also employs the g m -boosting technique.  Figure 3 shows the block representation of the proposed mixer with different stages. Starting from the bottom, Stage I refers to the transconductance stage that follows a common source configuration. Stage II refers to the core section categorized into LOI (local oscillator in-phase) and LOQ (local oscillator out-of-phase) stages where input signals are in 90 degree phase shift with respect to each other. For coupling, transconductance and core stages, coupling capacitors have been used. The third stage refers to the g m -boosting stage and finally, stage IV discusses the filters, i.e., first-order filter for avoiding leakage from the power supply and the ninth-order tunable filter for impedance matching at RF and IF stages. For a better understanding of the proposed circuit topology, the design and analysis of all stages have been discussed as follows.

Transconductance
Stage (RF+)   Figure 4 shows the complete circuit diagram of the proposed mixer. Based on the design, the transconductance stage follows the common source configuration and is categorized into different sections, i.e., RF+ and RF− stage, respectively. Both RF+ and RF− stages consist of resistors arranged in a shunt configuration with RF+ stage that consists of input resistors R 1 , R 2 , and R 3 . Similarly, RF− consists of input resistors R 5 , R 6 , and R 7 , respectively. R 1 and R 5 resistors are responsible for the overall input resistance of each stage and can alter the input voltage and hence the overall gain performance. R 4 and R 8 refer to the load resistors opted while keeping the desired drain current I D . Filters are also linked to the input end of these stages for impedance matching purposes. Transistor W/L ratio is in such a way that it satisfies the core stage transistor saturation region operating conditions. The input, output impedance, and gain expression of the RF stages can be obtained with the help of the equivalent small signal model. Figure 5 shows the small signal model while ignoring the filter whose analysis is discussed in the filter section. Therefore, for the RF+ stage R in is the internal resistance, R G refers to the gate resistance, which is the parallel combination of R 1 , R 2 , and R 3 respectively. Input impedance of RF+ stage  T0  T1  T2  T3   T4  T5  T6  T7   T8   T9   T10   T11   T12   T13   IFQP  IFQN   IFIN  IFIP   T14 T15 R1
Output impedance of RF+ stage where R 1 = r ds 14 = R 4 , sC 1 = sC db14 + sC 3 . Similarly, the input impedance of RF-stage can be represented as Output impedance of RF− stage where R 2 = r ds 15 = R 8 , sC 2 = sC db15 + sC 4 . Therefore, to obtain the frequency response of the small signal circuit, nodal analysis can be done. The first term should be the node at which the currents are added. If node voltages are multiplied, it refers to all admittances being connected to a node. Next terms will have negative signs which are actually neighboring node voltages and each of these terms uses a multiplication operation on the connecting admittance. The final terms refer to the current sources having a positive sign that is considered only if current sources are flowing out of that node [41]. Based on this, we have As V 1 = V gs , then from Equation (10), we get; By substituting (11) in (9), we get; R in is not used and upon simplification and converting G G , G 1 to R G , R 1 , we get; If s = 0, the low frequency gain is obtained as mentioned below: When the poles are real and The denominator of Equation (13) becomes Comparing Equation (13) with Equation (18), we get Similarly, for RF− stage, the simplified gain can be expressed as mentioned below:

Core Stages
It is well known that the image signal is an unwanted input signal to the mixer. Its frequency will be above or below the local oscillator (LO) frequency by an amount which is equal to the IF frequency. Suppose if f R1 is the frequency of the desired input signal, then f R2 is for its image. Thus, both image and actual input signals mix with the LO and will downconvert to the same frequency. This is problematic for the mixer as both downconverted products interfere with each other as they exit at the IF port together. Thus, by using separate LO stages will overcome this problem and the outputs will be obtained at different IF stages. Based on this phenomenon, two core stages have been developed for the proposed mixer whose outputs will be obtained at different IF stages. The switching stages steered by LO inputs are classified as in-phase (I) and quadrature-phase (Q) stages for image-rejection purposes. Both LO stages contain p-type field effect transistors (FETs) for flicker noise reduction purpose, the transistors T 0 -T 3 ,T 4 -T 7 are the part of LOQ and LOI stages, respectively. Alternate transistors in each stage form a differential pair and operate alternatively when LO pulse is applied. Hence, differential outputs will be obtained and the current switch between outputs. The output current is directly proportional to the input current and the signal that is applied at the gate terminals. For determining the output voltage, the current flowing through load resistors is considered along with the load resistors itself. In the design, coupling capacitors are used to couple RF and LO stages. The small signal model for obtaining the output voltage with respect to the current obtained from the RF stage is shown in Figure 6. The model uses Kirchoff's current law (KCL) for analysis. Therefore,

Gm-Boosting Section
G m -boosting circuitry is connected to core stages, which is responsible for the transconductance improvement. Hence, the conversion gain will be enhanced while controlling the power consumption [5]. The proposed design employs peaking inductors at the gate of the transistors. These inductors resonate with the parasitic capacitances and are responsible for avoiding current leakage. The design also employs P-type FETs (T 8 and T 11 ) connected to V dd . However, (T 9 -T 12 ) are N-type FETs. The design follows the stacking structure, where transistors T 9 and T 12 act as an amplifier that improves g m and overall gain by a factor of (−A). Transistors T 10 and T 13 are responsible for delivering the current to the connecting stages. All transistors are operating in the saturation region. The drain current will start flowing in the core stages, the current obtained from this stage will bleed to transconductance stage. Hence, the current will be reused by the transistors T 14 and T 15 , respectively. The equivalent circuit for the g m -boosting stage is shown in Figure 6.
When the transistors T 8 , T 10 , T 11 , and T 13 are operating in the saturation region, the current flowing through that stage is given by: Similarly, for the other section The LO switches are considered ideal. Therefore, during the positive half of LO pulse, the output current will be positive; during the negative half cycle, the current obtained will be negative. The total current due to the half LOI stage is represented as: This current is transferred to the LOQ stage, then the current within this stage will be due to LOI and the stage itself As the coupling capacitors connect the LO stages to the RF stage, the overall boosting can be observed in terms of CG, where the g m stage is acting in parallel with the load at the IF end. Moreover, g m -boosting inductor L 3 or L 4 present within the design are responsible for gain improvement. The design analysis is explained as per the positive feedback theory whose model is shown in Figure 7 . For using this principle, the T 9 signal paths are taken into consideration and output impedance has been ignored for simplicity. Thus, due to presence of L 3 or L 4 a non-zero impedance can be observed at the gate terminal of T 9 . The feedforward and feedback paths are considered using parasitic capacitances such as gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd), respectively. Thus, gate-source voltage of T 9 becomes V g,T9 while considering new signal paths. The next step is to calculate the open-loop voltage gain as per voltage-voltage feedback configuration. Hence, the voltage at the drain terminal is expressed as where V gs9 , g m9 and Z nB refers to the gate to source voltage of T 9 , transconductance of T 9 and output impedance at node nB that includes the duplicate, respectively. where where Z ' nB , α, C gd9 and C gd8 refer to the output impedance excluding the duplicate, voltage ratio from source to gate, parasitic capacitances for T 8 and T 9 , respectively. Thus, the openloop gain is represented as where where β is the feedback factor from drain to gate Hence, it has been verified from the above equations that the gain has been boosted in the presence of the inductor.

Filter Section
Filters present at the input and output stages are responsible for impedance matching at various frequencies within a band. However, the ones near the core stage prevents signal leakage from the power supply. Various filters have been proposed and the most common techniques are transmission lines, transformer dependent programmable or spiral inductors, and dual-behavior resonator topology [42][43][44][45]. However, these filters are limited to some extent and may cover a large area. Therefore, off-chip filters can be used but easy integration is not possible and they are expensive as well. Hence, the most convenient approach is to develop an image-rejected mixer that employs different filters. We propose ninth-order band pass tunable filters for impedance matching purpose which are present at the RF and IF stages of the mixer as shown in Figure 8. Moreover, Figure 9 shows the design of first-order bandpass filter present at the source terminals of the LOI stage transistors at one end and the power supply at the other end to avoid leakage from the power supply.  The input and output impedance of the ninth-order filter section can be expressed as a combination of series and parallel LC sections within the design. The filter order depends on the number of LC pairs. The input impedance, Z in is expressed as: For simplicity, different letters have been used to represent the LC combinations. The output impedance, Z out is expressed as: Similarly, the first-order impedance depends on the parallel combination of L and C.
The resonant frequency at which the impedance, Z P will be real can be defined as where Z P refers to the parallel circuit impedance. The resonant frequency varies depending on the selected filter circuit within the design. Figure 4 shows the complete structure of the designed mixer with g m -boosting, common source configured transconductance stage and Gilbert cell core stage. The first step is to determine the band of operation. The next step is choosing the design topology and filters for successful reconfiguration. The design uses Gilbert topology responsible for improving the overall CG, NF. To further enhance this performance, g m -boosting with inductive peaking is employed. The design is structured to provide good image rejection as well without affecting performance of the design. Figure 10 shows the complete small signal model used for obtaining the overall CG within the design. The CG, A v is represented by the expression below:

Conversion Gain
where all expressions in Equation (55) For determining i RF (s RF )/V gs14 (s RF ) ratio KCL is applied, and we obtain the expression below: Rearranging the above equation, we get; By substituting (56)-(61) into (55), the overall CG can be obtained. Figure   Figure 11 shows the noise model for the proposed circuit. In the circuitry, all passive elements are considered ideal, and the most important noise source is thermal noise, based on which the power spectral density of each stage is obtained. The design consists of resistors and transistors, respectively [41,46]. Equation (62) defines the power spectral density, which is the combination of the power spectral density obtained from all stages present within the design.
Hence, the noise figure of the proposed mixer is expressed as Moreover, for analyzing the high-frequency noise in the proposed mixer, the thermal noise due to resistors, the thermal noise due to drain, and gate of FETs are considered [47]. The noise contribution due to RF, LOI, LOQ and output stages are considered for the proposed mixer.
Starting with the noise contribution from the RF stage as per Figure 12, the noise signal at the output of the transconductor when multiplied with the switching pair's instantaneous current gain p 1(t) results in a current noise , i o14(t) as i o14(t) = n o14(t) p 1(t) (73) By considering the above process as a time-average wide sense stationary process, the power spectral density of the noise current is expressed as For the overall analysis of power spectral density at the RF stage, both correlated and uncorrelated power spectral density factors have to be considered. Thus, the uncorrelated power spectral density is expressed as where R G014 , r g014 refer to the external gate resistance (parallel combination of the resistors) and internal gate resistance.
Likewise, the correlated power spectral density can be expressed as Thus, the overall power spectral density is expressed as Next, the power spectral density due to LO stages is expressed as 2 ) ] + (k c + 1) 2 As 45 Considering the noise present at LO ports are stationary. Thus, time-averaged power spectral density of current noise at the output of the proposed mixer due to LO stages is expressed as where R LOI , R LOQ refer to equivalent noise resistances and r G1 , r G2 refer to poly gate resistances. As the image signal does not carry any important information, therefore the single sideband noise figure is considered over the double sideband noise figure as The above expression is defined for a single balanced mixer. Similarly, for the double balanced mixer, NF can also be defined which is almost twice the one obtained for a single balanced mixer.

Results and Discussion
The proposed mixer is designed and simulated in the SiGe 8HP process technology. To boost the transconductance within the RF stage, g m -boosting technique has been used in the design, which leads to good CG performance. Figure 13 shows the pre-and post-layout simulation results for the conversion gain performance of the proposed mixer. As depicted in Figure 13, the CGmin and CGmax values are quite similar for both simulations. However, variation can be observed at other frequencies within a band that can be discussed by considering the parasitic effects. The pre-layout CG at the center frequency, 7 GHz is 18.39 dB and after layout, it degrades to 17.7 dB. Due to the parasitic effects of passive components within the circuitry, the CG degrades after the final layout. In particular, the quality factors of the inductors within the circuitry are responsible for the gain performance degradation. Moreover, the parasitic resistance within the inductors can also lower the voltage gain within the circuitry.  Figure 14 depicts the NF of the mixer with the variation in frequency. The simulation results show that NF is less than 3 dB before pre-layout simulation and raised by 0.8 dB upon post-layout simulation at the maximum frequency. This performance has also been affected by the parasitic effects of passive components. It also has dependency on the number of resistive components, transistors, and conversion gain performance of the design. This mixer exhibits good NF with a variation of ±1 dB across the entire frequency range. The linearity performance of the mixer has been shown in Figures 15 and 16, respectively. The design is considered linear if it shows proportional behavior within the input and output. This behavior can be observed using third-order input intercept points (IP3) and 1dB compression point (CP1). The actual behavior of the mixer is well depicted in terms of pre-and post-layout simulation results. As per the simulation results, it has been observed that the design attained moderate linearity behavior when observed at different frequencies in a band where IP3 is 10 dBm higher than CP1.
The image-rejection ratio is an important aspect while designing the mixer as depicted in Figure 17. When desired and image signals enter the input together, it degrades the overall performance of the circuitry and waste power. Therefore, to overcome this problem, the image signal must be rejected which is done in the proposed design. The mixer attains a good IRR of 28.91 dB at 10.46 GHz upon performing pre-and post-layout simulations. The maximum IRR is around 30 dB, which is within the normal specified IRR range of 20-40 dB.   Figure 18 shows the return loss performance with respect to frequency. As per simulation results, the |S 11 | is below 10 dB at each centered frequency for the entire tuning band, which is as low as −22.42 dB at 11.91 GHz and 13.22 GHz, respectively.  Figure 19 shows the layout of the proposed mixer designed in 8 HP process technology covering around 1.98 mm 2 area. The design consists of different sections as discussed in detail in Section 3. The filter section consists of spiral inductors and capacitors. Inductors used provide accurate inductance values and are capable of achieving the maximum Q at a desired operating frequency. Additionally, variable capacitors, i.e., varactors, are used to attain the tuning capacitance.  Table 1 summarizes the performance of the proposed mixer and provides a comparison of the circuit with the recent works. As per Table 1, the achievable NF is as less as 2.5 dB and the maximum S 11 is −20 dB. As CG increases, the IP3 gets degraded due to CG-IP3 trade-off. Moreover, the maximum IRR is 36 dB. The overall area of the proposed mixer is higher than the other reported designs. However, the design attains high performance in terms of CG, NF, IRR and S 11 simultaneously at the expense of IP3 which is the best among all reported works in the literature.

Design Reliability
Conventional designs were less focused on reliability analysis due to the process and design guide limitations. However, in recent years it is important to consider reliability of the designs due to time, budget, scaling and demanding profile constraints. Relxpert tool developed by Cadence is used to simulate PFET and NFET devices for determining the device degradation performance where performance is evaluated as a function of stress time and biases. Relexpert output can be observed as a "corner in time" that moves towards slow corners in case of simulation from a typical corner. This process helps the designers in analyzing the degradation in circuit behavior during the initial design flow stages [58]. Degradation performance has been evaluated in terms of all performance parameters such as CG, CP1, IP3, NF and IRR ratio. Figure 20 shows the performance of the proposed mixer in terms of IRR and NF with 5 years of aging. From the plots it has been observed that both IRR and NF show degradation; however, more degradation can be observed in NF in comparison to IRR. Figure 21 shows the performance of the proposed mixer in terms of linearity parameters and it has been found that the linearity will degrade as expected as such variation is observed after post-layout simulation results as well. However, the NF is still ≤ 5 dB within the entire band, which is expected for a mixer. The behavior of the gain can be observed from Figure 22 which shows the performance of the proposed mixer in terms of gain. Based on the curve, it has been found that the gain degradation is very less as it reaches to 21.5 dB after 5 years and at present it is around 22.1 dB. Thus, the proposed mixer is reliable for future SDR applications.

Conclusions
In this paper, a novel reconfigurable I/Q Gilbert mixer has been proposed, which is designed and simulated in SiGe 8HP process technology. ninth-order tunable LC filters are embedded at the RF and IF ports for port matching and NF improvement. Moreover, a first-order tunable filter is employed to avoid the leakage through the power supply. The proposed design shows improved transconductance by using G m -boosting technique. Additionally, the employment of peaking inductors compensates for the gain reduction at high frequencies, while extending the overall bandwidth and hence results in a high gain. Based on the simulation results, with a 1.2 V power supply, the design attains a maximum gain of 22.1 dB. The input return loss is <−10 dB and achieves a minimum of −22.7 dB at 11.9 GHz and 13.22 GHz, respectively. Furthermore, NF ranges between 2.5 and 5.6 dB. The design also shows good IRR within the entire band. Thus, the proposed mixer is compatible enough to meet the future demands of software-defined radios.

Conflicts of Interest:
The authors declare no conflict of interest.