A Time-Based Electronic Front-End for a Capacitive Particle Matter Detector

This paper introduces the electronic interface for a capacitive airborne particle matter detector. The proposed circuit relies on two matched ring oscillators and a mixer to detect the frequency difference induced by the deposition of a particle onto an interdigitated capacitor, which constitutes the load of one of the oscillators. The output of the mixer is digitized through a simple counter. In order to compensate the oscillation frequency offset of the two ring oscillators due to process and mismatch variations, a capacitive trimming circuit has been implemented. The sensor is connected to host through an I2C interface for communication and configuration. The sensor has been implemented using a standard 130-nm CMOS technology by STMicroelectronics and occupies 0.12-mm2 die area. Experimental measurements using talcum powder show a sensitivity of 60 kHz/fF and a 3σ resolution equal to 165 aF.


Introduction
Atmospheric particle matter (PM) is a category of airborne pollutants that includes dust, tobacco smoke, diesel exhaust, and other primary sources. Fine particles that have a diameter between 10 µm (PM 10 ) and 2.5 µm (PM 2.5 ) represent a threat for human health because of their ability to penetrate deep into the respiratory system. Indeed, exposure to PM 10 and PM 2.5 has been linked to a reduction of the life expectancy between 8 and 36 months [1][2][3][4][5][6][7][8][9].
Conventional methods to monitor PM concentration are based on gravimetric or laser scattering detection methods that are bulky, costly, and do not allow appropriate spatiotemporal resolution. With the aim of reducing the sensor volume and enable ubiquitous PM measurement, solutions exploiting high-resolution capacitive sensors have been recently proposed [1,2,4,6,9]. As well known, capacitance detection represents a universal transduction mechanism, leveraged in a large variety of sensors and applications, thanks to the smartness and the conceptual simplicity [10], [11].
Capacitive PM detection represents, however, a challenging task due to the small capacitance variation induced by a single particle. Indeed, a particle with a radius between 1.25 µm and 20 µm induces over a planar capacitor a capacitance variation in the order of tens attofarad. [3][4][5]. However, in the case of a parallel and planar faces capacitor, which requires additional steps during the fabrication process, the variations would be an order magnitude bigger [1,12].
The electronic front-end therefore plays a fundamental role because it defines the ultimate resolution limit, power consumption, and area occupation of the overall sensor. Given the importance and widespread diffusion of integrated capacitive sensors, it is quite understandable that many different electronic interface topologies have been presented in literature, such as capacitance-to-voltage (C2V) [1][2][3][4][5]10,[13][14][15][16][17][18], charge based capacitance measurement (CBCM) [19][20][21][22][23][24][25][26][27], capacitance-to-current (C2I) [28][29][30], capacitance-to-time (C2T) [31][32][33][34][35], and capacitance to digital (C2D) [36][37][38][39][40][41][42]. Each method presents very different features in terms of resolution, area occupation, circuit, complexity, measuring range, and measuring time. Consequently, the adoption of a specific topology depends upon the constraints given by the particular application [11]. As an example, among the solutions in literature, only that reported in [4], which is based on C2V lock-in topology, shows a value of the resolution as low as low as 65 zF and targets PM detection. However, this is achieved at the expense of high-power consumption, area occupation, and partial on-chip implementation [11]. Regarding area occupation, solution in [29] based on C2I topology achieves a very low value of occupied area (0.03 mm 2 ), but this comes at the expense of worse resolution (800 aF). Similar conclusions can be carried out for all the other topologies [11]. However, a key aspect to consider is represented by circuit complexity, especially when several replicas of the same circuit must be implemented to process an array of capacitive transducers. In this case, CBCM and C2T topologies represents a good choice. Another aspect to consider when selecting a particular topology is represented by the availability of a digital output. Among the various solutions, only C2D topology inherently provides a digital output, although also C2T solution can achieve this feature by exploiting a simple counter. All of the other solutions require additional ADC converters, which increases further area and power consumption.
With the aim of implementing a fully integrated, simple, while effective, electronic front-end for a capacitive-based PM detector, in this paper we propose a circuit topology, based on C2T architecture, to detect the capacitance variation of a planar capacitor due to the deposition of PM. The proposed solution is based on the calculation of a frequency difference between two identical and matched ring oscillators, where the reference one exhibits always the same oscillating frequency, and the second one exhibits a varying oscillating frequency due to the variation of the permittivity of the sensing capacitor. A digital output is obtained by exploiting a counter and an I2C interface, which is also exploited to trim the frequency of the ring oscillators.
The remainder of this paper is organized as follows. Analysis, design, and simulation results of the proposed system are reported in Section 2. Section 3 reports the experimental measurements and a comparison with the state of the art. Finally, concluding remarks are drawn in Section 4.

Electronic Front-End Design
The simplified block diagram of the electronic front end is shown in Figure 1. It is composed by a reference ring oscillator (RO) and another RO whose frequency changes according to the capacitance variation induced by the deposition of PM on sensing capacitors connected at the output of each stage. The frequency difference between the two oscillators is detected through a mixer and a low-pass filter. Finally, a Schmitt trigger and a counter are exploited to get a digital binary word whose value is proportional to the capacitance variation. The core of the proposed system in Figure 1 exploits a similar principle of operation as that introduced in [32], where, however, the reference and sensing signals are processed by an XOR gate, which generates a signal whose frequency is the maximum common divider of the two input frequencies, which can assume the same value for different combinations of f s and f ref . This drawback is overcome using the mixer in the proposed system.

Description and Analysis of the Main Building Blocks
The schematic of each RO is shown in Figure 2. The load capacitor of each stage is made up by an interdigitated integrated capacitor, C S , which is exploited to detect the particles. An equal capacitor is used for the reference oscillator, but this is isolated from the environment by means of an oxide. Capacitor C load is equal to C S0 + C PAR + C TRIM , being C S0 the nominal value of the sensing capacitance, C PAR the intrinsic parasitic capacitance of the inverter, and C TRIM the absolute capacitance of the trimming block, which is described in detail in Section 2.3. Assuming that the two ROs share the same power supply, the oscillation frequency of the sensing and reference RO is respectively given by where I avg,s and I avg,ref is the average current of each stage of the sensing and reference RO, respectively, V DD is the supply voltage, and ∆C i represents the capacitance variation of the i-th stage sensing capacitor of the sensing RO. A passive RC low-pass filter is used at the output of a passive mixer Figure 3 to eliminate high frequency components. After that, a Schmitt trigger Figure 4 converts the signal to a square wave, which is finally fed to a binary counter. Assuming ideal operation of the mixer, the low-pass filter, and the Schmitt trigger, the frequency difference of the signal at the input of the counter due to a total capacitance variation (Note that the capacitance variations at the output of each stage are in general different from each other.) is expressed, using Equation (1), by where it is assumed that the average current is equal for all the stages. The rightmost approximation in Equation (3) holds assuming small capacitance variations (Although Equation (3) shows a hyperbolic dependence on ∆C, it can be approximated with its series Taylor expansion truncated to the first term which is equal to the rightmost term of (3)). From Equation (3), it is apparent that the frequency difference is increased when C load and N are decreased (i.e., when the nominal oscillation frequency is maximized). This can be achieved by reducing the parasitic capacitance of the inverters, by reducing the nominal value of the sensing capacitor and, in particular, by adopting the minimum number of stages.  The number of counts at the output of the counter can be simply obtained by multiplying the frequency of the filter by the reset period of the counter, thus yielding From Equation (4), it apparent that the counts are proportional to the ratio between ∆f and f ref and, consequently, the dependence on supply voltage and average current is eliminated.
Assuming a minimum and maximum detectable frequency variation equal to ∆f max and ∆f min , respectively, the number of bits of the counter is given by Finally, by combining Equations (4) and (5), we obtain the value of the frequency divisor as The minimum detectable capacitance variation is limited by the noise of the various building blocks in Figure 1. A simplified noise analysis can be carried out assuming that all the noise sources are uncorrelated and neglecting the jitter introduced by the mixer, low pass filter and Schmitt trigger. Consequently, the main source of jitter is assumed to be the two ROs. Using results in [43], the total jitter variance of a RO based on CMOS inverters due to white noise is given by where k is the Boltzmann constant, T is the absolute temperature, f 0 is the nominal oscillation frequency expressed by Equation (1), V th is the PMOS and NMOS threshold voltage, γ N and γ P are the channel noise factors equal to 2/3 in saturation region. The signal-to-noise ratio is then evaluated as where σ ref and σ s is the jitter variance of the reference and sensing RO, respectively.

Simulation Results
The proposed system in Figure 1 has been designed using the 130-nm HCMOS9A technology by STMicroelectronics. The RO are designed assuming V DD = 1.2 V and, according to Equation (3), setting N = 3 to maximize the sensitivity and the SNR. The resolution of the counter is set according to Equation (4) with ∆f LSB = 2.4 kHz and ∆f MAX = 625 kHz (which corresponds to a maximum detectable capacitance variation of about 10 fF) and is equal to 8 bits. The frequency divisor from Equation (5) is the equal to 2 15 . The other parameters are reported in Table 1, which yields a nominal oscillation frequency equal to 79.9 MHz.  Figure 5 shows the post-layout simulation of the signal at the output of the sensing and reference oscillator, the mixer, the low-pass filter and the Schmitt trigger for ∆C i = 1 fF. The frequency of the signal at the output of the trigger is equal to 60 kHz, as predicted by Equation (3). The simulated noise produces an uncertainty of the measured frequency variation, which determines the minimum detectable capacitance variation. In particular, a noisetran simulation over 50 runs with ∆C i = 1 fF gives a mean frequency variation value that coincides with the value predicted by (2) with ∆f RMS ≈0.8 kHz. Considering a Gaussian distribution of noise, we should set as minimum resolution 3∆f RMS ≈2.4 kHz, which corresponds to a 3∆C RMS = 40 aF. This value is calculated at the output of the mixer.
The frequency of the signal at the output of the Schmitt trigger as predicted by Equation (3) is proportional to the average charge current. Consequently, it is expected that the frequency varies with temperature. By inspection of Equation (1), the same conclusion applies for the reference ring oscillator. As a confirmation of these observations, Figure 6 shows the post-layout simulation of the frequency of the signal at the output of reference oscillator and the Schmitt trigger, respectively, versus temperature for ∆C i = 1 fF. The temperature coefficient of the signal at the output of the trigger over the industrial temperature range (−40:80 • ) is equal to −108 Hz/ • C, while the one of the reference signal is equal to −126 kHz/ • C. The simulation results in Figure 6 is coherent with the analytical model carried out in Section II.A, as detailed in Appendix A.
Finally, Table 2 summarizes corner analysis results assuming ∆C i = 1 fF.

Design of the Capacitive Trimming Circuit
Mismatch and process variations cause a random offset of the nominal oscillation frequency of the two ROs, which in turn increase the minimum detectable capacitance variation. Monte Carlo simulations in Figure 7 show that, imposing a capacitance variation equal to 4.1 fF, around the nominal output frequency (µ = 246.689 kHz), the standard deviation, σ, is equal to 80 kHz. Thus, we must be able to trim at least 240 kHz (3σ). To reduce the offset at the output of the system due to process and mismatch variations, a capacitive trimming circuit is adopted to change the C TRIM load capacitor and re-tune the oscillation frequency to the nominal value. At this purpose, the capacitive trimming circuits must be able to induce a frequency variation equal to about ±3σ = ±240 kHz, or 480 kHz as entire range.
The schematic of a single capacitive trimming circuit is reported in Figure 8. It is made up by five binary weighted capacitors, C 1 -C 5 . The minimum capacitor, C 1 , is equal to 20 fF. To increase matching, all the other capacitors are obtained by paralleling a proper number of minimum capacitors. Five switches, controlled through the I 2 C interface, are used to get 32 different configurations. Bridge capacitors C 6 , C 7 , and C 8 are used to reduce the capacitance variation (Considering that the sensitivity is equal to 60 kHz/fF, a variation of 4 fF is required to fully cover the error range of 240 kHz). The equivalent capacitance implemented by the capacitive trimming circuit is expressed by where C X is the equivalent parallel capacitor, which is a function of the switch configuration. Parasitic capacitances introduced by switches and metal connect can heavily affect trimming since they are commensurable to the capacitance variation to be measured. Consequently, a good layout strategy is mandatory. In order to preserve symmetry, every capacitance in Figure 8 has been divided in two and driven by two equally driven switches. The remaining capacitances have been connected to minimize metallization length and, as usual, adding dummy components to equalize boundary condition.
The capacitive trimming circuit is replicated also in the reference oscillator to cover the required frequency variation range (±3σ = ±240 kHz). Figure 9 reports the comparison between the frequency variation predicted by Equation (3) introducing the trimming capacitance Equation (9), the post layout simulations, and the measurement results. It is apparently a good fit between the three curves.  Figure 10 shows the microphotograph of the implemented system. The sensing capacitors are completely exposed through the removal of the passivation and the 200-nm nitride silicon layers. The reference capacitor, on the contrary, was passivated. This design choice, however, introduced an additional mismatch between the loading capacitors of the reference and sensing ROs. Consequently, the resulting frequency difference at the output of the Schmitt trigger at standby conditions was only partially compensated by the capacitive trimming circuit because the overall mismatch was higher than the one predicted in simulations. To get rid of the additional mismatch caused by the passivation of the reference capacitor, the oscillators were powered using a different power supply generator.

Measurement Results
Total occupied area is 0.12 mm 2 , including front-end, sensor, and reference capacitances. In particular, the electronic front-end occupies 0.06 mm 2 , while the remaining 0.06 mm 2 are due to the reference and sensing capacitors.
The measurements have been carried out through the deposition of talcum powder particles (ε r = 2) over the sensing capacitors. During experimental measurements, three main cases have been considered for the electrode coverage, namely low coverage, medium coverage, and high coverage. Figure 11 shows the microphotograph of the electrodes in the three considered conditions. Measured signals at the output of the trigger are reported in Figure 12. In the first case (low coverage), the measured ∆f is equal to 5 kHz, which corresponds to a total capacitance variation of ∆C = 83 aF. In the second case (medium coverage), ∆f = 10 kHz that is related to a total capacitance variation ∆C = 166 aF. Finally, in the last case (high coverage) ∆f = 18 kHz and ∆C = 300 aF.  In order to assess the validity of the measured capacitance variation induced by the talcum deposition, each case has been simulated using COMSOL Multiphysics, as detailed in the same Figure 11. Every capacitor in each case shows a different covering talcum concentration and thus a different capacitance variation. In particular, in the low coverage case, moving from the leftmost pixel to the rightmost one, the variations are respectively 0 aF, 111 aF, and 113 aF. In the medium coverage case, they are 146 aF, 148 aF, and 152 aF and finally, in the high coverage case, they are 114 aF, 1024 aF, and 45 aF. By looking at Equation (3), it is obvious that in case the variations are different, by making the average through the dividing N factor, it falls back in case they are equal. By this operation, the equivalent variations are 74 aF, 148 aF, and 394 aF. Note that there is a good matching between the predicted and measured values in the first and second case, where the model better describes the measured case. In the last case, the error between simulation and measurement is higher due to the difficulty of accurate modeling the actual distribution of the particles over the electrodes. Similar measurements were executed on other eight samples with similar results.
The reading error of the sensor is due to electronic noise and to the quantization error introduced by the counter. This error leads to a minimum detectable capacitance, i.e., it determines the resolution. It has been assessed by evaluating the mean value and standard deviation of 20 consecutive readings. The mean value of the hexadecimal word has been multiplied by the resolution of the counter and then compared to the output trigger frequency, resulting in a very good matching. Table 3 summarizes the measurements executed on the first sample, showing a 3 resolution equal to 165 aF in the worst case. With the purpose of also demonstrating the temperature behavior expressed in the second section, measurements inside a controlled oven were executed, whose results are shown in Figure 13. The measured curve shows a positive temperature coefficient equal to 6 kHz/ • C. Although this behavior seems at first sight to contradict the results reported in Figure 6, it is coherent with the analytical evaluation reported in the Appendix A. Indeed, in experimental measurements the passivation of the reference capacitor led to a load capacitance of the reference RO higher than that of the sensing RO. Consequently, as predicted by (A4) in the Appendix A, the temperature coefficient is positive.
The behavior of the system against ambient humidity variations was assessed using a test chamber where humidity changed from 20% to 70%. These measurements results are reported in Figure 14 for different values of ambient temperature, namely 20 • C, 30 • C, and 40 • C. By inspection of Figure 14, it is apparent that humidity variations produce a capacitance variation in the order of tens of aF. Moreover, they also confirm the temperature results of Figure 13.  Finally, Table 4 reports a comparison with other capacitive transducers in the literature. Among the compared solutions, the proposed sensor and [36] are the only ones providing a digital output word. Note, however, that area occupation of [36] does not include the area of the off-chip sensing MEMS capacitors. The solution proposed in [4], which targets the same application, shows a much lower resolution (0.065 aF), but at the expenses of a higher power consumption. The sensor introduced in [23] is designed for PM detection as well and shows a similar resolution, but exhibits a much higher area occupation. We can therefore conclude that the proposed sensor well compares with the state of the art, showing a good compromise between supply voltage, power consumption, area occupation, and resolution, while providing a digital output.

Conclusions
In this paper, a simple and mostly digital electronic front end for capacitive sensors is introduced. The system is designed for the detection of airborne particle matter using interdigitated planar capacitors implemented on the top metal of the die. Preliminary static experimental measurements show that the proposed system can detect talcum particles with a diameter in the order of 7 mm. The proposed circuit is just a part of the overall detecting system in which several capacitive electrodes are exploited in the detecting channel in order to enable in-flow detection. This system is currently under development.  Data Availability Statement: Data sharing is not applicable to this article.

Conflicts of Interest:
The authors declare no conflict of interest.

Appendix A
A first-order approximated model that considers temperature variations for the sensing and reference oscillation frequency expressed by (1) and (2) is given by where α is the temperature coefficient of the average current (Coefficient α takes into account the temperature dependence of the current due to the mobility and the threshold voltage), equal from simulations to −0.4 µA/ • C for both I avg,s and I avg,ref , T 0 is the room temperature and I(T 0 ) is the room temperature current. Equations (A1) and (A2) are written in the more general case in which the load capacitance and the supply voltage is different for the sensing and reference ROs. It should be noted that V DD,s and V DD,ref can be exploited as an additional knob to reduce the output offset frequency due to process and mismatch variations. By deriving Equation (A2), with respect to the temperature and neglecting the temperature coefficient of V DD,ref , the frequency temperature coefficient is obtained as which yields β = 117 kHz/ • C, that is about 7% lower than the simulated value reported in Figure 6 (126 kHz/ • C).
The temperature coefficient of the frequency difference can be obtained by substituting Equations (A1) and (A2) in Equation (2) and evaluating the first derivative respect to temperature, yielding Assuming V DD,s = V DD,ref = V DD and neglecting the second order term we get The numerical value predicted by Equation (A5), equal to 92.5 Hz/ • C, which is 14% lower than the simulated value in Figure 6 (108 Hz/ • C).