On Systematic Design of Fractional-Order Element Series

In this paper a concept for the efficient design of a series of floating fractional-order elements (FOEs) is proposed. Using even single or a very limited number of so-called “seed” FOEs it is possible to obtain a wide set of new FOEs featuring fractional order α being in the range [−n,n], where n is an arbitrary integer number, and hence enables to overcome the lack of commercial unavailability of FOEs. The systematic design stems from the utilization of a general immittance converter (GIC), whereas the concept is further developed by proposing a general circuit structure of the GIC that employs operational transconductance amplifiers (OTAs) as active elements. To show the efficiency of the presented approach, the use of only up to two “seed” FOEs with a properly selected fractional order αseed as passive elements results in the design of a series of 51 FOEs with different α being in the range [−2,2] that may find their utilization in sensor applications and the design of analog signal processing blocks. Comprehensive analysis of the proposed GIC is given, whereas the effect of parasitic properties of the assumed active elements is determined and the optimization process described to improve the overall performance of the GIC. Using OTAs designed in 0.18 μm TSMC CMOS technology, Cadence Virtuoso post-layout simulation results of the GIC are presented that prove its operability, performance optimization, and robustness of the proposed design concept.

Dealing mainly in the areas of signal processing, modeling and control, and electrical engineering, the implementation of required fractional-order function block relies on the presence of elements with fractional-order immittance, i.e., fractional-order elements (FOEs) or simply fractors. To design a FOE with required fractional order α (generally α ∈ IR), one of the direct implementations as recently summarized in [31] may be used, however all these techniques are still at the level of laboratory experiments. Hence, they do not provide readily available FOEs as discrete elements and mainly are suitable for capacitive FOE design only, i.e., 0 < α < 1. Additionally, the implementations as described in [31] enable one to obtain FOEs that are operable in a limited frequency band and with a narrow range of available α. To overcome the current obstacles in the unavailability of FOEs, they are commonly approximated by an RC network for the purpose of performance analysis and design verification by means of simulations or experimental measurements [32]. To approximate a FOE using an RC network, different approaches are described in the open literature, see e.g., [33][34][35]. However, for each different FOE, the RC network must be redesigned. This further limits the interest of the broader research community in fractionalorder circuits and systems, as individual research groups use their "tuned" FOE that is mainly specified with its fix fractional order α.
To obtain FOEs featuring new values of fractional order α without re-designing the "tuned" FOE, the generalized immittance converter (GIC) may be efficiently utilized. Originally, the GIC was and still is used to emulate a classic inductor (and to obtain so called synthetic inductor) using resistors, capacitors, and selected types of active elements, e.g., operational amplifiers [36], current conveyors [37], current feedback operational amplifiers [38], etc. The utilization of GIC in designing factional-order elements was also discussed e.g., in [39][40][41][42][43], where Antoniou's GIC employing operational amplifiers is used. The approach presented in [39] enables one to design new FOE with a fractional order between −2 and 2, but always requires a unique fractional-order element with specific α (i.e., 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8). A comprehensive analysis of opamp-based Antoniou's GIC, however limited to fractional-order inductor synthesis only, is provided in [40], similarly as in [41,42] the fractional-order inductor design and its utilization in the frequency filter design is discussed. First in [43], a more general approach to design FOEs is discussed, where both inductive and capacitive FOEs are used to design a set of new FOEs with a fractional order between −4 and 4. Note that as the Antoniou's GIC is always used, the newly obtained FOEs are always grounded.
In this paper, we elaborate the efficient utilization of so called "seed" fractionalorder elements featuring fractional order α seed that are employed in a general immittance converter to design a series of fractional-order elements. We partially presented this concept in [44], where the design of a series of grounded FOEs with fractional order [−2, 2] was presented. Here, we further develop the theory and the design approach to obtain arbitrary and floating FOEs. The structure of the paper is as follows. In Section 2, the theory on fractional-order elements is shortly described. In Section 3, we present the concept of designing a FOE with fractional order α being from the arbitrary range [−n, n], where n is a positive integer number. Using operational transconductance amplifiers (OTAs) as active elements, we also propose possible implementation of the general immittance converter and use it to design a wide series of floating FOEs. In Section 4, the behavior of the proposed GIC is further analyzed. Taking into account the non-ideal behavior of the active elements, the design rules are discussed to optimize the overall performance of the GIC. Section 5 provides post-layout simulations of new FOEs obtained by employing the proposed GIC, whereas the optimization recommendations are also advantageously utilized to broaden the operational frequency band and increase dynamic. To show a practical utilization of the GIC and the design of fractional band-pass filter is also discussed as an example. Finally, Section 6 concludes this paper.

Theory on Fractional-Order Elements
Fractional-order elements are understood to be the simplest electrical elements whose impedance function follows fractional order differential equations and are used as basic building blocks for other fractional-order circuits and systems design. In the open literature, FOEs are also refereed to as constant-phase elements (CPEs) [45], elements with fractional impedance (EFIs) [46], or generally fractors [39] whose impedance in s-domain is defined as: where F, called as fractance, is the coefficient of the fractor, and α is generally a real number, called the fractional-order. In frequency domain, the magnitude of a fractor is |Z F | = 1/(ω α F) Ω. For positive/negative values of α the magnitude |Z F | is monotonically decreasing/increasing with frequency by 20 · α dBΩ/dec, whereas the phase angle remains always constant ϕ = −α · 90 deg.
If 0 < α < 1, the phase angle of the fractor is negative and the fractor is called the fractional-order capacitor (also fractional capacitor, capacitive FOE, or capacitive fractor): where C α = F is referred to as pseudo-capacitance or fractional capacitance. For −1 < α < 0, the phase angle of the fractor is positive and the fractor is called the fractional-order inductor, also referred to as the fractional inductor, inductive FOE, or inductive fractor. The fractional order of the inductive fractor is commonly labeled as β, whereas it may be evident that β = −α: where L β = 1/F is the pseudo-inductance or fractional inductance. As presented in [33,47], the fractional capacitor and its pseudo-capacitance C α may be represented as the equivalent capacitor with capacitance C that features the same impedance at frequency ω 0 : and similarly for the fractional inductor with its pseudo-inductance L β , an equivalent inductor with its inductance L featuring the same impedance at frequency ω 0 can be specified: It may be noted that for α = 0, 1, or − 1, the fractor defined by (1) becomes resistor, capacitor, or inductor, respectively. For |α| > 1, the fractor (1) can be used to describe higher-order immittances, e.g., the frequency dependent negative resistor (FDNR), finding their application in a higher-order frequency filter design [48,49].

General Immittance Converter in FOEs' Series Design
As already discussed in Section 1, it is not necessary to limit the utilization of GIC to design synthetic inductors. The general immittance converter may also be efficiently used in fractional-order element design as shown e.g., in [39], where the known operational amplifier-based Antoniou's GIC was employed. Here we further extend the idea of transforming FOEs and provide a concept of efficient design of a series in fractional order α of fractional-order elements by using even single or very a limited number of "seed" FOEs.

General Immittance Converter Behavior Definition
Assume a general function block as shown in Figure 1 that is represented by general active/passive network to which general admittances Y i (i = 1, ..., n; n being even number) are connected. The general active/passive network may represent arbitrary interconnection of an arbitrary type of active and passive elements and is determined by its parameter g, a transcondustance specific for this active/passive network. Let the input admittance (Y IN ) of such a general function block be defined as: The general admittances Y i (i = 1, ..., n) may be represented by any type of passive element, such as conductor (G), inductor (L), capacitor (C), or fractional-order element (FOE), whereas adopting the nomenclature as defined in Section 2, for each passive element, i.e., conductor, inductor, capacitor, and FOE it is possible to claim that its fractional order α i equals to 0, −1, 1, and α FOE (−1 < α FOE < 0 or 0 < α FOE < 1), respectively. Under these assumptions, for the fractional order α defining the phase angle of the input admittance (6) can be written: and the feasible range of fractional order α is defined as [−n, n]. To better demonstrate the advantageous features of the proposed concept of designing a series in fractional order α of fractional-order elements, let n = 4. Then (6) and (7) simplify to: and respectively. As in practical analog circuit design, classic inductors, and/or inductive fractors are not commonly used, in the further text it is assumed that the general admittances Y i (i = 1, ..., 4) may be replaced only by conductors (α i = 0), capacitors (α i = 1), and/or capacitive FOEs (α i = α FOE , 0 < α FOE < 1). Now replacing the general admittance Y i (i = 1, ..., 4) by one of the three assumed types of passive elements, the following set of passive (synthetic) elements observed at the input of the immittance converter and specific with their fractional order α can be described:
Note that the feasible range of fractional order α is now [−2, 2] only, which is caused by the fact that neither classic nor fractional inductors are assumed to replace one or more general admittances Y i (i = 1, ..., 4).
The frequency dependent negative resistor-type I (FDNR-I) is also referred to as the D element (or double capacitor) and features purely real negative resistance that decreases in magnitude with increasing frequency [36], whereas FDNR-II also exhibits purely real negative resistance, however, its magnitude increases for increasing frequency. Additionally, comparing with [39], the inductive FOE, fractional FDNR-II, fractional FDNR-I, and capacitive FOE, may be referred to as Type-I fractor, Type-II fractor, Type-III fractor, and Type-IV fractor, respectively.
Using a general immittance converter allows one to obtain a wide series of new FOEs using a very limited set of "seed" FOEs and their fractional order α seed . As an example, assume a "seed" FOE with its fractional order α seed = 0.2. Using always at most two identical "seed" FOEs and two capacitors together with conductors to replace external admittances Y i (i = 1, ..., 4) in (8), then according to (9) 19 unique values of fractional order α from the range [−2, 2] are obtained. The specific combinations of external passive elements, i.e., of the conductors, capacitors, and "seed" FOEs, are listed in Table A1.
To better comprehend the advantage in utilizing "seed" FOEs, even 51 different values of fractional order α, still from the range [−2, 2], can be obtained by assuming α seed1 = 0.25 and α seed2 = 0.0625. As a result, for each α, the input admittance Y IN (8) features a phase angle from the range [−180, 180] deg as illustrated in Figure 2. The specific combinations of external admittances types defined by their α i is summarized in Table A2. Hence, it may be obvious that using a very limited set of "seed" FOEs, a broad series of new fractional order elements primarily with different fractional order α may be obtained. Furthermore, by adjusting the values of external capacitors (C), conductors (G), and most preferably also the transcondustance g of the active/passive network it is possible to obtain a generally arbitrary value of the fractance being observed at the input of the GIC.

Proposed Implementation of General Immittance Converter
To prove our theoretical concept in designing a series of floating fractional-order elements, we also propose possible circuit implementation, whose performance is analyzed in detail in Section 4. To implement the required GIC, the well-known OTAs are used as active elements.
The OTA, whose circuit symbol is shown in Figure 3, specified with its transcondutance g m is a source of current i OUT controlled by a difference of input voltages v + and v − [50]: whereas g m may commonly be adjusted by an external dc voltage V SET or current I SET .
g m In Figure 4, the novel configuration of a general immittance converter is shown. Taking into account the basic terminal relationship of OTA (10) and performing routine algebraic analysis, the input admittance is determined as: Comparing (11) with (6), it may be observed that the proposed circuit from Figure 4 fully follows the behavior of a general immittance converter as defined in Section 3.1, whereas for the transconductance g it holds: The following beneficial features of the proposed general immittance converter are identified: • Floating fractional-order elements are designed, • Only grounded external admittances are employed, • Electronic tunability of |Y IN | is possible by proper adjustment of the transcondutances g m of the active elements, • There is no restriction concerning matching between passive (external) or active elements.

Performance Analysis of the Proposed Immittance Converter
In theory, using the proposed OTA-based general immittance converter from Figure 4, the feasible range of the fractional order α is [−n, n], whereas n is generally an arbitrary even integer number.
For a more practical design of a series of fractional-order elements, let n = 4. The general immittance converter from Figure 4 simplifies to a circuit as shown in Figure 5, whose input admittance according to (11) is specified as: For the same reasons as already discussed in Section 3.1, assuming the external admittanaces to be suitably replaced by conductors, capacitors, and capacitive-type "seed" FOEs, the immittance converter from Figure 5 is capable of designing a series of fractionalorder elements with the fractional order α in the range [−2, 2]. Once the inductors and fractional inductors are used to replace one or more external admittances, the fractional order range of α will be [−4, 4].

Properties of Used OTA
For the purpose of analysis of the real behavior of the proposed GIC from Figure 5, the OTA element designed in the 0.18 µm TSMC complementary metal-oxide semiconductor (CMOS) process as presented in [51] is used. As shown in Figure 6, the assumed OTA consists of two differential voltage summation blocks, whereas the inputs of the first one serve as differential voltage inputs of OTA and the inputs of the second summation block are used to apply the control voltage V SET . The outputs of the summation blocks are multiplied mutually and amplified with the constant k resulting in two output currents with the same magnitude but shifted in phase by 180 deg. Hence, the following relation is valid for the output currents of the OTA from Figure 6: where k = 2 · 10 −3 A/V 2 and defines the transmission of the block k in Figure 6.
In accordance with (10), the relation between g m and V SET is given by: The dependence of g m on V SET of the OTA from Figure 6 obtained by Cadence simulations is given in Figure 7 (solid red line). It may be observed that (15) is valid for V SET in the range 0 to 0.5 V and proves the possibility to electronically set g m between 0 and 1 mS, whereas the maximum absolute error is 0.02 mS (Figure 7; dashed blue line). Detailed analysis of the OTA and discussion of its parameters is given in [51]. Here we further aim to analyze the influence of real properties of OTAs on the overall performance of the proposed GIC. In an ideal case the internal impedance of OTA input and output terminals is infinity. Considering a real OTA, its properties are commonly modeled by resistances and capacitances connected between each of the terminals and ground. Considering these OTA parasitic properties the proposed GIC from Figure 5 can be redrawn as seen in Figure 8. Assuming that all OTAs in the circuit are the same, the parasitic conductors G P symbolize a parallel combination of the input and output internal resistances of OTA. Similarly, the parasitic capacitors C P represent a parallel combination of OTA input and output internal capacitances. Based on [51], their approximate values used in this analysis are G P ≈ 1/(346 kΩ) = 2.89 µS and C P ≈ 0.28 pF. Note that the parasitic elements in the node E express the properties of twice the number of OTAs, thus their conductance and capacitance are double compared to the other parasitic elements, i.e., 2G P and 2C P . As the overall input port of the GIC labeled as F is differential, the terminal parasitic elements G P and C P are connected in series here (through ground) and thus these parasitics are considered to be G P /2 and C P /2. If the GIC is connected as single-ended, i.e., one of its input terminals is grounded, the values of the parasitic elements of the input node should be considered to be G P and C P . Figure 8. Proposed general immittance converter with OTA parasitic properties.

Influence of OTA Parasitics and Optimization of GIC Performance
To solely evaluate the influence of OTA parasitic properties, as well as FOEs, resistors, and capacitors used to replace the admittances Y 1 , Y 2 , Y 3 , and Y 4 are assumed to be ideal. For clarity, the nodes and input port, where the modeled parasitics are present are labeled by circled letters A to F in Figure 8.

Nodes A, B, C, D
As already mentioned in Section 3.1, the external admittances Y 1 , Y 2 , Y 3 , and Y 4 connected to these nodes are expected to be replaced by conductors (i.e., resistors), classic capacitors, or capacitive FOEs. In case of conductors, the parallel parasitic conductance G P is added, but it is usually very small and can be neglected. The capacitance C P is also in parallel and considering operational conductance of the order of milisiemens (mS), the parasitic effect of C P becomes significant at a very high frequency (above approx. 500 MHz), and thus can also be neglected.
On the other hand, the replacement of external admittances by capacitors or capacitive FOEs is worth analyzing. At low frequencies these elements have a very low admittance magnitude and the parasitic conductance G P may prevail. In case of fractor with fractional order α and fractance F this happens below the frequency: as illustrated by asymptotic admittance magnitude plot in Figure 9. Note that (16) is also valid for a classic capacitor when considering α = 1 and a capacitance equal to F. It follows that for a higher value of F correct operating range is extended to lower frequencies. Once for a specific F sufficiently low ω GP is not provided, the parasitic conductance G P can be reduced, e.g., by connecting in parallel a negative conductance as described in Section 4.3 in detail. Using this approach, i.e., the negative conductance, the frequency ω GP can theoretically be shifted to very low values. However, the demands on the accuracy of the negative conductance increase. Reducing G P also decreases the lower bound of the obtainable admittance magnitudes of nodes A to D.

Node E
In case of ideal OTAs, the order of the admittance of the node E (Y E ) equals to α E = −(α 2 + α 4 ), and hence can range from 0 to −2. Thus the character of the admittance ranges from resistive through fractional inductive, inductive, fractional FDNR-II to FDNR-II. The resistive character will be not included in the analysis, as in this case the whole lower branch including OTA 2 , OTA 4 , and OTA 6 can be omitted and replaced by a resistor and a similar conclusion as described in Section 4.2.1 is reached. Considering all other possible characters of Y E , the OTA parasitic properties affect the circuit mainly at high frequencies, since the admittance magnitude being defined as: becomes comparable with or even lower than the admittance magnitude of the parasitics 2G P and/or ω2C P , which may prevail. The situation is illustrated by the admittance magnitude asymptotic plots in Figure 10.
ω The black lines are defined by the admittances of the parasitic elements and their breakpoint is at the frequency ω 2P : This frequency is approximately 1.6 MHz for the above mentioned parasitics of the OTA. The red lines (Y E1 and Y E2 ) in Figure 10 show two cases of possible admittance magnitudes of the node E that are not affected by the parasitics 2G P and 2C P yet. When the red lines approach the black "boundary" line represented by the admittance of the parasitics, these parasitics start to take effect. The cut-off frequency of the correct operation for the first case (Y E1 ) is: Considering the second case (Y E2 ), the cut-off frequency is: Both these frequencies can be increased by increasing Y E , which can be done by increasing the product g m2 g m4 g m6 as seen in (17). The decrease of F 2 F 4 (F 2 and/or F 4 ) is also possible, however this may increase the lower cut-off frequency in the nodes B and/or D, see Section 4. 2.1 and (16). The orders α 2 and α 4 are fixed to obtain the required order of the GIC input admittance. The cut-off frequency ω 2GP can also be increased by decreasing 2G P using the negative conductance compensation (see Section 4.3) until ω 2GP = ω 2P . Decreasing further the parasitic conductance, the relation (20) starts to hold for the cut-off frequency. Note that if the compensation circuit described in Section 4.3 with the same OTA is used to reduce 2G P , in (18) and (20) it is necessary to assume 3C P instead of 2C P as the compensation circuit has its own parasitic capacitance C P .
Under certain conditions a sharp peak in the node E admittance magnitude characteristic can occur at the cut-off frequency. This happens when the cross product of the phasors of ideal Y E , jω2C P , and 2G P approaches zero as illustrated in Figure 11. The behavior of the GIC can be unstable in this case and it is necessary to ensure a suitable damping of the oscillations. Damping can be provided by modifying the value of 2G P by connecting an appropriate positive or negative conductance in parallel. However, in most cases the circuit is damped by its own parasitic properties and no modification is necessary. Excessive damping is not recommended as it can lead to an exceedingly soft transition of input admittance phase in a very broad band around the cut-off frequency. Figure 11. Phasor diagram resulting in zero admittance of node E.

Port F
The port F is the overall input node of the GIC and thus Y F = Y IN = s α F IN . This admittance is specified as the design criterion and thus cannot be modified during optimization. Due to the limited optimization possibilities (in fact involving only changes in parasitics) it is suitable to evaluate and optimize the GIC performance in this node first. The optimization of other nodes beyond the performance of this node brings no improvement.
The fractional order α of Y F is in case of ideal OTAs given by (9) and ranges from −2 to 2. If α is positive, the admittance at port F is capacitive and at high frequencies it reaches high values in magnitude compared to the admittance of parasitics G P /2 and ωC P /2 present at the port. Thus the parasitics do not take effect in the port F at high frequencies and the upper frequency of the GIC operation is determined primarily by the properties of node E as described in Section 4.2.2. On the other hand, at low frequencies Y F can reach a low magnitude comparable with the parasitic conductance G P /2 present at port F. This is similar to the situation described in Section 4.2.1 for nodes A, B, C, and D. Since the admittance Y F cannot be changed as mentioned above, the only way to broaden the operation band to lower frequencies is to reduce the parasitic conductance at port F, e.g., using the compensation technique as proposed in Section 4.3. Additionally, the cut-off frequencies of the nodes A, B, C, and D should be determined and if necessary adjusted in accordance with the cut-off frequency of port F.
If α is negative, the admittance at port F is inductive and at high frequencies it can reach a low magnitude that is comparable with the admittance of parasitics G P /2 and ωC P /2. The analysis is then similar to node E, see Section 4.2.2, with the difference that in this case the magnitude of Y F cannot be modified. Hence, the optimization can be done only by reducing G P /2 such that it is lower than both |Y IN | and ωC P /2 at frequency, where these admittances are equal, that is: and it is the maximum operation frequency of the port F and cannot be increased. Note that when the differential compensation circuit described in Section 4.3 with the same OTA is used to reduce parasitic conductance at port F, in (21) it is necessary to assume C P instead of C P /2, as again the compensation circuit has its own parasitic capacitance C P /2. The subsequent step is verification or prospective optimization of the cut-off frequency of the node E, whereas its value specified by (19) or (20) is to be at least as high as ω CP/2 . Also note that when the GIC is connected as single-ended, the parasitics in port F should be considered with values G P and C P instead of G P /2 and C P /2. The single-ended variant of the compensation circuit with negative conductance can be utilized as presented in Section 4.3. The effectiveness of the described compensation possibilities in individual nodes is demonstrated in Section 5.3, where the overall performance of the proposed GIC is discussed.

OTA-Based Circuit with Negative Conductance
When the parasitic conductance present in a node of the proposed GIC is to be decreased within performance optimization as described in Section 4.2, simple compensation circuits as shown in Figure 12 can be employed. The circuit from Figure 12a is suitable for compensation of parasitic conductance at nodes A to E, since compensation conductance in the COMP terminal relative to ground is: whereas the differential variant in Figure 12b can be connected to the port F and its input conductance is: We consider that the utilized OTA C has the same parasitic terminal properties as the OTAs used in the proposed GIC. The conductance G COMP can be set to an appropriate negative value by the setting of g mC . It should be again noted that when connecting the circuits from Figure 12 to a node or port, the total parasitic capacitance in the node or port increases by the parasitic capacitance of the compensation circuit which is C P or C P /2 in the case of Figure 12a,b, respectively. Thus it is necessary to take this value into account in the relations containing the parasitic capacitance of the node or port being optimized.

Simulation Results
To prove the functionality of the proposed GIC and mainly to show its advantageous feature in designing a wide set of fractional-order elements using a very limited count of "seed" FOEs, the performance of the GIC was further verified by post-layout simulations in Cadence Virtuoso 6.1.6. First, two "seed" FOEs are designed and further utilized in the proposed GIC, whereas following the recommendations from Section 4.2, the optimization steps are also verified to improve the overall performance of the GIC. Additionally, as an example, a band-pass filter is designed using the fractional-order FDNR-I with fractional order α = 1.75.

Design of "Seed" FOEs
To obtain the set of new FOEs and their fractional-order α as listed in Table A2, the "seed" FOEs with α seed1 = 0.25 and α seed2 = 0.0625 are required. Due to the commercial unavailability of such FOEs, these "seed" FOEs were approximated by 7th-order Valsa topology as shown in Figure 13. The resistances and capacitances were determined using the approach described in [34] and are summarized in Table 1. Computed resistor and capacitor values are the E48 and E12 series EIA standard compliant RC values, respectively. The fractances of the two "seed" FOEs are F seed1 = 112.3 µFs −0.75 and F seed2 = 578.9 µFs −0.9375 , respectively, and their admittance at central frequency of approximation 1 kHz is 1 mS. Figure 13. 7th-order Valsa RC network to approximate "seed" FOE. In Figure 14 the magnitude and phase admittance frequency characteristics of the approximated "seed" FOEs are shown (solid lines) and compared with ideal "seed" FOEs (dotted lines). The absolute errors in magnitude and phase of the approximated "seed" FOEs are also depicted (dashed lines), whereas the correct operation may be observed in 4 decades, i.e., from 10 Hz to 100 kHz.
Here we should note again that the general admittances Y 1 , Y 2 , Y 3 , and Y 4 are external and to be replaced by discrete resistors, capacitors, and/or "seed" FOEs. Hence, the accuracy of the fractional order α of the FOE being observed at the input of the GIC is determined only by the accuracy of the "seed" FOEs since the external resistors and capacitors are always characteristic with 0 deg and −90 deg phase shift, respectively. If higher accuracy of the fractional order α is required, the accuracy of α seed must also be increased by commonly increasing the order of the RC network used to approximate the "seed" FOE [34] or using a different RC network [33].

Simulation of the GIC
To implement the proposed GIC, the OTA cell designed in the 0.18 µm TSMC CMOS process as presented in Section 4.1 and described in detail in [51] was used. Since for our purpose we use the OTA cell as the final block, here we do not further focus in detail on its layout design, as our prime aim is the proposal of the concept designing a series of FOEs using "seed" FOEs. Those interested in issues regarding the chip layout design may refer to [52][53][54].
The overall circuit layout of the proposed GIC is shown in Figure 15. In Figure 15, the cells OTA i (i = 1, 2...7) correspond to prime active elements of the GIC circuit as shown in Figure 5. The cells OTA C−j (j = A, B...F) represent the single-ended or differential compensation circuit from Figure 12 to reduce the parasitic conductance G P present in the nodes A to E, or port F as labeled in Figure 8. Additionally, the block I BIAS is a set of current sources to bias the OTA cells. The labels Y 1 , Y 2 , Y 3 , Y 4 , and Y IN+ , Y IN− represent the pins, to which the external discrete elements, i.e., resistors, conductors, and/or "seed" FOEs are to be connected, or the input terminal of the GIC, respectively. Within the simulations, next to the "seed" FOEs as described in Section 5.1, the external general admittances Y 1 , Y 2 , Y 3 , and Y 4 of the GIC are always replaced by 1 mS admittances or 159.2 nF capacitors (as at the central frequency 1 kHz their admittance is 1 mS). The transconductances g m of all prime OTAs are 1 mS (i.e., V SET = 0.5 V). The resulting magnitude and phase characteristics of the input admittance of the immittance converter from Figure 5 are presented in Figure 16. The black dotted lines represent the results with ideal OTAs and approximated "seed" FOEs employed. To maintain the clarity of the simulation results being displayed in Figure 16, only the α values from the range [−2, 2] with the step 0.25 were selected. Based on the values of external admittances and setting of OTAs, the input admittance magnitude of the GIC is always |Y IN | = 1 mS at 1 kHz.
In Figure 16 it is apparent that the input admittance magnitude and phase characteristics are affected by the OTAs parasitic properties. Most distorted are the characteristics for |α| > 1, both at low and high frequencies, whereas in the magnitude characteristics ( Figure 16a) peaking is evident in several cases. This peaking is caused by the resonance of the node E or port F admittance (which has a character of fractional or integer-order FDNR-I or FDNR-II) with OTA parasitic conductance. Fortunately, damping of the oscillations is always ensured by the OTA parasitic capacitance and thus the circuit is stable. However, the overall bandwidth of correct operation for the highest values of |α| reduces down to two decades only, which is two decades lower than the bandwidth of the approximated "seed" FOEs. To broaden the bandwidth of the GIC, optimization is required by following the steps as described in Section 4, which are validated in Section 5.3.

Optimization of GIC Performance
The influence of the OTA parasitics on the significant reduction of the operational frequency band of the newly obtained FOEs can be observed in Figure 16, mainly for |α| > 1. To reach an operational bandwidth of FOEs at the input of GIC to be at least the same as it is of the "seed" FOEs (i.e., 10 Hz-100 kHz), optimization is necessary and is demonstrated on two following examples. In this case, the fractional FDNR-I is obtained at the input of the GIC, i.e., port F, whose fractance is F IN = 22.55 nFs 0.75 . Decreasing frequency the admittance magnitude also decreases until the parasitic conductance G P /2 starts to prevail. This happens at a lower cut-off frequency at approximately 23.8 Hz (Figure 16a) generally determined by (16), where G P was substituted by G P /2 (note that (16) is originally valid for nodes A, B, C, D where parasitic conductance G P is present).
Within optimization, using the circuit from Figure 12b to compensate the parasitic conductance at port F, the lower cut-off frequency is decreased down to 1 Hz to maintain a sufficient margin to frequency 10 Hz due to soft admittance phase transition (Figure 16b). To reach this new lower cut-off frequency, the input conductance G COMP was set to −1.439 µS, whereas according to (23) compensation transconductance g mC equals to 2.885 µS.
The upper cut-off frequency is determined by the parasitics of the node E as described in Section 4.2.2. To increase this upper cut-off frequency it is necessary either to increase the product g m2 g m4 g m6 or to decrease F 2 F 4 (in this case capacitances C 2 and C 4 as α 2 = α 4 = 1). Since the transconductances g m of all OTAs are already set to 1 mS (maximum according to Figure 7), the product g m2 g m4 g m6 cannot be further increased. Hence, having selected the upper cut-off frequency to be 100 kHz, using (19) new capacitances C 2 and C 4 (considering them equal) were determined to be 20.9 nF. Note that here the margin from the required 100 kHz was not considered, as the damping in the node E is low and the admittance phase shows the transition in a narrow band. Moreover, the excessive increase of the upper cut-off frequency in node E would lead to lower capacitances C 2 and C 4 and undesirable deterioration of the cut-off frequency in nodes B and D.
Within the optimization of the upper cut-off frequency, the ratio g m2 g m4 g m6 /(F 2 F 4 ) was increased. Hence, to keep the original value of the input fractance F IN unaffected, according to general formula (13), the ratio G 1 F seed1 /(g m1 g m3 g m5 g m7 ) must decrease. As again the transconductances g m of all OTAs are already set to their maximum values (i.e., 1 mS) and the "seed" FOE is not expected to be modified, the only possibility is to decrease G 1 to 17.3 µS.

Optimization Example for α = −1.75
For this case, the fractional FDNR-II with fractance 4434 Fs −2.75 is obtained at the input of the GIC. The admittance magnitude decreases with increasing frequency, where the parasitics at port F define the upper cut-off frequency of approximately 42 kHz (Figure 16a) generally determined by (16), where again G P was substituted by G P /2. The only solution to increase the upper cut-off frequency is to reduce the parasitic conductance of the port F by using the compensation circuit from Figure 12b. In this case it is possible to decrease the port F parasitic conductance almost to zero, thus the transconductance of the compensation circuit is set slightly lower than G P , i.e., g mC = 2.888 µS.
To reduce the lower cut-off frequency, it is necessary to increase capacitances C 1 and C 3 in the nodes A and C according to (16). The optimized lower cut-off frequency is set to 1 Hz to have again sufficient margin to 10 Hz due to soft phase transition. Hence, the new value of capacitances C 1 and C 3 is 460 nF.
Within the optimization of the lower cut-off frequency the product C 1 C 3 was increased. Hence, the ratio g m2 g m4 g m6 /(G 2 F seed1 g m1 g m3 g m5 g m7 ) must decrease according to general formula (13) to keep the original value of the input fractance F IN unchanged. For this purpose, the transconductances g m2 , g m4 , and g m6 were set to 0.493 mS, whereas g m1 , g m3 , g m5 , g m7 , G 2 , and mainly F seed1 are kept the same. As transconductances g m2 , g m4 , and g m6 were changed, it is necessary to check the upper cut-off frequency of the node E if it is large enough. According to (20) the value of f 2CP is 4.2 MHz, which is much more than the required upper cut-off frequency of 100 kHz. Hence no further optimization is needed.
For the both optimized examples as described in Sections 5.3.1 and 5.3.2, the resulting admittance magnitude and phase frequency characteristics are shown in Figure 17 along with the characteristics of the non-optimized GIC taken from Figure 16. It is evident that the optimized circuit provides a higher frequency bandwidth of the admittance characteristics covering the required 4 decades. The fractional FDNR-I (blue lines) reaches an upper cut-off frequency almost equal 100 kHz as considered during the optimization. The lower cut-off frequency reached approximately 5 Hz, which is higher than the projected value of 1 Hz, however, here the GIC function is affected by parasitics of multiple nodes and also the "seed" FOE shows a higher error (see Figure 14). The fractional FDNR-II (red lines) has also been optimized successfully. Its upper cut-off frequency is around 100 kHz and lower cut-off frequency is 0.9 Hz. Additionally, as seen from Figure 17a, the dynamic range of the admittance magnitude has also increased thanks to the optimization.

Fractional Band-Pass Filter Design
To also show the practical utilization of the proposed GIC and the fractional-order element that are being obtained at its input, a fractional band-pass filter as presented in Figure 18 is designed, as an example. The transfer function of the filter from Figure 18 is determined as: where a = 1/(CR) and b = 1/(FR), whereas F is the fractance of fractional FDNR-I (FOFDNR-I) with its fractional order being in the range 1 < α < 2.
According to (24), the band-pass filter features stop-band attenuation of +20α dB/dec and −20 dB/dec for frequencies lower and higher than the pole frequency, respectively.
For Butterworth approximation of fractional-order band-pass filters, based on [55] the coefficients a and b are determined as: where ω 0 is the angular pole frequency of the filter. Assuming the FOFDNR-I with its fractance F = 22.55 nFs 0.75 and fractional order α = 1.75, as is obtained at the input of GIC and using (24)- (26), the values of resistor and capacitor of the filter from Figure 18 can be determined as R = 21.88 Ω and C = 742 nF for pole frequency f 0 = 10 kHz.   The magnitude and phase frequency responses of the band-pass filter reached by simulations are shown in Figure 19 and compared to ideal behavior. Within simulations, the FOFDNR-I was assumed to be implemented prior and after the GIC performance optimization as discussed in Section 5.3.1. From the simulation results it can be seen that the filter follows the ideal behavior very well, mainly for the optimized design of the required FOFDNR-I (solid lines). The proper behavior of the filter may be observed in four decades, which corresponds to optimized GIC performance and even the bandwidth of the initial "seed" FOEs. The most significant differences can be seen in the results of the non-optimized circuit above pole frequency, where a greater slope of attenuation was achieved. This is caused by parasitics in node E of the GIC used, which manifest themselves at a frequency of 10 kHz, as described before in Section 5.3.1.

Conclusions
In this paper we presented the concept of an efficient design of fractional-order element series in fractional order α using a very limited count of initial FOEs, here referred to as "seed" FOEs. The proposed concept is powerful and significantly helps to overcome the current obstacle of commercial unavailability of FOEs and was based on the utilization of general immittance converter, in addition a novel general OTA-based implementation was also proposed. To show the advantageous features of the proposed concept, as an example two "seed" FOEs with fractional orders 0.25 and 0.0625 were implemented to design a series of new 51 FOEs with unique fractional order in the range [−2, 2]. The "seed" FOEs were approximated using the Valsa RC network in four decades featuring a very low absolute error. Comprehensive analysis of the designed circuit was given to enable its performance optimization. Using OTAs designed in 0.18 µm TSMC CMOS technology, Cadence Virtuoso post-layout simulation results were presented which prove the operability of the proposed GIC, whereas the performance optimization was also shown on two examples to extend the operational frequency range. Finally, a fractional-order band-pass filter was also designed, which successfully utilizes the floating fractional FDNR-I with its fractional order α = 1.75.  Acknowledgments: The research results described in this paper are supported by the Czech Science Foundation, project No. 19-24585S. For the research, the infrastructure of the SIX Research Center was used.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations are used in this manuscript:  Table A1. Combinations of admittances Y i , their α i and the unique fractional order α of Z IN for α seed = 0.2.