Analytical Optimal Load Calculation of RF Energy Rectifiers Based on a Simplified Rectifying Model

Wireless power transfer (WPT) is an essential enabler for novel sensor networks such as the wireless powered communication network (WPCN). The efficiency of an energy rectifier is dependent on both input power and loading condition. In this work, to maximize the rectifier efficiency, we present a low-complexity numerical method based on an analytical rectifier model to calculate the optimal load for different rectifier topologies, including half-wave and voltage-multipliers, without needing time-consuming simulations. The method is based on a simplified analytical rectifier model based on the diode equivalent circuit including parasitic parameters. Furthermore, by using Lambert-W function and the perturbation method, closed-form solutions are given for low-input power cases. The method is validated by means of both simulations and measurements. Extensive transient simulation results using different diodes (Skyworks SMS7630 and Avago HSMS285x) and frequency bands (400 MHz, 900 MHz, and 2.4 GHz) are provided for validation of the method. A 400 MHz 1- and 2-stage voltage multiplier are designed and fabricated, and measurements are conducted. Different input signals are used when validating the proposed methods, including the single sinewave signal and the multisine signal. The proposed numerical method shows excellent accuracy with both signal types, as long as the output voltage ripple is sufficiently low.


Introduction
Wireless power transfer (WPT) is an emerging technology that removes the traditional charging cables. Due to its convenience, WPT can be found or foreseen in many applications such as electric vehicles, consumer electronics, and new communication networks [1,2]. Specifically, far-field WPT based on RF signals can deliver wireless power over a long distance up to kilometers, which enables new communication and sensing networks in the IoT domain such as wirelessly powered communication network (WPCN). These networks consist of low-power sensor nodes whose power is provided by either dedicated RF sources or ambient RF energy, which prolongs the sensors' lifetime and reduces the maintenance cost [3].
The receiving side of an RF WPT system is called an energy rectifier. The rectifier converts the RF signal into a DC voltage that either directly powers electronics or is stored in storage units such as batteries or super-capacitors. It often consists of an antenna that captures the wireless signal; a matching and rectifying network for RF-to-DC conversion; and a power management unit (PMU), which is the rectifier's load. The power conversion efficiency (PCE) of a rectifier has been shown to depend on both received RF power and its load; thus, the optimal load for a rectifier needs to be understood [4]. Additionally, novel excitation waveforms such as multisine waveform featuring high peak-to-averagepower ratio (PAPR) and multiple frequency components [5] have been proposed to boost the rectification efficiency. To analyze the optimal load with general excitation, transient simulations are often conducted [6], which are time-consuming and computationally intensive. Harmonic balance (HB) is another option, but its complexity poorly scales with the number of frequency components in the excitation waveform so that it soon becomes impractical [7].
Instead of numerical solvers, many efforts were put into the analytical modeling of rectification. The works [8][9][10] used the time-domain method to analytically analyze the shunt-diode rectifier. Afterwards, ref [11] the model was extended with class-f harmonic termination. In [12][13][14], Bessel functions are used to separate DC component and the first harmonic of the diode voltage and the optimal load using the developed model is calculated. A limitation to the aforementioned works is that they all assume the applied excitation to be a sine wave. Works in [15,16] extensively analyzed the incurred losses in the complete rectification chain and pointed out the optimal load resistance for the overall efficiency in the low input power range is equal to the diode junction resistance and series resistance combined. The junction resistance, however, depends on the junction bias voltage, which in turn depends on the load; thus, additional steps are needed to calculate or measure this quantity.
There have also been works focusing on developing analytical rectification models for general multisine signals. In [17], a simplified analytical model was developed to mathematically prove the efficiency gain of the multisine excitation. Later, this model was used in [18,19] to optimize the transmission waveform with frequency-selective fading channels because of the tractability of this rectifier model and its ability to capture the non-linearity of the rectifier circuitry. For the same reason, this model was also used in system performance analysis and optimization of WPCNs and shows superior accuracy to the conventional linear rectifier model in [20][21][22][23]. Despite the successful applications of this model, the key assumptions in [17,18] when developing it are the ideal diode and the half-wave rectifier topology.
In our previous work [24], the model with diode parasitics in the simplest half-wave rectifier was discussed; then, the model was extended for the voltage-doubler. We also showed the low-complexity method to derive the optimal load. The method works with general multisine input signals, provided that the output voltage ripple is small enough. In the current work, we further extend the model to generic N-stage voltage-multipliers. More extensive transient simulations are conducted to validate the result. Two different Schottky diodes are considered in the simulation, and three different frequency bands: 400 MHz, 900 MHz, and 2.4 GHz, which are simulated as well to investigate the impact of frequency. Finally, rectifier prototypes are designed and fabricated and a measurement campaign is conducted to provide experimental data to further support the results.
The paper is organized as follows: Section 2 introduces the simplified analytical rectifier model for both half-wave and N-stage voltage multiplier with a realistic diode equivalent model; Section 3 describes the calculation of the optimal load and its closedform asymptotic solutions; and numerical and experimental validations are discussed in Section 4, including the simulation setup, PCB design considerations, measurement setup, results, interpretation, and discussion. Finally, Section 5 summarizes the paper and discusses the implications of applications.

Analytical Rectification Model
In this section, we will summarize the rectification model for the half-wave topology and analyze the effects of diode parasitic parameters. Then, we will extend the model to a generic N-stage voltage multiplier.

Half-Wave Rectification Model
The schematic of a half-wave rectifier is shown in Figure 1a. The diode is modeled by the equivalent circuit shown in Figure 2, where there is the ideal diode junction D j , junction capacitance C j , series resistance R S , parallel capacitance C P , and series inductance L S . Assume a multisine input voltage to the rectifier circuit being: where N f is the number of sub-carriers or tones, V A is the amplitude of each tone, f n and φ n are the frequency and phase of the n-th tone, respectively. The tones are assumed to follow a uniform frequency grid, such that f n = f 0 + n∆ f , with ∆ f being the frequency separation. As a result, v in (t) is a periodic signal with period T = 1/∆ f when N f > 1. The CW signal can be viewed as a special case with N f = 1 and a period of T = 1/ f 0 .  According to the Kirchhoff's voltage and current law, and Figures 1a and 2, we have the following relationships: where i s is the diode saturation current, and α = 1/(nv t ) with n and v t being ideality factor and thermal voltage, respectively. Equation (3) is the Shockley equation of the diode junction. Because we are interested in the DC output voltage rather than its transient, we average both sides of Equation (2) over a signal period after the system reaches steady state: where i dc is the DC component of output current i out , E {.} denotes time averaging, and the juntion current i D j (t) is substituted by Equation (3). Note that during the time averaging, the current terms related to capacitors vanishe. This is because in the steady state, the amount of electronic charges on a capacitor remains the same in the beginning and the end of a period. As a result, the average current has to be zero. Next, we assume the output capacitor C in Figure 1a is sufficiently large, such that the output voltage ripple is negligible. Hence, the output voltage over the load is effectively a DC signal, such that we can write i out (t) ≈ i dc and v out (t) ≈ i dc R L . This is a reasonable assumption since a steady state voltage source is essential for the proper functionality of the circuitry behind the rectifier. Following this assumption, we can further approximate the current through diode i D (t) = C dv out (t) dt + i out (t) ≈ i dc . Substituting these approximations in Equation (4) The series inductance term is dropped because L S is typically very small so naturally Similarly, the parallel capacitance term in Equation (5) is also dropped due to small C P value. As a result, Equation (5) can be rewritten by i R S (t) ≈ i dc , and Equation (7) Substitute it back to Equation (6): Note now that i dc is still on both sides of the equation. Move i s to the left hand side and multiply αR h e α(i dc +i s )R h to both sides: where R h = R S + R L . Equation (10) can be solved for i dc by using the principle branch of the Lambert W-function [26]: where z dc = i s T T 0 e αv in (t) dt − i s , which is a monotonic function with the amplitude of input voltage, and W(x) is the Lambert W-function whose value is the solution of w to the equation we w = x. The Lambert W-function does not have an explicit formula but can be evaluated by simple numerical methods described in [26].

N-Stage Voltage-Multiplier Rectification Model
In this section, we will generalize the analytical half-wave rectification model developed in the previous section to N-stage voltage-multiplier. Figure 1b shows the schematic of a N-stage voltage-multiplier. A voltage-multiplier is often used to boost the output DC voltage by cascading voltage-doublers. The capacitors C n with even n are used to provide DC offset to each stage so the output voltage is stepped up gradually. Assume all diodes used in Figure 1b are the same. According to the Kirchhoff's current law, for the upper diode of the last stage D 2N : where C P(2N) and D j(2N) denote the parallel capacitance and junction of the 2N-th diode. By time-averaging the above equation in the steady state like we did with Equation (2), we get: According to the Kirchhoff's voltage law for the diode D 2N , the junction voltage is: where L S(2N) and R S(2N) are series inductance and series resistance of the 2N-th diode. The same treatment with the series inductance and resistance can be done as when analyzing the half-wave rectifier, to approximate v L S(2N) ≈ 0 and v R S(2N) ≈ i dc R S . To ensure a small output ripple, all capacitors in a voltage-multiplier need to be large enough so the time constant is larger than the signal period. This means the capacitors can be considered short-circuits at high frequency so that their voltage drop has only DC component [27]. At DC, the capacitors are open circuit and the input is shorted because the input voltage does not have DC component. As a result, the voltage drop across C 2N is: which equals to the voltage drop across the first 2N − 1 cascaded diodes. Using it in Equations (13) and (14), we get: Again, solve it for i dc using the principle branch of the Lambert W-function: where R = R S + R L 2N and N is the number of stages of a voltage-multiplier. Given the similarity between Equation (11) for half-wave and Equation (17) for voltage-multiplier, the half-wave model can be viewed as a special case of the multiplier model with number of stages N = 0.5.

Problem Formulation
We have so far developed the output DC current in the last chapter. By definition, the output DC power P dc is: The optimal load that maximizes P dc can be found by numerically evaluating Equation (18) based on Equation (17) with a scanned R L . This solution is called numerical solution of the analytical model.
To find the closed-form solution to the optimal load, the first derivative of P dc needs to be formulated. We first write the i dc 's first derivative with respect to the load using (17): where E = αR(i s + z dc )e αi s R . To simplify the notation, we omit the dependency of both i dc and P dc on v in and R L in equations from here on. The derivative of P dc with respect to the load resistance: Use Equations (17) and (19) in (20) we further have: Since i dc is by definition a non-negative number, solving for I 0 = 0 is equivalent to solving ∂P dc ∂R L = 0. However, finding the closed-form solution can be a challenge due to the lack of explicit formula of the W-function.

Closed-Form Approximations for Low Input Power
The W-function can be approximated in closed-form under some assumptions. By definition, the value of the W-function in Equation (21) is the solution of the equation: An easy solution would be obtained if the second term on the right hand side was absent, which is W(E) = αi s R. This situation is similar to solving a nonlinear ordinary differential equation (ODE). When the ODE is constructed in a way that there is a simple part added by a complex nonlinear term, often the perturbation method can be applied if the nonlinear term is small [28]. Here, we apply the perturbation method to solve Equation (22) under the condition that z dc is small compared with i s . Because z dc is a monotonic function of input voltage amplitude, the condition is equivalent to a small input power.
The exact solution W(E) is obviously a function of z dc ; thus, a power series about z dc exists that approximates W(E): where W (K) a (E) is the approximation to W(E) with order K and the coefficients W k , ∀k = 0, 1, . . . , K are the generating solutions. Naturally, the smaller z dc is, the less order K is needed before the approximation converges. After substituting (23) into (22) and taking logarithm on both sides, we obtain Taking the derivative of this equation from 0 to K times and equating z dc to zero each time gives us K + 1 generating equations. We list them with K = 2 here: Then, it is straightforward to get the generating solutions: Using the first two generating solutions and (23), the W(E) is approximated in order K = 1 by: Substitute this into I 0 = 0 and solve for R L , the optimal resistance based on the 1st order approximation is: This solution is then the closed-form approximation with the first-order truncation for extremely low input power. Note that what is inside the bracket is the diode's resistance at low power [29], which suggests the load should match the resistance of all diodes in series to obtain maximum output power.
Furthermore, using all three generating solutions in (28), the W(E) is approximated in order K = 2 by the following: This approximation of higher order is accurate over a wider z dc range than the 1st order approximation in (29). By substituting this into I 0 = 0, multiplying a positive term α(α −1 + i s R) 4 /(i 2 s z dc ) to both sides of the equation, and simplifying, we get a cubic equation about R: where µ = z dc /2 − i s . Since only positive multipliers are used during the derivation of (32), the equation (32) is equivalent to ∂P dc ∂R L = 0. During the simplification of the above equation, we used approximation R ≈ R L /2N in order to simplify the derivation. This is supported by the fact that the diode series resistance R S is normally no more than a few tens of Ohm while the optimal load is typically in the order of kilo-Ohm. As the optimal load decreases to lower magnitudes with higher input power, the approximation (31) will become inaccurate, as we will show in Section 4 for validation results. The solution to the above cubic function is found by using Cardano's general cubic formula. The roots of a cubic equation ax 3 + bx 2 + cx + d = 0 are given by: . The choice of plus or minus in B is arbitrary as long as it does not lead to B = 0. We then choose the smallest positive real root out of the three, i.e., where Θ = {k ∈ {0, 1, 2}|x k is real and positive}. Theorem 1. The smallest positive root of (32) is the optimal load resistance that maximizes P dc when z dc < 2i s .
Proof of Theorem 1. Denote the left hand side of (32) by C I 0 . C I 0 has a positive y-intercept 1 α 3 i 2 s , so its positive before R increases to its minimum positive root and becomes negative after that. C I 0 has the same polarity as partial derivative ∂P dc ∂R L because there is only a positive term multiplied to I 0 , which means the first positive root is a local maximizer of P dc . It can be easily proven that C I 0 either monotonically decreases or increases first then decreases when z dc < i s by inspecting C I 0 's derivative. This means C I 0 always has a single positive root when z dc ≤ 2i s ; thus, the local maximizer is also a global maximizer. When z dc ≥ 2i s , there may be more than one positive root, but the small z dc assumption is violated so the perturbation approximation is inaccurate anyway.

Validation and Discussions
The validation consists of two parts: simulation and measurement, whose details will be explained in this section. The results and insights obtained from the validation will also be discussed.

Simulation Setup and Results
To verify the accuracy of the proposed methods, a set of transient simulations are carried out with MATLAB Simscape Electrical [30] by sweeping the load R L . The load sweep starts from 10 Ω to several tens of kΩ. Two low-barrier Schottky diodes Skyworks SMS7630 and Avago HSMS285x are used for comparison. Key parameters of the two considered types of diode are taken from their data sheets and summarized in Table 1. In Simscape, the junction capacitance C J is modeled as a voltage dependent parameter calculated based on zero-bias junction capacitance C J0 , junction potential V J , and grading coefficient M. All capacitors in Figure 1 are set to 500 pF. Besides, the simulation is carried out in three different frequency bands: 400 MHz, 900 MHz, and 2.4 GHz, due to their availability of license-free bands.  Figure 3(a1) shows the calculated optimal load of three different rectifier topologies, i.e., half-wave, 1-, and 2-stage voltage-multipliers with Skyworks SMS7630 diode at 400 MHz frequency band. It can be seen that the numerical solution to the analytical model (red) has good accuracy compared with simulated results (blue) for all topologies. This proves that our proposed simplified analytical model is sufficiently accurate and that no numerical simulation is needed. Besides, the optimal load of 1-and 2-stages voltagemultipliers are roughly 2 and 4 times larger than that of the half-wave rectifier, which corresponds to 2 and 4 times more series diodes from the load's view point. Figure 3(a1) also shows the closed-form solutions with truncation order K = 1 (yellow) and K = 2 (purple). When K = 1, the closed-form result is accurate only when input power is extremely low and is an upper bound of optimal load. This is helpful when determining the specification of an adaptive optimal load system. For K = 2, the valid input power region is wider until approximately 30 mV of input voltage amplitude, after which it becomes inaccurate. This completely closed-form solution is helpful in very low power applications due to its extremely low computational complexity.  GHz. This is because the Skyworks diode has very small parasitic parameters, see Table 1, which means the reactance part of the diode impedance remains negligible within the frequency spectrum that we considered. Figure 3(b1-b3) shows the calculated optimal load at three different frequency bands, with multisine signals consisting of four subcarriers that are separated by 1 MHz. The numerical solution to the analytical model (red) still shows high accuracy in low input power region, while larger discrepancy is observed as input amplitude increases than when N f = 1. This is because a much larger signal period and thus a much larger ripple is created by the multisine signal. As a result, to minimize the output ripple, an output R-C section with a much larger time-constant is needed than when single-sinusoid signal is used. In the simulation, the output capacitor is 500 pF all the time, so when the load decreases, it will come to a point when the output ripple becomes significant, which is also when the low ripple assumption of the rectification model fails. In practice, this can be avoided by using a large enough capacitor in the output R-C section based on the applied signal. Figure 4 shows the optimal load calculated by the proposed methods and simulation when using Avago HSMS285x. Similarly to the results with the Skyworks diode, the proposed analytical solution (red) shows very good accuracy compared with simulated results (blue). However, at 2.4 GHz, a slightly larger discrepancy can be observed between the analytical and the simulated results, due to the fact that the Avago diode has considerably larger parasitic capacitance and inductance as can be seen from Table 1. This means at higher frequency, the effect of parasitics becomes more significant while the simplified model neglects it. Nevertheless, the error is still minor within the frequency range that we consider. Another observation is that the optimal load with the Avago diode is almost twice as large as the Skywork's. This can be interpreted from the order 1 closed-form solution. The saturation current i s of the Avago diode is almost half of the Skyworks one. According to (30), this corresponds to an approximate twice as large optimal load. This observation shows the optimal load of a rectifier is highly dependent on the diode's parameter.

Measurement Setup
To further validate the results, the one-, and two-stage voltage multiplier PCBs are designed in Altium Designer at 400 MHz and fabricated, see Figure 5. Only 400 MHz is chosen for fabrication because of the lack of high-frequency probes for debugging purposes in our lab. An IS400 substrate with dielectric constant r = 4.3 and thickness h = 0.119 mm is used. Grounded co-planar waveguide (GCPW) with vias is used as transmission line with track and slot width of 0.225 mm and 0.17 mm to ensure 50 Ω characteristic impedance. An edge-mount SMA connector is used for RF input, and a pin header is used to connect external variable load. All capacitors used on the PCBs are 500 pF. The used Schottky diode is SMS7630-040LF from Skyworks. Measurements have been conducted to obtain experimental data to validate the model presented in Section 2.
The variable load is achieved by a resistor bank on a bread board, see Figure 6. In total, there are 14 resistors, and 16 resistance values are used in the measurement. The used resistance values are listed in Table 2.    Figure 7. The measured output DC voltage and power with one-and two-stage multipliers are shown in Figures 8 and 9, respectively. The voltage and power are plotted against the load resistance with different tone amplitude V A . During measurement, V A is measured at the central pin of the SMA connector on the PCB using a Teledyne LeCroy SDA816Zi serial data analyzer with a ZS1000 active probe with 1 GHz bandwidth. The fluctuation with the measured results with low input V A and especially low load resistance is because of the low output voltage, which is close to the digital oscilloscope's noise floor. Despite this, the measured and simulated results are consistently in very good agreement.    (17) and (18). The accuracy of the analytical model is confirmed with respect to both measured and simulated results when N f = 1 for all input levels. When N f = 4, however, the model fails to predict the rectifier output with small loads when the input level is high. This is because high PAPR signals in general (in this case the multisine signal) need an R-C section with a higher time constant than the conventional single-sine signal to eliminate the output voltage ripple, and a negligible ripple is a prerequisite for our simplified model, as we explained in Section 4.1. Indeed from Figures 8 and 9, as the load increases, which leads to a larger time-constant, the model becomes more and more accurate.
Moreover, the optimal load based on the measured data as a function of V A is shown in Figure 10. The simulated results and the numerical solution of the analytical model are also shown as solid and dashed lines, respectively, for comparison. Note that the resolution of the measured optimal load is limited by the step size of the variable load listed in Table 2. Also note that the optimal load associated with the lowest input level tends to be an outlier since the rectifier's output voltage is close to the oscilloscope's noise floor, so more randomness is observed on the left-most measured point in Figure 10a,b. It can be seen that the simulated data is in close agreement with the measured data when N f = 1 and N f = 4. The numerical solution of the analytical model also shows great agreement with the measured data except in the high input V A region with four-tone multisine signal, which has already been explained before.

Conclusions
In this paper, we analyzed simplified analytical rectification models for the halfwave rectifier and the N-stage voltage-multiplier. The targeted rectifier topologies are generic, and the models consider the diode as its realistic equivalent circuit. Based on the models, a set of methods that calculate the optimal loading condition for the rectifiers are given, including a low-complexity numerical method, and closed-form approximations for low input power scenarios. The proposed methods are validated by both simulation and measurement.
The simulation results show that the parameters of the diode, namely, saturation current i s and ideality factor n, significantly influence the optimal loading condition. The simulation results also show that the carrier frequency does not influence the optimal loading condition with Skyworks SMS7630 diode. The effect of frequency gets larger only when the frequency and the diode parasitics get larger. In our simulation, the Avago HSMS285x diode with much higher parasitics exhibits more discrepancy between simulated and analytical optimal loads at 2.4 GHz than 400 MHz and 900 MHz. However, the discrepancy is still negligible. This means the frequency impact is negligible at least below 2.4 GHz.
The proposed numerical and closed-form methods have low computational complexity, which can provide a head start when designing a rectifier system. It provides very good accuracy without the need for either harmonic balance or transient simulation provided that the output voltage ripple is eliminated. Moreover, the proposed methods are also valid for general signals, for example, novel input signals such as the multisine waveform, with which the problem can quickly become infeasibly large for harmonic balance as the number of tones increases [7]. Another possible application is adaptive load control in an actual rectifier to ensure optimal efficiency. Implementation of such a control scheme constitute future work.

Data Availability Statement:
The data can be made available upon request to the correspondence author.