Modelling of SEPIC, Ćuk and Zeta Converters in Discontinuous Conduction Mode and Performance Evaluation

High-order switched DC-DC converters, such as SEPIC, Ćuk and Zeta, are classic energy processing elements, which can be used in a wide variety of applications due to their capacity to step-up and/or step-down voltage characteristic. In this paper, a novel methodology for analyzing the previous converters operating in discontinuous conduction mode (DCM) is applied to obtain full-order dynamic models. The analysis is based on the fact that inductor currents have three differentiated operating sub-intervals characterized by a third one in which both currents become equal, which implies that the current flowing through the diode is zero (DCM). Under a small voltage ripple hypothesis, the currents of all three converters have similar current piecewise linear shapes that allow us to use a graphical method based on the triangular shape of the diode current to obtain the respective non-linear average models. The models’ linearization around their steady-state operating points yields full-order small-signal models that reproduce accurately the dynamic behavior of the corresponding switched model. The proposed methodology is applicable to the proposed converters and has also been extended to more complex topologies with magnetic coupling between inductors and/or an RC damping network in parallel with the intermediate capacitor. Several tests were carried out using simulation, hardware-in-the-loop, and using an experimental prototype. All the results validate the theoretical models.


Introduction
Discontinuous conduction mode (DCM) appears in current unidirectional DC-DC elementary switching converters such as buck, boost or buck-boost, whose switch consists of a transistor (usually a MOSFET or an IGBT) and diode, when the inductor current becomes zero in the diode conduction subinterval. The diode turns OFF and a third subinterval appears in which both transistor and diode are OFF [1,2]. In these converters a continuous conduction mode (CCM) is easily achieved by using synchronous switching, that is, replacing the diode with a transistor and applying complementary switching signals to the resulting current-bidirectional half-bridge structure [1,2].
However, the unidirectional switch is easier to implement and sometimes DCM operation is preferred because it reduces problems related to the diode reverse recovery current [3]. Further, DCM operation in boost and buck-boost converters has been proposed to eliminate the right half-plane zero that can limit the voltage control loop bandwidth [3]. In addition, paralleling DCM converters (with or without interleaving) is achieved naturally without a dedicated control strategy [4].
In single phase AC-DC power factor correction (PFC) applications based on the boost converter, the inductor current becomes discontinuous in the vicinity of the zero-crossings After an intense search of high-order converters in the literature, it is concluded that the scientific community is more focused on the application than on the modelling of high order converter operating in DCM. The motivation of this research emerges from the fact that the methodology proposed in [28] to model the DCM of theĆuk converter does not work properly in the case of the SEPIC converter in DCM. There were problems to identify a key current component denoted as i x in the differential equation of the intermediate capacitor voltage. In this work, a novel full-order method based on including explicitly the diode average current in the system equations is proposed. The diode average current is obtained for the SEPIC converter by means of a graphical procedure adapted from the procedure followed for theĆuk converter in [28] and for the interleaved converters in [30]. The use of the diode average current allows us to extend easily the model developed for the SEPIC converter to theĆuk and Zeta converters. In fact, it provides better results for theĆuk converter than using the model in [28]. In practice, it is a common procedure to magnetically couple the inductors to reduce from two to one the magnetic core to implement both inductors [31]. Another typical procedure is adding a damping network to improve the transient converter behavior. The damping network is a simple way to minimize the settling time and suppress current and voltage spikes preserving the semiconductor devices. It is also well known that the addition of a damping network in parallel to some capacitors considerably improves the converter's dynamics (see Chapter 16 in [1]). Another example of the improvement of a converter's dynamics can be found in [32], where the use of magnetic coupling and a damping network moves the right half plane zeroes to the left half plane in a similar high-order switched converter operating in CCM. The prize to pay for the mentioned improvements is a slightly reduced conversion efficiency due to the added resistive losses in the damping network. In all the cases, the model proposed in this work can also be easily adapted to versions of the SEPIC, Cuk and Zeta converters depicted in Figure 1 in which the inductors are magnetically coupled and/or an RC damping network is added in parallel to the intermediate capacitor.
The main benefits of the proposed methodology are listed below: • Because it is based in simple graphical representations of inductor's and diode current waveforms it is easy to understand and apply; • Provides a full-order model that can be particularized to any of the three high-order step up/down switching converters with or without positive/negative magnetic coupling between inductors and damping networks in the intermediate capacitor; • The three converters and its variants can be analyzed in the classical forms depicted in Figure 1, where the MOSFET and diode do not share any common node. To apply Vorperian's method, which also provides full-order models, the structures of two of the converters must be modified to a "common-common" configuration of the DCM switch.
This paper is a contribution to full-order modeling of the SEPIC, Zeta, andĆuk DCM converters, and it includes simulation, hardware-in-the-loop, and experiments in power circuits to validate the obtained models. Most works in the literature perform only theoretical analysis and simulations. The remainder of the article is organized as follows: Section 2 proposes the modelling procedure, first in a detailed way for the SEPIC converter, and later its generalization toĆuk and Zeta converters. The model performance in terms of frequency and transient responses are verified in Section 3 by comparing the theoretical predictions with ideal simulations of the switched converters using PSIM software. In addition, hardware-in-the-loop tests and experimental results are presented. Finally, the conclusions and proposal for future works are discussed in Section 4.

Modeling in Discontinuous Mode of SEPIC,Ćuk and Zeta Converters
The proposed modelling procedure will be applied first in a detailed manner to the SEPIC converter. Afterwards, the method is generalized to the above mentioned high-order converters in DCM:Ćuk and Zeta. The non-linear model provided initially by the proposed method, that will be linearized around the steady-state equilibrium point, has considered the following assumptions: • Ideal no-losses components, without parasitics; • Constant switching frequency f s and period T; • Capacitors large enough so that their average voltages can be considered approximately constant through a switching cycle and small voltage ripple amplitudes.

Analysis and Modeling of SEPIC Converter in DCM
The proposed methodology starts with the obtention of three ideal subcircuits assuming DCM depicted in Figure 2 from which, by following Kirchhoff's voltage laws, the inductor current slopes at each subinterval are obtained (1) and ( 2). Subcircuits in Figure 2 are defined by the conduction states of the converter semiconductors (MOSFET and diode) along a switching cycle of constant duration T. At the first subinterval, whose duration is d 1 T, the MOSFET is ON and the diode is OFF (Figure 2a). The duration of the second subinterval is d 2 T. In this subinterval ( Figure 2b) the MOSFET is turned OFF and the energy stored at the inductors produce the diode activation. Finally, with the MOSFET still OFF, a third subinterval (DCM) appears when both inductor currents combine so that the diode current is zero and the diode turns OFF (Figure 2c). The duration of the third subinterval in which both switches' semiconductors are OFF is 1 − (d 1 + d 2 ) T. The state variables of the model are average inductor currents and capacitors voltages i L 1 , i L 2 , v C 1 , v C 2 , and v C d . Magnetic coupling M between inductors L 1 and L 2 has been considered. A damping (R d C d ) network connected in parallel to the intermediate capacitor has also been taken into account as shown in Figure 2.
(2)  A particular case are slopes in the third subintervals, since they are equal for both currents they have been renamed with just one subindex as m 31 = m 32 = m 3 .  The current slopes, obtained from Figure 2 using Kirchhoff voltage law, have been summarized in Table 1. As expected, the slopes depend on the average voltages and the parameters of the magnetic elements (L 1 , L 2 and M) compacted by using additional parameters ∆L and L S , the determinant of the magnetic parameter matrix and the equivalent inductance in the DCM subinterval, respectively.
The inductor current average state equations obtained as described previously are the first two of the non-linear model in (3). The remaining equations in the model are the average capacitor voltages that are derived from Kirchhoff current laws. In the equations corresponding to intermediate capacitor C 1 and output capacitor C 2 , the proposed model introduces the diode average current (i D ) and the relative duration of the second subinterval (d 2 ) as auxiliary key variables that will be determined graphically in the next subsection. As will be seen, these two variables contribute significantly to the non-linearity of the model, that has as inputs the relative duration of the first subinterval (d 1 ) and the assumed constant input voltage value (v g = V g ). Note that d 1 represents the nominal duty cycle of the converter.

Slope
Equation

Nonlinear Model of Average Values Based on a Graphical Method for the SEPIC Converter in DCM
The full-order non-linear model of average values of the SEPIC converter shown in (3) allows us to analyze the converter behavior in the operation interval. In general, the inductors currents have a damped oscillatory behavior (see Figure 3a) where, as mentioned previously, it is possible to identify three operating conditions as a function of the average slope: current transient with positive slope (Figure 3b), current transient with negative slope (Figure 3c) and inductor current in steady state ( Figure 3d) with zero slope. In Figure 3b it is observed how the average values of the currents increase. This behavior is directly associated with the positive sign of the m 3 slope. Likewise, in Figure 3c the current average values decrease (m 3 < 0) while in Figure 3d the average currents reach a steady state value (m 3 ≈ 0). It is important to note in Figure 3 that i L 2 has been intentionally plotted with a negative sign to show that in the third sub-interval, slopes of i L 1 and −i L 2 have equal magnitude (m 3 ) as seen in (1) and (2).
In steady state, inductor currents exhibit slopes of opposite signs in the first and second subintervals, and zero slope in the third subinterval (m 3 = 0). The slopes and durations of the first and second subintervals result in a constant average inductor current. Due to the rectilinear behavior of the inductor currents in each subinterval, it is possible to obtain their average values from the areas of the triangles between the curves and the horizontal axis. In (4), a general expression of the average inductor current is shown, where m 1j is the slope of the inductor current in the first sub-interval and I 3 is the constant value of the current in the third sub-interval.
Replacing the slope and evaluating the sign of I 3 in (4), Equations (5) and (6) are obtained. Constant I 3 is eliminated by adding the previous equations so that the second subinterval duration is obtained (7). On the other hand, (8) allows calculation of the average diode current. This equation is obtained by adding the average inductor currents in the second subinterval. i D is proportional to the area between the inductor currents as shown in Figure 4a and redrawn as a right triangle in Figure 4b.
Since the nonlinear model will be later linearized around the steady-state equilibrium point, it has been assumed that the proposed method, which derives the different average current values from the triangular areas in the steady-state waveforms, will provide simple and precise enough expressions of d 2 (7) and i D (8) to complete the model in (3). Both expressions will introduce additional nonlinearities to the dynamical model of the SEPIC converter.

Steady State Operating Point of the SEPIC Converter in DCM
The steady state operating point (9) has been obtained by replacing (7) and (8) in (3) and equating the derivatives to zero. where As expected in a DCM SEPIC converter in open loop [10,11] an equivalent pure resistive input impedance is deduced from the input current expression.

Full-Order Dynamic Model
The non-linear model of average values of the SEPIC converter established in (3) can be extended to theĆuk and Zeta topologies, changing the slope values according to Table 2. Furthermore, because of differences in the output section of the converters, it is necessary to include in the v C 2 's equation the variable ς that depends on the converter type to unify the general model. To complete the generalized nonlinear model d 2 and i D equations must be included. The resulting model is given in (12).
where ς is a function of the converter: Note that variables d 2 and i D have the same expressions for the three converters: SEPIC,Ćuk and Zeta.

Steady State Operation Point
The methodology to obtain the steady state operating point of the SEPIC converter is valid for all three converters. Equations of i L 1 , i L 2 v C 2 and v C d shown in (9) are equivalent forĆuk and Zeta topologies. The only difference is for v C 1 . Additionally, d 2 included in (10) is valid for any of the three converters. The generalized expressions of the operating point are given in (14) where having a pure resistive input impedance in terms of average voltage and current is a common characteristic of the SEPIC,Ćuk and Zeta converters in DCM. Note that the input current of the Zeta converter has the same average value than its L 1 inductor current.
Note that Equation (11) is valid for all three converters.

Boundary between Continuous and Discontinuous Conduction Mode
Continuous and discontinuous operation modes can be defined according to constant where k c is the k value in the boundary between operation modes. It can be easily verified that By replacing this result in the boundary condition d 1 = 1 − d 2 and solving for k c , it is obtained which corresponds exactly with the expression of k c presented in the literature for buckboost converters [2]. Furthermore, if the load resistance is constant then d 2 is also a constant in DCM, while d 2 satisfies the equation d 1 + d 2 = 1 in CCM. Based on these features it is possible to find the relation between d 1 and d 2 shown in Figure 5. The boundary between both modes is the common point between the lines d 2 = Operation zones of high-order converters.

Linearized Model
The linearization procedure is well known. The full-order nonlinear model of any of the three converters can be represented aṡ where x is the state vector and u is the input vector defined as To obtain the small signal model, the non-linear model is linearized around an operating point (x o ). The small signal model can be expressed aŝẋ where A o and B o defined in (20) are the Jacobian matrices evaluated at the operating point.
Analytical expressions of the small signal model are very complex, therefore it is usually more practical to obtain numerical expressions for each particular case.

Results
Comparisons between the theoretical and the switched models in time and frequency domains are presented in this section by means of PSIM simulations, hardware-in-theloop (HIL) tests and experimental results. A description of the nomenclature used is presented below: Experimental results: direct measurements in a real proof-of-concept reconfigurable prototype of high-order converters.
In order to explore the scope of the proposed theoretical model, the three high-order converter structures have been used with different magnetic couplings: null, positive and negative. A base set of circuit parameters has been proposed for all three converters. Some parameters were intentionally changed to analyze the response under non-fulfillment of design criteria (high voltage ripple capacitors or inductor currents without triangular waveform).
It is relevant to clarify the notation used to present the results. Until now in this paper, average values nomenclature has been used to express variables from the theoretical model according to equation x = X +x; where x is an average value, X is a steady state value, andx is the small signal value. Thereby i L 1 , i L 2 , v C 1 , v C 2 represent theoretical model variables and i L 1 , i L 2 , v C 1 , v C 2 will be used to denote switched model variables.

Component Description
The selection criteria for the inductors is to keep a fixed value of the self inductance with or without magnetic coupling. The value of L 1 and L 2 have been selected equal to 56.4 µH. Additionally, the inductors selection fulfills a compromise between a high operating margin in DCM and an acceptable current ripple. A mutual inductance of 47.4 µH is achieved with the chosen inductors array, so a coupling factor of k a = 0.84 is obtained. The mutual inductance can be considered positive or negative depending on the component ports connection. In some cases it has been considered that there is no coupling between L 1 and L 2 (M = 0).
The values of the capacitors C 1 and C 2 were selected considering the criteria of reduced size and approximately constant average voltage. Capacitor values of C 1 = C 2 = 5.0 µF ensure peak-to-peak ripple capacitor voltage amplitudes less than 4%. Regarding the damping network, its values have been selected, taking into account the guidelines provided in [32]. A capacitor ten times larger than the intermediate one has been selected while the series resistor has been adjusted by simulation so that it ensures a sufficient damping of the internal dynamics. The selected values were 1.5 Ω for R d and 50 µF for C d . The load resistance has also been selected as R = 100 Ω to ensure DCM at the operation points considered in the study.
Three parameter sets have been defined for the proposed model validation. They are summarized in Table 3. Because of a temporary unavailability of the initially selected loosely-coupled magnetic components [31], an almost equivalent arrangement using Coilcraft's Hexa-Path perfectly magnetic coupled inductors and other non-coupled inductors has been used. A description of each arrangement is given below:

Operation Points
Taking into account the three high-order converter structures and the three possible types of coupling (positive, negative or zero), three case studies have been defined to verify the performance of the proposed full-order model in a broad enough way. The case studies are:Ćuk without magnetic coupling between the inductors, SEPIC with positive magnetic coupling and Zeta with negative magnetic coupling. The operating points listed in Table 4 are obtained by replacing in the theoretical expressions the base set of circuit parameters (Test-1) and the simulation parameters (V g = 10 V, d 1 = 0.4, f s = 100 kHz). In this table the constant (k) allows determining the conduction mode in which the converter operates. This value is less than k crit = (1 − d 1 ) 2 = 0.36, and therefore the converters operate in DCM, as it is verified for all presented cases. Finally, it is satisfied that v C d = v C 1 in steady state.

Transfer Functions
Tables 5-7 includes the theoretical transfer functions of inductor currents and capacitor voltages that have been considered in time and frequency domain analysis. In this work, transfer functions can be a function of the input voltage or the duty cycle. The transfer functions can be of 4 or 5 order depending on the addition of the damping network in the topologies. In Tables 5-7, it can be seen that the transfer function of i L 1 /v g is the only one that has all its zeros in the left half-plane in all cases. The other transfer functions have at least one zero in the right half-plane. Another important finding is seen in the analysis of the damping network effect. In the absence of the damping network, the transfer function presents a pair of complex poles with a very small real part 32.48 and very little damped. In fact, they are the dominant poles. With a damping network, the effect of these poles is well damped and the dominant pole becomes a real pole with value of 4012. From the point of view of pole analysis, there is a good damping.

Small Signal Response
The objective in small signal is to verify the correspondence between switched and theoretical model responses. The structure used in this comparison is theĆuk converter without magnetic coupling with the parameter set for the power circuit Test-1. To obtain the results depicted in Figure 6, a reference change in the input voltage of 1 V has been applied. The input voltage v g changes from 9 V to 10 V at t = 10 ms and decreases again to 9 V at t = 15 ms. The theoretical model results correspond to a linearized model for the operating point v g = 10 V. In Figure 6a, the averaged model currents have a constant behavior, except during transitions where a small disturbance occurs, but the steady state condition is quickly reached. In Figure 6b it can be observed that the average voltages of the proposed model follow the behavior of the switched model even after the disturbance. The magnitudes obtained by the theoretical model for v g = 10 V are approximately equal to the operating point values listed in Table 4. Currents and voltages averaged values of both switched and theoretical model for v g = 9 V and v g = 10 V are given in Table 8. These results validate the good performance of the theoretical model calculated for v g = 10 V condition to approximate the average values of the responses obtained from the switched simulations for v g = 9 V and v g = 10 V. The relative error (RE) were less than 0.51% in all cases. The results show that the v g = 9 V condition is a small signal operation as had been supposed before.        Table 3.

Description Transfer Function
Zeta (M < 0, Test-1)î L 1 (s) v g (s) = (s + 1616.65) (s + 840.76) 2 + 56857.98 2 (s + 2011.00)(s + 2107171.60) (s + 9390.14) 2 + 42766.67 2 =   In the analysis carried out in this work, the SEPIC converter was the topology that, without a damping network, requires the longest time to reach a steady state. For this reason, the positive-coupled SEPIC converter was used specifically to analyze the damping network effect on the capacitors voltage. Two parameter sets have been used in the simulation: Test-1 for response without damping network and Test-2 for the analysis of the damping network effect. Switched and theoretical model responses are depicted in Figure 7a,b. In the presented results, the input voltage changes from 9 V to 10 V at time t = 120 ms. The direct effect of the damping network is observed in the intermediate capacitor voltage. In the absence of the damping network, the voltage requires a significant settling time (in the order of 80 ms) to reach steady state. On the other hand, with the addition of the damping network, the settling time is minimal. These behaviors are equivalent in both switched and theoretical models. It can be verified in graphs from Figure 7 that the theoretical model of average values also has an equivalent performance to the switched model when the damping network is added to the power circuit of the higher-order converter.

Non-Fulfillment of Design Criteria
The topology considered in this case is the negative-coupled Zeta converter. The purpose of this analysis is to show that, when the low ripple condition is not fulfilled in the capacitors, the theoretical averaged model does not approximate accurately the switched model. In this section, the Test-1 and Test-3 parameter sets have been considered. The difference is that the value of C 1 passed from 5 µF in Test-1 to 0.5 µF in Test-3. Derating the capacitor by a factor of 10 times is a violation of the design criteria of approximately constant capacitor voltage. Note that in the Zeta converter the averaged voltages in C 1 and C 2 are equal. According to Table 4 this value is 42.16 V. It can be verified in Figure 8 that v C 1 and v C 2 are equal to the theoretical value in all cases, since the operation point in steady state does not depend of the capacitor values. It is also observed that for the condition C 1 = 5 µF the average values of the switched model voltages are approximately equal to the theoretical model values. When the capacitor C 1 changes to 0.5 µF two situations are evident: (i) the voltage ripple in C 1 increases from 3.1% under design conditions to 34%, while the ripple of C 2 remains constant, (ii) the average values voltages in C 1 and C 2 for the switched model increase and differ from the theoretical model values.
In Figure 8d, it is observed that v C 2 does not correspond to the average value of v C 2 . It can also be easily verified by area analysis in Figure 8d, that v C 1 does not correspond to the average value of v C 1 . In fact the new average value of v C 1 and v C 2 is 45.3 V. It is concluded that the theoretical model values do not correspond with the average value of the switched model, which increased by 3.1 V with the decrement in C 1 capacitor. An important comment on the currents comparison in Figure 8 is about their waveform shapes. In Figure 8e both currents, i L 1 and i L 2 , have a piecewise linear function of triangular shape while in Figure 8f, the triangular waveform is not completely linear. Logically the capacitors ripple increment affects the currents triangular shape, which also demonstrates that in the high voltage ripple condition the theoretical model does not faithfully reproduce the switched model results.

HIL Validation
Nowadays, the use of Hardware-in-the-loop (HIL) tools to validate the controllers performance is more popular [33]. In this paper, different tests have been carried out in HIL to validate the simulation results in the high-order switched DC-DC converters previously presented by means of the experimental setup shown in Figure 9. The HIL testing system consists of: where the evaluation kit, a TI 28069M LaunchPad (the red board), is connected to the RT Box via an RT Box LaunchPad Interface (the green board). The differente high-order switched DC-DC converters has been modelled using PLECS RT Box 1. In this way, the converter duty cycle has been generated using TI 28069M LaunchPad, which is a Texas Instrument microcontroller. In this subsection, the HIL test is presented with the goal of validating the time domain responses presented in the previous subsections. Figure 10 shows the HIL test to compare the proposed model and the simulation of the switched model using PSIM of theĆuk converter without coupled inductors shown in Figure 6. In addition, the HIL test to validate the proposed model and the simulation of the switched model using PSIM of the SEPIC converter with positive magnetic coupling shown in Figure 7 is presented in Figure 11. Finally, the proposed model and simulation in Figure 8 correspond with the the HIL test of the Zeta converter with negative magnetic coupling shown in Figure 12. A good agreement between the model, the switching simulations and the HIL results is observed in all the cases. Therefore, the proposed procedure models correctly the considered high order step-up and down converter topologies (SEPIC,Ćuk or Zeta) operating in DCM.   Figure 12. HIL test to validate the proposed model and the simulation of the switched model using PSIM by the Zeta converter with negative magnetic coupling shown in Figure 8: (a) C 1 = 5 µF, (b) C 1 = 0.5 µF. CH1: i l 1 (4 A/div), CH2: v C 2 (1 V/div, ac coupling), CH3: v C 1 (10 V/div, ac coupling), CH4: −i l 2 (4 A/div), and time base of 4 ms.

Experimental Results
A reconfigurable power converter was built to validate the theoretical models and the HIL results. Its design allows the implementation of any topology and any magnetic coupling. The components description of the power converter is presented in Table 9. Considering the reconfigurable characteristic of the power converter, series and parallel interconnections between inductors or capacitors have been done to obtain the closest values to the parameters listed in Table 3. The components configurations are given below:   The same tests carried out with HIL have been performed with the converter prototype. The experimental setup of the power circuit is shown in Figure 14. Voltage and current waveforms for aĆuk converter without magnetic coupling are shown in Figure 15. The effect of the damping network in the SEPIC converter with positive magnetic coupling is shown in Figure 16. Finally, the results of the Zeta converter with negative magnetic coupling are shown in Figure 17. The waveforms in Figures 15 and 16 show good agreement with waveforms in Figures 10 and 11. The results shown in Figure 17 have some distortion due to resonances with parasitic capacitances, but they are similar to the ideal waveforms shown in Figure 12.    Figure 16. Experimental results for the SEPIC converter with positive magnetic coupling which demonstrate good agreement with HIL results showed in Figure 11: (a) without damping network, (b) with damping network. (CH2: v C 2 (2 V/div), CH3: v C 1 (2 V/div), and time base of 500 µs). Figure 17. Experimental results for the Zeta converter with negative magnetic coupling which validate HIL results showed in Figure 12: (a) C 1 = 5 µF, (b) C 1 = 0.5 µF. CH1: i l 1 (4 A/div), CH2: v C 2 (1 V/div, ac coupling), CH3: v C 1 (10 V/div, ac coupling), CH4: −i l 2 (4 A/div), and time base of 4 µs.

Frequency Domain Responses
TheĆuk converter without magnetic coupling has been used to analyze the theoretical model's performance. The same topology was used in the small signal validation. The variables selected for this analysis are one current and one voltage, specifically i L 1 and v C 2 . To obtain broad information on the frequency domain response, transfer functions were considered a function of the input voltage and the duty cycle, which are included in Table 5. The lower limit of the frequency analysis is 100 Hz and the upper limit is 50 kHz, a value that corresponds to half the switching frequency. It is observed in all the bode plots shown in Figure 18 that the theoretical model is equivalent to the switched model response. Another common feature is a resonance that occurs at approximately 10 kHz.

Frequency Domain Validation
Another way to validate the good performance of the proposed methodology is by comparing results with the generalized switch averaging technique [6] in a specific case using frequency responses. To make a fair comparison with the literature, a full-order dynamic model of a Zeta converter in DCM presented in [29] was chosen. The power circuit parameters used to calculate the transfer functions and to obtain the frequency responses are the same as those proposed in [29]. The transfer functions obtained with both methodologies are given in Table 10. Note that all of the models are fourth order transfer functions and the numerator polynomial is second order. The corresponding frequency responses are shown in Figure 19. Both theoretical responses show a good agreement of the frequency response of the switched model up to a frequency about 1/5 of the switching one. Note that frequency response of reduced-order models is usually considered accurate up to about 1/20-1/10 of the switching frequency. Theoretical Switched (d) Figure 18. Frequency response of theoretical and switched models for: (a)î , and (d)v C 2 (s) d(s) .  Figure 19. Frequency response comparison: (a)v

Conclusions
In this paper, a methodology for analyzing high-order switched converters, specifically SEPIC,Ćuk and Zeta, operating in discontinuous conduction mode, is proposed to obtain a full-order dynamic model. The studied converters have very similar piecewise linear current functions if small capacitor voltage ripples are assumed. These converters present a special discontinuity mode where the inductor currents are constant and different from zero. This behavior occurs at the third sub-interval of the switching period in which neither the MOSFET nor the diode conduct. On the basis of the triangular shape of the current diode non-linear average models are obtained. The methodology can be applied to any high-order converter even if additional attributes, such as magnetic coupling or a damping network, are considered. A generalized full-order dynamic model and the steady state operation point summarize the theoretical analysis. Simulations, HIL tests and experimental results validated some full-order small signal models. The comparison of the results demonstrate that theoretical small signal models accurately reproduce the switched models around the operation points as long as the low ripple condition is satisfied. Future research will deepen in the applications, such as power factor correction or visible light communication, the use of the dynamic DCM model to design control laws of the analyzed high-order converters, and the extension of the proposed model's methodology to other converter topologies not modeled in DCM to date.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

Abbreviations
The following abbreviations are used in this manuscript: