Digital Impedance Emulator for Battery Measurement System Calibration

Meaningful information on the internal state of a battery can be derived by measuring its impedance. Accordingly, battery management systems based on electrochemical impedance spectroscopy are now recognized as a feasible solutions for online battery control and diagnostic. Since the impedance of a battery is always changing along with its state of charge and aging effects, it is important to have a stable impedance reference in order to calibrate and test a battery management system. In this work we propose a programmable impedance emulator that in principle could be used for the calibration of any battery management system based on electrochemical impedance spectroscopy. A digital finite-impulse-response filter is implemented, whose frequency response is programmed so as to reproduce exactly the impedance of a real battery in the frequency domain. The whole design process of the filter is presented in detail. An analytical expression for the impedance of real battery in the frequency domain is derived from an equivalent circuit model. The model is validated both through numerical simulations and experimental tests. In particular, the filter is implemented on a low-cost microcontroller unit, and the emulated impedance is measured by means of a custom-made electrochemical impedance spectroscopy measuring system, and verified by using standard commercial bench instruments. Results on this prototype show the feasibility of using the proposed emulator as a fully controllable and low-cost reference for calibrating battery impedance measurement systems.


Introduction
Measuring the impedance of a battery is being increasingly recognized as a fundamental step for its online diagnostic [1,2], i.e., when it is connected and operating in any battery-powered electric/electronic system. It is well known that Electrochemical Impedance Spectroscopy (EIS) data can provide meaningful information on the internal state of a battery [3,4]. Different portions of the impedance curve in the frequency domain are indeed related to different internal components and processes that can be modeled by means of equivalent circuits, and that are correlated with the battery State-of-Charge (SOC) and the State-of-Health. Yet as much as this topic has been widely investigated, most of the published experimental results are obtained by means of standard laboratory bench equipment that is not suited for online applications [5]. Online battery control and diagnostic systems, standardly referred to as Battery Management Systems (BMSs), are a key component in many applications, the automotive sector in particular being presently the subject of extensive research [6,7]. The integration of online EIS measurements into BMSs is an important development that is currently being investigated by several authors, with some promising solutions that have already been published [8][9][10][11][12].
Calibration and test under several working conditions are unavoidable stages in the developing process of a BMS [13,14]. The use of real batteries at this stage is not feasible, since the internal state of a battery and its response to external signals and solicitations change among different batteries (even of the same brand and model). Moreover, the characteristics of a single battery are not stable enough when repeated measurements are performed. A fully controllable reference is thus needed. Commercial bench instruments, such as the Keithley 2281S Series or ITECH IT6400 Series, are DC power supplies allowing for both current sourcing and sinking, which can simulate the voltage of a battery according to a predefined discharge curve [15]. These instruments are well suited to test charge and discharge cycles, but they do not emulate the impedance of a real battery and cannot be used to simulate the time transients expected in operating conditions.
A BMS testing approach frequently discussed in the literature is based on the so-called Hardware-In-the Loop paradigm (HIL) [16][17][18]. In general, a HIL simulator is a hardware that emulates all the input and outputs of the actual system under consideration. In this case, the HIL is designed to emulate a battery or a battery pack, its voltage, current, frequency response, state-of-charge, aging and failures. The BMS under test is interfaced to the HIL, and it can then be operated as if it were connected to an actual battery pack. The HIL is a piece of hardware fast enough to calculate and reproduce in real time the outputs of a real battery according with all the external inputs and solicitations. In general, a HIL simulator is a complex modular system that has to be designed and assembled for specific operations and requirements. Widely used commercial equipment is provided by dSPACE GmbH. In particular, the dSPACE EV1077 emulation board can emulate four cells and in principle can be programmed according to any mathematical model, such as equivalent circuit models including temperature and aging effects. Less complex and even low-cost solutions have also been presented in the literature [19][20][21].
In [22], a programmable setup implementing impedance emulation is proposed for the calibration of LCR meters. A power supply is used to sink the current supplied by the LCR meter, while a voltage generator and a current generator are used to emulate the voltage drop V generated by a current I across an arbitrary impedance Z. Both V and I are then measured by the LCR-meter in order to estimate Z = V I . In this work, we propose an even simpler method to emulate the impedance of a battery that can be used as a reference to calibrate an EIS based BMS or other EIS equipment. The basic idea is to program a Finite Impulse Response filter (FIR), so that its frequency response would match exactly the impedance of the battery that has to be emulated. A general overview of the method is presented in Section 2. An experimental realization will be presented in Section 4.
The main difference of the proposed emulator with respect to the other reviewed solutions is that it does not source or sink any current. As regards the advantages, the emulator can be simply connected in place of the battery to the EIS equipment. It is programmable virtually with any impedance curve, so as to provide a reference for any state of a real battery. Finally, it is a low-cost solution requiring minimal equipment and components, that can be easily replicated to emulate multiple batteries.

General Overview of the Impedance Emulation Method
We refer to the BMS/EIS equipment presented in [11], since it is a very simple system possibly representing the basic scheme of a class of BMSs to be developed. The reference EIS equipment is illustrated in Figure 1. It essentially consists of a controllable current source and two differential Analog-to-Digital Converters (ADCs). A controlled current I is injected into the battery through a shunt resistor R shunt of known value. The injected current is estimated by measuring with ADC1 the voltage difference V shunt across the shunt. ADC2 measures the voltage difference V out across the battery. Thus, the complex impedance can be obtained as where ω is the angular frequency in rad/s. The impedance emulator, sketched on the right of Figure 1, is designed to be connected in place of the real battery, with the only difference that the current I is not injected into the emulator, but flows directly towards the ground through a load resistor R load . By means of an ADC, the emulator acquires the voltage V in across the load, and outputs a voltage V out through a Digital-to-Analog Converter (DAC). A Microcontroller Unit (MCU) is programmed to generate V out according with a predefined impedance model. A picture of the built prototype is shown in Figure 2. The EIS instrument consists of a custom-made current source with its power supply, and a Data Acquisition board (DAQ) that provides two differential ADCs (cf. Figure 1) and is also used to control the current source. The impedance emulator is implemented on a Texas Instruments MCU development board. A simple breadboard is used to connect the shunt resistor and to interface the BMS to the impedance emulator.
The MCU acts as a digital FIR filter, acquiring V in at a sample rate F s = 1 T s , obtaining as input and output the discrete time sequences x[n] = V in (nT s ) and y[n] = V out (nT s ), which are related as: where h[n] is the impulse response of the system in the time domain, and N is the total number of samples. It is well known from the theory of digital filters [23] that h[n] is related to the frequency response of the system Z(ω) by the Discrete Fourier Transform (DFT) as: where ω k = 2πF s N k. Thus, the MCU is programmed so as to keep the ratio of V out (ω) over V in (ω) always equal (numerically) to the battery impedance Z(ω) that one wants to emulate, independently of the value selected for R load . When the emulated impedance is measured by means of the EIS equipment, the following relations hold: Thus, once programmed, the same emulator could be in principle adapted to different EIS instruments by just selecting a suitable R load . A reference impedance model Z(ω) has to be chosen. It can be obtained from the measured impedance of a real battery as it will be illustrated below. Then, the coefficients h[n] are obtained by inverting the DFT and stored in the non-volatile memory of the MCU. Each time a sample of V in is acquired by the ADC, the convolution sum (2) is calculated, and the resulting V out is written on the DAC register. The length of the sequence N is upper bounded by the memory capacity, and also by the clock frequency of the MCU, since the convolution sum has to be computed in a time shorter than the sampling period T s ; N is also lower bounded in accordance with the frequency resolution ∆ f = F s N required by any particular application. The full design process of the FIR filter is illustrated step-by-step in Section 3, while the experimental implementation of a test prototype is presented in Section 4.

Design of the Fir Filter
The impedance emulating FIR filter has been designed by going through the following steps. A paragraph will be devoted to the details of each step.

1.
Modeling the impedance of a battery. Since the aim of the filter is to emulate a real battery, it has been designed to reproduce an experimental impedance. An analytical model facilitates the design process, and allows for more control, thus, the measured impedance has been fitted to an equivalent circuit model.

2.
Choosing the number of samples and the sampling rate. This has to be done according to the frequency range of interest for the impedance, and with the memory capacity and the clock frequency of the MCU.

3.
Definition of the impulse response. It has been derived from the impedance curve in the frequency domain by an Inverse DFT.

4.
A numerical simulation of the filter response. This has been performed on MATLAB in order to verify that the model is correct.
The experimental results are shown in Figure 3. The choice of the two SOCs is motivated by the fact that they are associated with two impedance curves that are significantly different, practically being at the extremes of the range of variation of the battery impedance. Hence, we wanted to check the performance of the system at both the extremes (see Section 5.1). The battery has been modeled as the equivalent circuit shown in the same figure. It is a model commonly used in the literature, which we had previously verified to fit well the experimental impedance curves of the Samsung battery [24]; it implements some fractional order components, i.e., two Constant Phase Elements (CPEs) and a Warburg element. The complex impedance of the equivalent circuit is: where s = iω. The model has thus nine parameters that have to be fitted to experimental data. The solid curves plotted in Figure 3 have been calculated by using Formula (5), after θ had been estimated through a non-linear least-squares fitting algorithm. The chosen frequency interval allows detection of the two main features of the impedance curve: the semicircle at higher frequencies and the straight line at 45 • at lower frequencies.

Step 2: Choosing the Number of Samples and the Sampling Rate
The number of samples N and the sampling rate F s cannot be selected independently, since they both define the frequency resolution as ∆ f = F s N . The frequency range of interest is 0.1-400 Hz, hence, in order to meet the Nyquist condition, the sampling rate should be F s > 800 Sa/s. We chose F s = 1000 Sa/s. Given the memory capacity of the MCU used to implement the prototype (see the experimental Section 4), we set N = 30,000 Sa. Thus, the frequency resolution of our impedance emulator is ∆ f = 33 mHz, which is enough to even discriminate between the two lower frequency components (100 and 200 mHz). On the chosen MCU, the computation of (2) with N = 30,000 requires 827 µs, which is compatible with the chosen sampling period T s = 1 ms. In case of a different frequency range of interest or different MCU for other applications, the parameters should be reconfigured accordingly to the following analogous criteria. The parameters of the prototype configuration are summarized in Table 1 in the experimental Section 4.
cannot be computed. The solution is to use the low-frequency approximation of s −0.5 given in [25]: i.e., the fractional order response is approximated with an integer order one. Let us define: Hence, by defining Z r = Z − Z w , the impedance can be approximated as Z ≈ Z r +Z w . A very good approximation is thus obtained, as shown in Figure 4. . FIR frequency response obtained by using the approximation (7) compared with the experimental data. The components Z r , Z w and Z i are also reported as to show the goodness of the approximation Z w ≈ Z i for f < 1 Hz.

Step 4: A Numerical Simulation of the Filter Response
The emulator model has been simulated with MATLAB in order to verify that numerical and discretization errors, as well as the noise will not significantly affect the results. Since on the MCU all the computations will be performed using 32-bit single-precision representation of numbers, in MATLAB the 32-bit precision was also explicitly selected, the 64-bit precision being the default.
Both the signal acquisition with the EIS equipment, and the acquisition and processing of the emulator have to be simulated. The simulation can be divided into three stages:

1.
A simulated signal V in is acquired by the EIS equipment at a sampling rate F aq , and by the emulator at sampling rate F s . ADC signal quantization is simulated; 2.
The signal V out is computed by summing (2), and the DAC output is synthesized as a Zero-Order-Hold signal (ZOH); 3.
The acquisition of V out by the EIS equipment at sampling rate F aq is simulated. The impedance is estimated as the ratio of the DFTs of V out and V in .
where indicates the floor function, while is a zero-mean Gaussian noise with variance σ 2 . Simulations were performed by setting σ = 0 and 3 mV. The second value for the noise was used since it is comparable to the random noise observed on experimental measurements. The simulated input signal is shown in Figure 5 for σ = 3 mV.

Simulation Stage 2
The output V out resulting from (2) is shown in Figure 6. The solid blue line is the ZOH signal generated by the DAC with period T s , and σ = 3 mV. The green line with dot markers is the simulation result of the DAC signal as acquired by the EIS measurement system with sampling period T aq = 10T s . Additionally, the ADC quantization for V out was simulated as it was done for V in . The analogous results for σ = 0 are also reported in the plot. It can be noted that V out as synthesized by the DAC is very stable when going from σ = 0 to σ = 3 mV; this is explained by the fact that V out is approximately an order of magnitude lesser than V in , hence the noise acquired with V in is reduced accordingly, and it almost disappears given the finite resolution of the DAC. Then, the noise is added again as the DAC signal is re-acquired by the EIS system.

Simulation Stage 3
The frequency spectra of both input and output signals are obtained by applying a Fast Fourier Transform (FFT) to the sampled sequences of measured voltages: The spectrum of V out has to be corrected for the distortion introduced by the ZOH as This correction is explained and formally derived in Appendix A. The ratio between the corrected V out ( f k ) (10) and V in ( f k ) yields the FIR frequency response.

Simulation Results and Discussion
In Figure 7, the simulated response of the FIR filter is reported and compared with the analytical response function (5). For σ = 0 the agreement is very good for both amplitude and phase. For σ = 3 mV, the agreement is still very good for the amplitude, but some errors are introduced in the phase, in particular at higher frequencies f > 20 Hz. Regardless, in the worst case, the relative error affecting m(Z) is 9%, while the mean relative error is 3%. The relative error on e(Z) is negligible, its mean value being 0.2%, and 0.4% in the worst case. The simulation was performed assuming that signal acquisitions on the EIS measurement system and on the emulator are perfectly synchronous. Although it would be possible, in principle, to implement the synchronization on the actual system, the emulator is intended to be a portable instrument applicable to different equipment, also when the synchronization is not possible. When the two systems are not synchronized, the sampling instant of the emulator can fluctuate with a flat distribution within the T aq sampling period of the EIS equipment. This results in a random delay or anticipation between V in and V out affecting the phase of the impedance. Several simulations have been performed by including between V in and V out a random delay ∆t in the interval − T aq 2 , T aq 2 . The Bode plots of the frequency response for a couple of simulations are shown in Figure 8. The response amplitude is not affected at all, but for F aq = 10 kSa/s, the phase measured at higher frequencies is not repeatable because of the random delay fluctuations. The only solution to this problem, if synchronization is not feasible, is to use a higher sampling frequency, such as F aq = 100 kSa/s, as shown on the right of Figure 8.

Implementation of the Impedance Emulator on an MCU
The impedance emulation method described above could be in principle implemented on any MCU equipped with an ADC and a DAC, provided that its specifications such as clock frequency, ADC sampling rate, resolution, and so on, meet the requirements of the particular application it is intended to be used for. In order to test the devised method, we used the low-cost development board LAUNCHXL-F28379D by Texas Instruments, mounting the 32-bit, 200 MHz dual-core microcontroller TMS320F28379D. All the relevant specification and settings of this implementation are summarized in Table 1. Important configuration details have already been discussed on Section 3.2. Here we add that the duration of the ADC sample and hold window had to be set at least to 125 µs as reported, otherwise, for shorter times, the acquired signal was to noisy, resulting in unacceptable measurement errors.
The computation of the convolution sum (2) was performed as follows. The ADC buffer consists of N 16-bit unsigned integer memory locations storing the sequence x[n], while the impulse response h[n] is stored in a constant buffer consisting of N 32-bit floating point memory locations. In order to store the continuously updating x[n], circular buffering was used, i.e., a pointer to an address of the ADC buffer is incremented by one at each acquisition, and when the end of the buffer is reached, the pointer returns to the beginning of the buffer; hence, after N acquisitions, older values start to be overwritten, since they are not needed anymore. In order to exploit the dual-core parallelism of the MCU, the convolution was split into two separate sums, one over the even terms, computed by core 1, and one over the odd terms, computed by core 2. The sequence of the iterations performed for both sums is illustrated in Figure 9, starting from the memory location labeled as t storing the last acquired sample. Figure 9. The sequence of the iterations performed to compute the convolution (2), split into two separate sums over the even and odd terms, respectively. The first term of the summation is indicated in green, that is, the memory location storing the last acquired sample, i.e., the sample at current time t. The last term is indicated in red.

The Acquisition System
The DAQ of our custom EIS equipment is the 16-bit U2351A data acquisition board from Keysight. The setting we used to test the impedance emulator by acquiring V in and V out are summarized in Table 2. The application of the FFT and the computation of the impedance, as illustrated on Section 3.4.3, are performed in post-processing by using MATLAB. No windowing has been applied, since the sampling rates and the number of samples were chosen as to always acquire an integer number of periods of each sinusoidal component [11]. The DAQ board also mounts a DAC that we used to pilot the voltage-controlled current pump in order to generate the multisine excitation signal. The amplitude of each current component was 50 mA. The shunt and load resistor values were R shunt = 200 mΩ, and R load = 5 Ω.
In order to check the reproducibility of the results, we also tested the emulator by using a bench waveform generator to generate V in , and a bench oscilloscope to acquire V in and V out . Resistors R shunt and R load were not used in this phase. The settings of the oscilloscope are reported in Table 2. The clocks of the two instruments were synchronized by wiring the oscilloscope external-clock input connector to the clock output connector of the waveform generator.
After some preliminary measurements, and by following the analysis presented in Section 3.4.4, we decided to measure the emulated impedance in two separate stages, one for the lower and one for the higher frequencies. Indeed, at lower frequencies, a longer acquisition time is needed in order to acquire several periods of the slower sinusoidal components, hence, the sampling rate F aq = 10 kSa/s was used in order to limit the total number of samples. At frequencies greater than 20 Hz, we instead used the sampling rate F aq = 100 kSa/s, in order to avoid phase fluctuations of the kind shown in Figure 8. The results were then combined into a unique impedance curve over the whole frequency interval 0.1-400 Hz.
As a last point, in simulations, V out was treated as it were generated instantly as V in was acquired by the ADC of the emulator. Of course, this is not the case in the real system, that has instead a latency due to the time required to compute (2), introducing a delay T c = 827 µs between V in and V out . Since the Laplace transform of a delayed function is simply: the effect of the MCU latency on the impedance Z( f k ) is corrected by just multiplying V out ( f k ) by the phase factor exp(i2π f k T c ).

Results Obtained on the Custom EIS Measurement System
The emulated impedance for the SOC 100%, as measured by means of the custom EIS equipment, is reported in Figure 10 for seven repeated measurements. It can immediately be noticed that, although the fluctuations due to random noise are small, there are, however, considerable systematic phase distortions at higher frequencies. Points measured at frequencies greater then 100 Hz looks like complete outliers, while at smaller frequencies, it seems that a linear phase distortion exp(−i2π f k T d ) is present. This can be verified by applying the following calibration procedure: Figure 10. The emulated impedance as measured by the custom EIS system for seven repeated measurements.

1.
Phase calibration. Let us consider the column vector of the measured phases ϕ m = [ϕ( f 0 ), ϕ( f 1 ), . . .] T m , where the index m is used to indicate each one of the repeated measurements, and the vector defined by arranging all the ϕ m in a single column, ϕ = [ϕ 1 , ϕ 2 , . . .] T . Let us also consider the analogous vector ϕ 0 of the expected phases computed analitically. Finally, the column vector f of all the frequencies { f } k repeated many times on a column as the number of repeated measurements (i.e., f, ϕ and ϕ 0 have the same number of elements). The difference between the measured and the expected phase can then be written as the following linear system in the single unknown T d : The least-squares solution is T d = −29.7 µs. Only the frequencies up to 100 Hz were included in the equation system.

2.
Amplitude calibration. Since the ADCs of the acquisition system and of the emulator are different, and can produce different results on equal signals, in general, the amplitude has to be calibrated. As above, let us consider the column vector of the measured . .] T m , then again the single column arrangement A = [A 1 , A 2 , . . .] T , and finally the vector A 0 of the expected amplitudes computed analytically. The amplitude correction is given by a calibration constant k A determined by the following linear system: The least-squares solution is k A = 0.9938, very close to 1. Indeed, in this case, as it can be seen in Figure 10, the amplitudes were already well matching the expected curve even without calibration.
By applying the calibration procedure, the corrected results shown in Figure 11 were obtained. The good agreement of the measured and expected curves up to 100 Hz proves that the hypothesis of a linear phase distortion was right. Nevertheless, the non-linear systematic phase distortion above 100 Hz remains. By keeping the values of T d and k A just computed, and measuring the emulated impedance for the SOC 20%, again a good matching is obtained, as shown in Figure 12. This suggests that the calibration is linked to the EIS system, and does not depend on the response programmed in the filter. In any case, the origin of such a strong phase distortion is not clear. In order to verify that it is due to the EIS system, and not to the emulator, we performed a set of measurements with a bench oscilloscope. Figure 11. The emulated impedance as measured by the custom EIS measurement system after the calibration illustrated in Section 5.1.

Results Obtained on the Oscilloscope
The emulated SOC 100% was measured by means of the oscilloscope, and the same calibration procedure described in Section 5.1 was applied, obtaining T d = −3 µs, and k A = 1.02. The results are reported for two different numbers of samples in Figures 13 and 14, showing a good agreement between measured and expected curves. The slight phase distortion is within the time resolution set on the oscilloscope (T aq = 10 µs at higher frequencies), and might be due to the fact that there is no clock synchronization between the oscilloscope and the impedance emulator. The mean and standard deviation over five repeated measurements of the amplitude and phase of the emulated impedance are reported in Figures 15 and 16. As expected, the error is lower for a greater number of samples. Systematic distortions are at any rate present also in the results obtained with the oscilloscope. However, the phase distortion above 100 Hz in this case is much smaller than that observed with the custom EIS system in Figures 13 and 14. This indicates that the distortion at high frequency is due to the EIS system, and not to the emulator.

Conclusions
We presented a method to emulate the impedance of a battery by means of a digital filter. All the details of the design are described. A low-cost prototype of the impedance emulator has been implemented and tested. A good agreement between the programmed and measured impedance was obtained when the emulator was tested by means of a bench oscilloscope. A relevant non-linear phase distortion was instead observed when the emulator was tested on a custom EIS measurement system. Such distortion is clearly linked with the EIS equipment and will need further investigation. Additionally, other excitation signals (e.g., binary sequences [10]) still need to be investigated on the emulator.
Overall, however, results show the feasibility of using the proposed emulator as a fully controllable and low-cost reference for calibrating battery impedance measurement systems. An immediate continuation of this work will be the implementation of the emulator on a better performing MCU or on a single-board computer, in order to increase both the sampling rate F s and the number of samples N s . This should allow emulation of the impedance at frequencies higher than 400 Hz, at the same time reducing the phase distortion.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author. The data are not publicly available because they have not been ordered and stored in a clear and manageable form.

Conflicts of Interest:
The authors declare no conflict of interest.

Appendix A. Sampling the DAC Signal
First, we briefly review some basic notions on ZOH signals. Let X( f ) be the Fourier transform of any continuous time (c.t.) signal x(t), and X zoh ( f ) the Fourier transform of its respective c.t. ZOH signal x zoh (t), sampled with period T. It is also assumed that the sampling rate F = 1/T and the bandwidth of the c.t. signal satisfy the Nyquist criterion. Hence, the following relation holds [23]: i.e., the ZOH signal has a delay of T/2 with respect to the original signal x(t), and also its amplitude is distorted by the sinc( f T). In general, given the ZOH spectrum X zoh ( f ), the spectrum of the original signal X( f ) can be reconstructed by inverting (A1). From now on, we always assume that the frequencies of all the spectral components, the sampling rates, and the duration of the acquisition window, are chosen in order to always acquire an integer number of cycles for each component, and that an integer number of samples is acquired at each cycle. Thus, the spectral components of the DFT with rectangular windowing, divided by the number of samples, are the same as the spectral components of the c.t. signals.
The DAC signal of Figure 6 is a c.t. ZOH with period T s , generated from the sequence V out (nT s ) as computed by the FIR filter. Let us indicate as V out nT aq the sequence obtained by sampling the DAC signal with sampling rate F aq = 1/T aq = 10 kHz (the EIS samples of Figure 6). To calculate the impedance, we need to calculate DFT[V out (nT s )]( f ), where the sequence V out (nT s ) could be simply obtained by decimating V out nT aq . However, we want to keep all the samples, since, in general, this has an averaging effect on the noise, thus producing better results. We then derive a different method. One might think that (A1) could be inverted as where N aq is the number of acquired samples, while N s = N aq T aq /T s is the decimated number of samples. Although it is correct to identify X( f ) ≡ DFT[V out (nT s )]( f )/N s , this inversion does not yield correct results. Indeed, DFT V out nT aq ( f )/N aq cannot be identified with the spectrum X zoh ( f ) of the c.t. ZOH signal of the DAC, since X zoh ( f ) is not band-limited. The two spectra might be considered the same when T aq T s , and (A2) would thus be correct to a very good approximation. In any case, as we will see in the following, the problem has an exact solution, and it is not necessary to use an approximation, whatever the values of T aq and T s might be.
Intuitively, the solution can be derived as follows. The DAC output can be viewed as a c.t. ZOH signal with period T aq and constant for N periods, with N = T s /T aq = N aq /N s . Hence, in accordance with the general Formula (A1), its Fourier transform can be written as: Since, by construction, the c.t. ZOH signal with period T aq is the same as the c.t. ZOH signal with period T s , their spectrum is the same, hence, we can invert (A1) as: that is the same as the correction (10) that we applied in Section 3.4.3. Let us now derive the same result more formally. For the sake of brevity, we define X s ( f ) ≡ DFT[V out (nT s )]( f ), and X aq ( f ) ≡ DFT V out nT aq ( f ). Let us also define the zero-padded sequence: and let X zp aq ( f ) be its DFT. It is a known result in the theory of signal processing that X zp aq ( f ) = X s ( f ) [23]. The sequence V out nT aq can be rewritten as a sum of translated zero-padded sequences: and its DFT can thus be expressed as: Clearly, since X s ( f ) is band-limited, so it is X aq ( f ). The last summation is also a known result, it being the DFT of the discrete-time rectangular function with N samples: Thus, finally: i.e., the same result is obtained as that in (A4) and (10).