An Array of On-Chip Integrated, Individually Addressable Capacitive Field-Effect Sensors with Control Gate: Design and Modelling

The on-chip integration of multiple biochemical sensors based on field-effect electrolyte-insulator-semiconductor capacitors (EISCAP) is challenging due to technological difficulties in realization of electrically isolated EISCAPs on the same Si chip. In this work, we present a new simple design for an array of on-chip integrated, individually electrically addressable EISCAPs with an additional control gate (CG-EISCAP). The existence of the CG enables an addressable activation or deactivation of on-chip integrated individual CG-EISCAPs by simple electrical switching the CG of each sensor in various setups, and makes the new design capable for multianalyte detection without cross-talk effects between the sensors in the array. The new designed CG-EISCAP chip was modelled in so-called floating/short-circuited and floating/capacitively-coupled setups, and the corresponding electrical equivalent circuits were developed. In addition, the capacitance-voltage curves of the CG-EISCAP chip in different setups were simulated and compared with that of a single EISCAP sensor. Moreover, the sensitivity of the CG-EISCAP chip to surface potential changes induced by biochemical reactions was simulated and an impact of different parameters, such as gate voltage, insulator thickness and doping concentration in Si, on the sensitivity has been discussed.


Introduction
Biosensors for multianalyte detection attracted much attention in many fields of application, including point-of-care and clinical diagnostics, food and drug screening, environmental monitoring, etc. Electrolyte-gated field-effect devices (EG-FED) have been recognized as a promising transducer in designing chemical and biological sensors because of their small size and weight, fast response time, real-time monitoring, label-free and multiplexed biomolecular detection, possibility of on-chip integration of EG-FEDs and signal-processing circuit and compatibility to micro-and nanofabrication technologies with the future prospect of large-scale production at relatively low costs [1][2][3][4][5][6][7][8]. In addition, miniaturized analysis systems (e.g., lab-on-a-chip devices or electronic tongues) based on on-chip integrated EG-FEDs in an array format have received tremendous attention due to their ability for multiplexed and (quasi)simultaneous assaying of multiple chemical or biological species [9][10][11][12][13][14]. Such multiplexed biochemical sensing systems may offer several advantages over devices for single-analyte detection, such as reduced assay time and sample volume, reduced costs and high throughput.
The electrolyte-insulator-semiconductor capacitor (EISCAP) belongs to the family of EG-FEDs and represents a biochemically sensitive capacitor [15]. In contrast to ISFETs (ionsensitive field-effect transistor) or Si nanowire transistors, EISCAPs have a simple structure (see Figure 1a) and are easy and low-cost in fabrication; typical preparation steps do not require photolithographic patterning, and the implementation of a simple O-ring provides sufficient protection of the conductive regions of the EISCAP from the electrolyte solution. At the same time, the results achieved with EISCAPs are fully transferable to other EG-FEDs, thereby circumventing the need for fabrication of complicated transistor structures. At present, a lot of single EISCAP sensors modified with particular recognition elements have been developed and successfully proved for the detection of pH [16], concentration of ions [17], enzyme-substrate reactions [18][19][20][21], charged biomolecules (nucleic acids, proteins, biomarkers, nanoparticle/molecule hybrids) [22][23][24][25][26][27][28][29], plant virus particles [30], as well as for realizing biomolecular logic gates [31][32][33]. For recent progress in research and development of chemical sensors and biosensors based on EISCAPs, see [15]. advantages over devices for single-analyte detection, such as reduced assay time and sample volume, reduced costs and high throughput. The electrolyte-insulator-semiconductor capacitor (EISCAP) belongs to the family of EG-FEDs and represents a biochemically sensitive capacitor [15]. In contrast to ISFETs (ion-sensitive field-effect transistor) or Si nanowire transistors, EISCAPs have a simple structure (see Figure 1a) and are easy and low-cost in fabrication; typical preparation steps do not require photolithographic patterning, and the implementation of a simple O-ring provides sufficient protection of the conductive regions of the EISCAP from the electrolyte solution. At the same time, the results achieved with EISCAPs are fully transferable to other EG-FEDs, thereby circumventing the need for fabrication of complicated transistor structures. At present, a lot of single EISCAP sensors modified with particular recognition elements have been developed and successfully proved for the detection of pH [16], concentration of ions [17], enzyme-substrate reactions [18][19][20][21], charged biomolecules (nucleic acids, proteins, biomarkers, nanoparticle/molecule hybrids) [22][23][24][25][26][27][28][29], plant virus particles [30], as well as for realizing biomolecular logic gates [31][32][33]. For recent progress in research and development of chemical sensors and biosensors based on EISCAPs, see [15].  [15], open access publication under CC BY license); (b) layout of an EISCAP sensor array fabricated on a Si wafer anodically bonded to the glass substrate; (c) schematic of a chip combining a 2 × 2 array of nanoplate EISCAPs prepared on a SOI substrate (reproduced from [23] with permission from John Wiley and Sons); (d) design of an array of EISCAPs separated via the electrolyte reservoirs fabricated on the gate surface (schematically). RE: reference electrode, VG: gate voltage, Ab: antibody, ssDNA: single-strand deoxyribonucleic acid.
In spite of successful experiments with single EISCAP sensors, however, the on-chip integration of multiple EISCAPs for multiplexed detection of multiple target analytes seems to be problematic, challenging the fabrication of electrically isolated, individually addressable capacitive structures: EISCAPs prepared on the same Si chip will stay interconnected via the common Si substrate. This may result in an unwanted cross-talk between the different EISCAPs in the array, thereby limiting the possibility to realize onchip integrated multisensor systems. Only a few studies addressed this task in the literature. For example, Taing realized an EISCAP sensor array fabricated on a Si wafer that is anodically bonded to a glass substrate [34]. To obtain separate electrically decoupled EISCAPs, the Si wafer was diced by means of a saw cutter and, subsequently, the edges of the separated EISCAP chips were protected from contact with solution using a Figure 1. (a) Schematic structure of a conventional single EISCAP biochemical sensor with different receptor functionalities (reproduced from [15], open access publication under CC BY license); (b) layout of an EISCAP sensor array fabricated on a Si wafer anodically bonded to the glass substrate; (c) schematic of a chip combining a 2 × 2 array of nanoplate EISCAPs prepared on a SOI substrate (reproduced from [23] with permission from John Wiley and Sons); (d) design of an array of EISCAPs separated via the electrolyte reservoirs fabricated on the gate surface (schematically). RE: reference electrode, V G : gate voltage, Ab: antibody, ssDNA: single-strand deoxyribonucleic acid.
In spite of successful experiments with single EISCAP sensors, however, the on-chip integration of multiple EISCAPs for multiplexed detection of multiple target analytes seems to be problematic, challenging the fabrication of electrically isolated, individually addressable capacitive structures: EISCAPs prepared on the same Si chip will stay interconnected via the common Si substrate. This may result in an unwanted cross-talk between the different EISCAPs in the array, thereby limiting the possibility to realize on-chip integrated multisensor systems. Only a few studies addressed this task in the literature. For example, Taing realized an EISCAP sensor array fabricated on a Si wafer that is anodically bonded to a glass substrate [34]. To obtain separate electrically decoupled EISCAPs, the Si wafer was diced by means of a saw cutter and, subsequently, the edges of the separated EISCAP chips were protected from contact with solution using a photoresist layer as schematically shown in Figure 1b. Another approach was proposed in [23], where an array of individually addressable nanoplate EISCAPs for chemical/biological sensing was developed using a SOI (silicon-on-insulator) wafer ( Figure 1c). The nanoplate EISCAPs were prepared on a thin top Si layer (two photolithographic steps were needed). For isolation of the individual nanoplate capacitors, the top Si layer was anisotropically etched using the patterned top SiO 2 layer as a mask. However, due to the large series lateral resistance of the top nanoplate Si, the frequency-dependent C-V curves of the nanoplate EISCAPs were deformed; they significantly differed from typical C-V plots of conventional EISCAPs [35]. Finally, a 2 × 2 array of on-chip integrated EISCAPs was demonstrated in [36], where the gate area of each sensor was separated by means of fabrication of individual electrolyte reservoirs, schematically illustrated in Figure 1d. Each EISCAP was addressed through an individual Au pseudo-reference electrode integrated onto the chip, which induced a large drift and instable sensor signal.
The above discussed examples demonstrate the possibility of realization of on-chip integrated EISCAPs. However, the price to be paid was the loss of the substantial advantages of EISCAP devices-their simple layout, as well as easy and cost-efficient preparation. In this work, we present a new and simple design, as well as the operational setup for an array of on-chip integrated, individually electrically addressable EISCAPs with a so-called control gate (CG) (further referred to as CG-EISCAP) as an alternative transducer structure for the multiplexed (quasi)simultaneous detection of multiple analytes without cross-talk effect between the individual sensors. Figure 2 shows the schematic structure of the new designed sensor chip for detecting of multiple analytes, exemplarily combining three individual electrically addressable CG-EISCAPs (CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3). In comparison to conventional EISCAPs, which are based on an electrolyte-insulator-semiconductor system, the new designed CG-EISCAPs are composed of an electrolyte-insulator-metal-insulatorsemiconductor structure. Here, the patterned metal layer (e.g., Au, Al) between the two insulators (insulator-1 and insulator-2) plays the role of the particular CG, in addition to the sensing gate (SG) using the common reference electrode (RE), similar to CMOS (complementary metal-oxide-semiconductor) floating-and programmable-gate ISFETs [37,38]. In order to protect the CG from contact with solution, it is covered with the top insulator-2 (e.g., Al 2 O 3 , Ta 2 O 5 ) or stacked insulators (e.g., SiO 2 -Si 3 N 4 ), which may also serve as a biochemical sensing layer (e.g., being pH-sensitive). In addition, the surface areas (spots) of insulator-2 above the CGs can be modified with various recognition elements (ionophores, enzymes, antibodies, nucleic acids, etc.), thereby making the CG-EISCAP chip sensitive to multiple analytes. Both insulator layers are assumed to be ideal, that is, no current passes through the insulator. For the measurement, the RE (e.g., a conventional Ag/AgCl RE) should provide a stable potential independent of pH or concentration of the analyte solution. The distance between the metal CGs should be sufficiently small to decrease parasitic capacitances associated with the surface areas between the sensors uncovered with the metal CG layer. Conversely, this distance should be sufficiently large to prevent overlapping of the depletion regions in the semiconductor due to the fringing effect and, thereby, practically eliminate possible cross-talk effects between the on-chip integrated CG-EISCAPs.

Design of On-Chip Integrated, Individually Addressable CG-EISCAPs
The CG-EISCAP represents a dual-gate device combining SG and CG, which are coupled with a common floating gate (FG). Thus, the FG potential (V FG ) can be modulated by either SG or CG. CG has a multi-purpose function and is connected with the multiplexer by three positions (floating "F", short-circuited "SC" and capacitively-coupled "CC"), which enables an activation or deactivation of the particular CG-EISCAP. In contrast to conventional EISCAPs, the proposed design allows independent biasing and tuning of the operating point of each CG-EISCAP sensor in the desired region of the capacitance-voltage (C-V) curve (accumulation, depletion or inversion) by means of applying an additional voltage on the respective CG. This way, possible device-to-device differences in the flat-band voltage of various CG-EISCAPs caused from technological factors (e.g., inhomogeneously distributed trapped charges on the floating gate or non-uniform thickness of the gate insulator) can be compensated, too. In addition, both typical characterization modes of EISCAPs, namely the C-V curve and the ConCap (constant-capacitance) mode response can be recorded for each sensor separately in two ways: by means of applying an AC (alternating current) voltage (a) between the RE and the rear-side contact (as for conventional EISCAP sensors) or (b) between the CG and the rear-side contact. Finally, beside the field-effect measurement setup, the proposed structure can also be used as an impedimetric sensor or as capacitively-coupled contactless electrolyte-conductivity detection (so-called C 4 D [39]) sensor. The CG-EISCAP represents a dual-gate device combining SG and CG, which are coupled with a common floating gate (FG). Thus, the FG potential (VFG) can be modulated by either SG or CG. CG has a multi-purpose function and is connected with the multiplexer by three positions (floating "F", short-circuited "SC" and capacitively-coupled "CC"), which enables an activation or deactivation of the particular CG-EISCAP. In contrast to conventional EISCAPs, the proposed design allows independent biasing and tuning of the operating point of each CG-EISCAP sensor in the desired region of the capacitance-voltage (C-V) curve (accumulation, depletion or inversion) by means of applying an additional voltage on the respective CG. This way, possible device-to-device differences in the flat-band voltage of various CG-EISCAPs caused from technological factors (e.g., inhomogeneously distributed trapped charges on the floating gate or non-uniform thickness of the gate insulator) can be compensated, too. In addition, both typical characterization modes of EISCAPs, namely the C-V curve and the ConCap (constant-capacitance) mode response can be recorded for each sensor separately in two ways: by means of applying an AC (alternating current) voltage (a) between the RE and the rear-side contact (as for conventional EISCAP sensors) or (b) between the CG and the rear-side contact. Finally, beside the field-effect measurement setup, the proposed structure can also be used as an impedimetric sensor or as capacitively-coupled contactless electrolyte-conductivity detection (so-called C 4 D [39]) sensor.
It is worth to mention, that in contrast to on-chip integrated EISCAP arrays reported in [36], our design uses one common RE for all sensors in the array. On the other hand, a conventional Si wafer is utilized instead of a costly SOI [23,35] or an anodically bonded Si wafer [34]. In addition, the fabrication of CG-EISCAPs is easy; it requires only one photolithographic step when depositing the CG layer via a shadow mask or two photolithographic steps in case of structuring of the CG layer by lift-off process or etching. In some embodiments, the technological process steps could also include front-side contacting to the Si instead of rear-side contacting or the preparation of an on-chip integrated common pseudo-RE. Schematic structure of the designed sensor chip for detecting multiple analytes, combining an array of three individually addressable CG-EISCAPs and measurement setup. RE: reference electrode (sensing gate, SG); V G : gate voltage; V AC : alternating current voltage; Al: rear-side contact; CG1, CG2 and CG3: control gates; position "F": floating; position "SC": short-circuited; position "CC": capacitively-coupled; C CG1 and C CG3 : control gate capacitances; V CG1 and V CG3 : voltage applied to the control gate; R1 and R2: receptors; T1 and T2: target species to be detected; ϕ 1 , ϕ 2 and ϕ 3 : potential at the insulator-2/electrolyte interface related to CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3, respectively. For better visibility, the multiplexer for CG-EISCAP-2 is not shown.
It is worth to mention, that in contrast to on-chip integrated EISCAP arrays reported in [36], our design uses one common RE for all sensors in the array. On the other hand, a conventional Si wafer is utilized instead of a costly SOI [23,35] or an anodically bonded Si wafer [34]. In addition, the fabrication of CG-EISCAPs is easy; it requires only one photolithographic step when depositing the CG layer via a shadow mask or two photolithographic steps in case of structuring of the CG layer by lift-off process or etching. In some embodiments, the technological process steps could also include front-side contacting to the Si instead of rear-side contacting or the preparation of an on-chip integrated common pseudo-RE.

Modelling of On-Chip Integrated, Individually Addressable CG-EISCAPs
For the development of the electrical equivalent circuit and modelling of the CG-EISCAP chip in different setups, let us assume that CG-EISCAP-1 in Figure 2 is modified with receptor R1 for the detection of target analyte T1, while CG-EISCAP-2 is modified with receptor R2 for the detection of target analyte T2. CG-EISCAP-3 is unmodified and serves for pH control of the analyte solution or as reference sensor. Since generally EG-FEDs (particularly EISCAPs) are charge-sensitive devices, any specific electrochemical interaction between the immobilized receptor and target analyte (e.g., affinity reaction, DNA hybridization, local pH changes due to enzymatic reactions, etc.) that occurs at or immediately near the gate surface (within the so-called Debye length from the surface) will induce changes in the surface charge/potential of gate insulator-2 that will consequently modulate the overall capacitance of the EISCAP sensor (see e.g., recent review [15]).
The complete electrical equivalent circuit of the CG-EISCAP chip is complex and involves components associated with the resistance of the RE (R RE ), resistance of the bulk solution, double-layer capacitance at the electrolyte/insulator-2 interface, capacitances of insulator-1 and insulator-2, the space-charge capacitance in the semiconductor, and resistances of the bulk semiconductor and the metal-semiconductor rear-side contact. However, as discussed in [15,40,41], for typical gate insulator films used for EISCAPs (e.g., SiO 2 , Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 ) and their usual thickness range (10-100 nm) as well as appropriate experimental conditions (ionic strength of the solution >0.1 mM; measurement frequencies of <1 kHz), the interferences from several components, such as double-layer capacitance and electrolyte resistance, are negligible. In addition, the resistances of bulk Si and Al-Si rear-side contact are much smaller than R RE and therefore, can be also neglected. Hence, the equivalent circuit of the individual CG-EISCAP sensor with a floating CG can be simplified as a series connection of capacitances of insulator-2, insulator-1 and the variable space-charge capacitance of the semiconductor. Figure 3 represents the simplified equivalent circuit of the chip composed of three CG-EISCAPs. Here, C i1 , C i2 and C nsc (n = 1, 2, 3) are the capacitances of insulator-1, insulator-2 and space-charge region in the semiconductor associated with CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3, respectively. In this work, the surface-sensing areas (spots) of all three CG-EISCAPs are assumed to be equal and all capacitances are defined per unit surface area: where ε 1 , ε 2 and d 1 , d 2 are permittivities and thicknesses of insulator-1 and insulator-2, respectively. The space-charge capacitances of CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3 are given as: C 1sc = ε s /w 1 , C 2sc = ε s /w 2 , C 3sc = ε s /w 3 , respectively, where ε s is the permittivity of the semiconductor, and w 1 , w 2 and w 3 are the widths of the corresponding depletion regions. The width of the depletion region and consequently, the space-charge capacitance of each sensor will be determinedamong others-by the applied voltage on the gate (in this case, SG and/or CG) and by the respective electrolyte/insulator-2 interfacial potentials. We assume that the surface areas of insulator-1 covered with metal CGs are much larger than that of metal-free areas. Therefore, the parasitic capacitance associated with the surface areas between the individual CG-EISCAPs (uncovered with metal CG layer) has not been included in the equivalent circuit.
DNA hybridization, local pH changes due to enzymatic reactions, etc.) that occurs at or immediately near the gate surface (within the so-called Debye length from the surface) will induce changes in the surface charge/potential of gate insulator-2 that will consequently modulate the overall capacitance of the EISCAP sensor (see e.g., recent review [15]).
The complete electrical equivalent circuit of the CG-EISCAP chip is complex and involves components associated with the resistance of the RE (RRE), resistance of the bulk solution, double-layer capacitance at the electrolyte/insulator-2 interface, capacitances of insulator-1 and insulator-2, the space-charge capacitance in the semiconductor, and resistances of the bulk semiconductor and the metal-semiconductor rear-side contact. However, as discussed in [15,40,41], for typical gate insulator films used for EISCAPs (e.g., SiO2, Si3N4, Al2O3, Ta2O5) and their usual thickness range (10-100 nm) as well as appropriate experimental conditions (ionic strength of the solution >0.1 mM; measurement frequencies of <1 kHz), the interferences from several components, such as double-layer capacitance and electrolyte resistance, are negligible. In addition, the resistances of bulk Si and Al-Si rear-side contact are much smaller than RRE and therefore, can be also neglected. Hence, the equivalent circuit of the individual CG-EISCAP sensor with a floating CG can be simplified as a series connection of capacitances of insulator-2, insulator-1 and the variable space-charge capacitance of the semiconductor. Figure 3 represents the simplified equivalent circuit of the chip composed of three CG-EISCAPs. Here, Ci1, Ci2 and Cnsc (n = 1, 2, 3) are the capacitances of insulator-1, insulator-2 and space-charge region in the semiconductor associated with CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3, respectively. In this work, the surface-sensing areas (spots) of all three CG-EISCAPs are assumed to be equal and all capacitances are defined per unit surface area: Ci1 = ε1/d1, Ci2 = ε2/d2, where ε1, ε2 and d1, d2 are permittivities and thicknesses of insulator-1 and insulator-2, respectively. The space-charge capacitances of CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3 are given as: C1sc = εs/w1, C2sc = εs/w2, C3sc = εs/w3, respectively, where εs is the permittivity of the semiconductor, and w1, w2 and w3 are the widths of the corresponding depletion regions. The width of the depletion region and consequently, the space-charge capacitance of each sensor will be determined-among othersby the applied voltage on the gate (in this case, SG and/or CG) and by the respective electrolyte/insulator-2 interfacial potentials. We assume that the surface areas of insulator-1 covered with metal CGs are much larger than that of metal-free areas. Therefore, the parasitic capacitance associated with the surface areas between the individual CG-EISCAPs (uncovered with metal CG layer) has not been included in the equivalent circuit.  The equivalent capacitance of the chip (C eq ) is determined as: where C 1 , C 2 , and C 3 are the overall capacitances of CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3, respectively, which are determined by the combination of the capacitances C i1 , C i2 and C nsc in series: As can be seen in Figure 3, the individual CG-EISCAPs in the array are still interconnected via the common Si substrate, which may result in an unwanted cross-talk between the on-chip integrated sensors (see Introduction). For example, if the chip is exposed to the solution containing both T1 and T2 target analytes, the interaction of target T1 with the immobilized receptor R1 will modulate the interfacial potential (ϕ 1 ) as well as the space-charge (C 1sc ) and overall (C 1 ) capacitance of CG-EISCAP-1. Analogously, the interaction of target T2 with the immobilized receptor R2 and/or possible pH changes will modulate the overall capacitances of CG-EISCAP-2 (C 2 ) and CG-EISCAP-3 (C 3 ), respectively, all resulting in a change of the equivalent capacitance, C eq , of the chip. As a consequence, such a chip is unable to selectively distinguish between particular target analytes in a multicomponent solution. However, the existence of CGs enables addressable activation/deactivation of individual CG-EISCAPs by switching the CG of each sensor in various setups, such as floating/short-circuited CG or floating/capacitively-coupled CG, which are discussed below. This feature of an addressable activation or deactivation of on-chip integrated individual CG-EISCAPs by simple electrical switching the respective CG (instead of fabricating an array of separate EISCAPs) makes the new design capable for multiplexed operation. Detection of multiple analytes is possible, eliminating cross-talk effects between the sensors in the array. Figure 4 shows the electrical equivalent circuit and measurement setup of the chip with floating/short-circuited CG. The chip is exposed to the solution containing multiple target analytes (exemplarily, T1 and T2) and the gate voltage V G is applied to the structure via the RE to set the working points of all three sensors in the depletion region.
The equivalent capacitance of the chip (Ceq) is determined as: where C1, C2, and C3 are the overall capacitances of CG-EISCAP-1, CG-EISCAP-2 and CG-EISCAP-3, respectively, which are determined by the combination of the capacitances Ci1, Ci2 and Cnsc in series: As can be seen in Figure 3, the individual CG-EISCAPs in the array are still interconnected via the common Si substrate, which may result in an unwanted cross-talk between the on-chip integrated sensors (see Introduction). For example, if the chip is exposed to the solution containing both T1 and T2 target analytes, the interaction of target T1 with the immobilized receptor R1 will modulate the interfacial potential (ϕ1) as well as the space-charge (C1sc) and overall (C1) capacitance of CG-EISCAP-1. Analogously, the interaction of target T2 with the immobilized receptor R2 and/or possible pH changes will modulate the overall capacitances of CG-EISCAP-2 (C2) and CG-EISCAP-3 (C3), respectively, all resulting in a change of the equivalent capacitance, Ceq, of the chip. As a consequence, such a chip is unable to selectively distinguish between particular target analytes in a multicomponent solution. However, the existence of CGs enables addressable activation/deactivation of individual CG-EISCAPs by switching the CG of each sensor in various setups, such as floating/short-circuited CG or floating/capacitively-coupled CG, which are discussed below. This feature of an addressable activation or deactivation of on-chip integrated individual CG-EISCAPs by simple electrical switching the respective CG (instead of fabricating an array of separate EISCAPs) makes the new design capable for multiplexed operation. Detection of multiple analytes is possible, eliminating crosstalk effects between the sensors in the array. Figure 4 shows the electrical equivalent circuit and measurement setup of the chip with floating/short-circuited CG. The chip is exposed to the solution containing multiple target analytes (exemplarily, T1 and T2) and the gate voltage VG is applied to the structure via the RE to set the working points of all three sensors in the depletion region. To detect target analyte T1 with the CG-EISCAP-1, CG1 is kept floating (CG1 is switched to position "F" of the multiplexer), while CG2 and CG3 should be short-circuited (switched to position "SC", Figure 2) to exclude an impact of possible gate-surface potential changes of CG-EISCAP-2 and CG-EISCAP-3 on the total capacitance of the chip and, therefore, on the output signal. FG1 transfers the signal from the electrolyte/insulator-2 interface to the semiconductor in an electrostatic way: the floating gate potential of CG-EISCAP-1, V FG1 , will follow the changes in both the gate voltage (V G ) and the interfacial potential (ϕ 1 ). The term ϕ 1 can be represented as ϕ 1 = ϕ 01 ± ∆ϕ 1 , where ϕ 01 is the potential at the insulator-2/electrolyte interface before the biochemical interaction of target T1 with the immobilized receptor R1 and ∆ϕ 1 is the potential change induced via the biochemical interaction. The expression for V FG1 of CG-EISCAP-1 can be obtained using the capacitive voltage divider model:

Setup with Floating/Short-Circuited CG
where V G1-eff is the effective gate voltage and is given by [42,43]: Here, V op is the overall potential drop through the RE/electrolyte/insulator system, E ref is the potential of the RE relative to vacuum, χ sol is the surface-dipole potential of the solvent, W m is the metal electron work function, q is the elementary charge (1.6 × 10 −19 C) and C t1 is the sum of all capacitances coupled to the floating node with: The simplified equivalent circuit corresponding to the floating/short-circuited CG setup is shown in Figure 4 (right), where the equivalent capacitance (C eq ) of the chip is determined as: In general, in the presence of a series resistance (e.g., resistance of the RE, R RE ), the measured capacitance (C m ) will be given by [35,44,45]: where f is the measurement frequency. C m will be equal to C eq , if (2πfR RE C eq ) 2 << 1. Otherwise, C m will be affected by the series resistance, resulting in frequency-dependent C-V curves and a much smaller C m than the real capacitance of the system.
In Equation (8), all terms are constant except C 1sc , which at a constant V G presumably will depend on the T1 concentration in solution. Thus, the chip will detect explicitly potential changes on the gate surface of CG-EISCAP-1 resulting from the interaction of T1 with R1. Although, the gate surface potential of CG-EISCAP-2 will be also altered due to the interaction of T2 with R2, this has no impact on the results of the detection of T1 with CG-EISCAP-1 (because it is short-circuited). Consequently, there are no cross-talk effects between the individual CG-EISCAP sensors in the array. Similarly, for the detection of the target analyte T2 with CG-EISCAP-2, CG2 should be held as floating, while CG1 and CG3 should be short-circuited. Finally, for the pH control with the CG-EISCAP-3, CG1 and CG2 should be short-circuited, while CG3 should be switched to position "F".
To compare the shape of the expected C-V curve and the potential sensitivity of the CG-EISCAP chip and the single EISCAP (without control gate), let us determine C eq in the accumulation, depletion and inversion region, respectively. In the accumulation region (V G < 0), C 1sc >> C i1 and C 1sc >> C i2 . Then, the equivalent capacitance of the chip in the accumulation region (C eq-acc ) can be derived from Equation (8) as: By strong inversion, the depletion-layer width reaches a maximum, w m [46]: where k is the Boltzmann's constant, T is the temperature, N A is the density of ionized acceptors (p-Si) and n i is the electron density in the intrinsic semiconductor. The corresponding high-frequency capacitance of EISCAP-1 in the inversion range (C 1inv ) reaches its minimum. The equivalent capacitance of the chip in the inversion range (C eq-inv ) can be obtained from Equation (8) by replacing C 1sc with C 1inv = ε s /w m : Typically, C 1inv << C i1 and C 1inv << C i2 , hence, Equation (12) can be simplified as For biochemical sensor applications, more interestingly in the depletion region, the space-charge capacitance in the semiconductor and, therefore, the overall capacitance of the chip depends on both the gate voltage and the interfacial potential. In Equation (8) for C eq , the only variable term is the space-charge capacitance (C 1sc ), which can be deduced from the expression for the depletion capacitance of a MOS (metal-oxide-semiconductor) capacitor (C scMOS ) [46]: For this, the flat-band voltage V FB (the externally applied voltage needed to make energy bands in the semiconductor flat from bulk to the surface and the net charge density in the semiconductor to zero) and the gate-insulator capacitance (C i ) of the MOS structure are replaced by the flat-band voltage (V fb1 ) and series capacitances C i1 and C i2 (C i = C i1 C i2 /(C i1 +C i2 )) of the CG-EISCAP-1, respectively: Generally, the flat-band voltage of the EISCAP is given by [47]: where W s is the silicon electron work function, and Q i and Q ss are the charges located in the oxide and the surface and interface states, respectively. By assuming that Q i and Q ss , and the charge at the floating gate are zero and grouping analyte-concentration independent potentials in V ip = E ref + χ sol − W s /q, the expression (16) for the flat-band voltage can be simplified as: By substituting expressions (15) and (17) into Equation (8), we obtain the following equation for the equivalent capacitance of the chip in the depletion region, C eq-dep : At a constant V G , all terms in Equation (18) can be considered as constant except for ϕ 1 , which is analyte-concentration dependent. The combination of Equations (10), (12) and (18) gives the complete description of the C-V curve. The sensitivity (S ϕ ) of the chip to surface potential changes induced by the receptor-target analyte interaction onto the CG-EISCAP-1 surface can be obtained by differentiation of C eq-dep with respect to ϕ 1 : The analysis of Equations (10), (13), (18) and (19) reveals that the C-V curve of the chip will have the same shape as for a single conventional EISCAP sensor (without control gate) with the same stacked double-gate insulators and gate surface area as the CG-EISCAP-1, but will be shifted parallel along the capacitance axis with the amount of 2C i2 , as shown in Figure 5. The overall capacitance and output signals of other CG-EISCAPs will remain unchanged. The chip combining an array of CG-EISCAPs will respond in exactly the same manner as the single conventional EISCAP sensor. Therefore, no loss in sensitivity of the CG-EISCAP chip to surface potential changes in comparison with a single EISCAP sensor will be observed. Similar expressions can be obtained in the case of measurements with the CG-EISCAP-2 and the CG-EISCAP-3 sensors. Equations (18) and (19) describe the equivalent capacitance in the depletion region and potential sensitivity of the CG-EISCAP chip without defining the origin of the potential generation at the analyte/insulator-2 interface. If the applied gate voltage, V G , is fixed, the only variable component is the interfacial potential ϕ, which is analogous to the effect of applying an additional voltage to the gate. The sensitivity of the chip to analyte concentration variations will be determined by the particular mechanism of the interfacial potential generation (e.g., pH or ion-concentration change, antibody-antigen affinity reaction, DNA hybridization, enzymatic reactions, etc.) and many other experimental factors (e.g., effective charge of the target analyte, distance of bound analyte charge from the gate surface, density of receptors, buffer capacity and ionic strength of the sample, and so on). Therefore, corresponding expressions for the analyte sensitivity, derived from other kinds of EG-FEDs, are fully transferable to CG-EISCAPs. For example, the pH sensitivity of such CG-EISCAPs can be determined as changes of the interfacial potential (ϕ) in response to a change in the bulk pH [48]: with α = 1 (2.3 kTC DL /q 2 β int ) + 1 (21) Here, α is a dimensionless sensitivity parameter, varying between 0 and 1, β int is the surface intrinsic buffer capacity that characterizes the ability of the oxide surface to release or bind protons, and C DL is the double-layer capacitance. Figure 6 shows the equivalent circuit and measurement setup of the chip with floating/capacitively-coupled CGs. First, the CGs of all three sensors are floating (switched to position "F", Figure 2) and the working points of all three sensors are fixed in the depletion region by applying the gate voltage, V G , via the RE. To detect target analyte T1 with the CG-EISCAP-1, CG1 is kept floating, while CG2 and CG3 are capacitively coupled (switched to position "CC", Figure 2) to the floating gates of FG2 and FG3 via external (or technologically on-chip integrated) capacitances C CG2 and C CG3 , respectively. In this setup, in addition to SG, the capacitively coupled CG2 and CG3 can also be used to modulate the space-charge capacitances of the CG-EISCAP-2 and the CG-EISCAP-3. The floating gate voltage of the CG-EISCAP-2 (V FG2 ) or the CG-EISCAP-3 (V FG3 ) is established by a weighted sum of the two input voltages, namely, the effective gate voltage (V G2-eff or V G3-eff ) and the control gate voltage (V CG2 or V CG3 ). The expressions for V FG2 and V FG3 can be obtained by taking into account that each weight is determined by the capacitance of its input normalized by the total capacitance (C t2 or C t3 ) coupled to the floating node:
Sensors 2021, 21, x FOR PEER REVIEW 10 of 18  Figure 6 shows the equivalent circuit and measurement setup of the chip with floating/capacitively-coupled CGs. First, the CGs of all three sensors are floating (switched to position "F", Figure 2) and the working points of all three sensors are fixed in the depletion region by applying the gate voltage, VG, via the RE. To detect target analyte T1 with the CG-EISCAP-1, CG1 is kept floating, while CG2 and CG3 are capacitively coupled (switched to position "CC", Figure 2) to the floating gates of FG2 and FG3 via external (or technologically on-chip integrated) capacitances CCG2 and CCG3, respectively. In this setup, in addition to SG, the capacitively coupled CG2 and CG3 can also be used to modulate the space-charge capacitances of the CG-EISCAP-2 and the CG-EISCAP-3. The floating gate voltage of the CG-EISCAP-2 (VFG2) or the CG-EISCAP-3 (VFG3) is established by a weighted sum of the two input voltages, namely, the effective gate voltage (VG2-eff or VG3-eff) and the control gate voltage (VCG2 or VCG3). The expressions for VFG2 and VFG3 can be obtained by taking into account that each weight is determined by the capacitance of its input normalized by the total capacitance (Ct2 or Ct3) coupled to the floating node: To exclude an impact of possible gate-surface potential changes of the CG-EISCAP-2 and the CG-EISCAP-3 on the total capacitance of the chip, the CG-EISCAP-2 and the CG-EISCAP-3 have to be deactivated by switching to position "CC" (Figure 6) and applying a voltage on CG2 and CG3. The CG-EISCAP-2 and the CG-EISCAP-3 can be deactivated by shifting the operation point either to the accumulation or strong inversion state, where the overall capacitance of these sensors is independent of the gate voltage (V G ) or respective interfacial potentials (ϕ 2 , ϕ 3 ). In the following, exemplarily, the expressions for the equivalent capacitance of the CG-EISCAP chip are obtained by assuming that the CG-EISCAP-2 and the CG-EISCAP-3 are deactivated by shifting their operation point in the strong inversion region. where VG2-eff and VG3-eff are determined by Equation (6) by replacing ϕ1 with ϕ2 or ϕ3, respectively. To exclude an impact of possible gate-surface potential changes of the CG-EISCAP-2 and the CG-EISCAP-3 on the total capacitance of the chip, the CG-EISCAP-2 and the CG-EISCAP-3 have to be deactivated by switching to position "CC" (Figure 6) and applying a voltage on CG2 and CG3. The CG-EISCAP-2 and the CG-EISCAP-3 can be deactivated by shifting the operation point either to the accumulation or strong inversion state, where the overall capacitance of these sensors is independent of the gate voltage (VG) or respective interfacial potentials (ϕ2, ϕ3). In the following, exemplarily, the expressions for the equivalent capacitance of the CG-EISCAP chip are obtained by assuming that the CG-EISCAP-2 and the CG-EISCAP-3 are deactivated by shifting their operation point in the strong inversion region.

Setup with Floating/Capacitively-Coupled CGs
By assuming that CCG2 = CCG3 = CCG and C2sc = C3sc = Cinv, the overall capacitance of the CG-EISCAP-2 (C2) or the CG-EISCAP-3 (C3) in the inversion region is given by: Typically, Cinv << Ci1, hence, Equation (26) can be simplified as: The equivalent capacitance of the chip in the accumulation, inversion and depletion regions can be derived from Equations (10), (13) and (18)  By assuming that C CG2 = C CG3 = C CG and C 2sc = C 3sc = C inv , the overall capacitance of the CG-EISCAP-2 (C 2 ) or the CG-EISCAP-3 (C 3 ) in the inversion region is given by: Typically, C inv << C i1 , hence, Equation (26) can be simplified as: The equivalent capacitance of the chip in the accumulation, inversion and depletion regions can be derived from Equations (10), (13) and (18) by replacing C i2 by C 2 , Equation (27): Note, since in Equation (30) the inversion capacitance, C inv , of the high-frequency C-V curve is independent of the gate voltage or interfacial potentials, the sensitivity (S ϕ ) of the chip using the setup with floating/capacitively-coupled CG will be defined by the same Equation (19) as for the setup with floating/short-circuited CG. Thus, the chip combining an array of CG-EISCAPs will respond only to surface potential changes induced by the receptor-target analyte interactions occurring onto the surface of the CG-EISCAP-1 and in exactly the same manner as the single conventional EISCAP sensor. However, the C-V curve will be shifted parallel along the capacitance axis with the amount of 2C 2 (Equation (27)), as shown in Figure 5 (black curve). Similar expressions can be obtained in the case of detection with the CG-EISCAP-2 (CG2 is floating, while CG1 and CG3 are capacitively coupled) or the CG-EISCAP-3 (CG3 is floating and CG1 and CG2 are capacitively-coupled).
The C-V curves of the CG-EISCAP chip in floating/short-circuited and floating/capacitivelycoupled setups were calculated for the accumulation, inversion and depletion regions using Equations (10), (12), (18), (28), (29) and (30), respectively. The C-V curves of the single EISCAP were simulated using Equations (10), (12) and (18) without the second term (2C i2 ). To depict the course of the equivalent capacitance of the CG-EISCAP chip and the single EISCAP, also in the transition range from depletion to accumulation region, all C-V curves in Figure 7 were extrapolated (dotted curves).
As predicted in Section 3.1, these C-V curves have the same shape, independent of the CG-EISCAP chip or the single EISCAP setup. However, in comparison with the C-V curves of the single EISCAP, the C-V curves of the CG-EISCAP chip are shifted along the capacitance axis in the direction of larger capacitance values due to the additional parallel constant capacitances of the other sensors in the array. The amount of these shifts is defined by the second term in Equations (10) and (28) (see also Figure 5). As expected, at a constant C eq , the C-V curves are also shifted along the voltage axis. The direction and amount of these shifts (∆V G , see top C-V curves in Figure 7) depend on the sign and amplitude of additional potential changes induced by any biochemical interaction on the sensor surface: ∆V G = ±∆ϕ 1 . In case of a p-type EISCAP, an additional positive potential generated by the biochemical interactions on the EISCAP surface will lead to an increase in the width of the depletion layer (correspondingly, the depletion capacitance decreases). As a consequence, the overall capacitance of the CG-EISCAP chip or the single EISCAP will also decrease, resulting in a shift of the C-V curve towards more negative (less positive) gate voltages (Figure 7, blue curve).
Conversely, an additional negative potential generated by the biochemical interaction on the EISCAP surface will decrease the width of the depletion layer in the Si and consequently, increase the depletion capacitance. The overall capacitance of the CG-EISCAP chip or the single EISCAP will also increase, resulting in a shift of the C-V curve in the direction of more positive (less negative) gate voltages (Figure 7, red curve). Such shifts of the C-V curve along the voltage axis upon biochemical interaction was observed in many experiments on conventional single EISCAP-based pH sensors or biosensors (e.g., [17,19,20,24,26]). Often, these sensors work in the ConCap mode, by which gatesurface potential shifts induced upon biochemical interactions can directly be determined from the dynamic sensor response (see [15] and references therein). Figure 8 shows the calculated curves of the sensitivity of the CG-EISCAP chip on the gate voltage (a), the thickness of the insulator-1 and insulator-2 (b) and the doping concentration (c). With increasing gate voltage, the sensitivity of the CG-EISCAP chip to surface potential changes induced by the receptor-target analyte interaction is decreased. Maximum sensitivity will be achieved at the inflection point of the C-V curve, which corresponds to the flat-band condition as it has been discussed in [49]. In the transition range from depletion to accumulation region (i.e., at gate voltages of V G < V fb1 ), the sensitivity of the CG-EISCAP chip will again decrease (not shown), similar to conventional EISCAPs. As expected, the calculations, depicted in Figure 8b, show that the sensitivity is increased with decreasing the layer thicknesses of both insulator-1 and insulator-2. This is due to the increase in the C eq-acc /C eq-inv ratio and the steepness of the C-V curve in the depletion region. The C-V curves of the CG-EISCAP chip in floating/short-circuited and floating/capacitively-coupled setups were calculated for the accumulation, inversion and depletion Finally, Figure 8c illustrates the dependence of the sensitivity on the doping concentration (N A ) at different thicknesses of insulator-1 (d 1 ). The sensitivity is increased with increasing N A , reaching its maximum value, and is decreased by further increase in N A . Such a course of Sϕ curves may be explained by taking into consideration the ratio: Such a course of S ϕ curves may be explained by taking into consideration the ratio: in Equation (19). If R << 1, S ϕ~NA 1/2 and the sensitivity is increased with increasing the doping concentration. Conversely, if R >> 1, the S ϕ~NA −1 and the sensitivity is decreased with increasing the doping concentration. The maximum sensitivity value and its position along the N A -axis depends on d 1 . At a constant V G and ϕ 1 , with decreasing d 1 , the maximum sensitivity is increased and its position is shifted towards higher N A values.

Conclusions
Multiplexed biochips for multianalyte detection have been increasingly recognized as powerful tools in many fields of application, including point-of-care diagnostics and personalized medicine. In this work, a new design for an array of on-chip integrated, individually electrically addressable CG-EISCAPs for a multiplexed (quasi)simultaneous detection of multiple analytes is presented. In comparison with conventional EISCAPs, CG-EISCAPs have a supplemental control gate in addition to their sensing gate, which enables the activation or deactivation of individual CG-EISCAPs inside the array, thus (practically) eliminating possible cross-talk effects between the sensors.
The new designed CG-EISCAP chip was modelled for two setups (floating/shortcircuited CG and floating/capacitively-coupled CG). To validate the equivalent-circuit model of the CG-EISCAP chip, the capacitance-voltage curves were simulated for different setups and compared with that of a single EISCAP sensor (without CG). The simulation results reveal that the chip combining an array of CG-EISCAPs will respond in exactly the same manner as the single EISCAP sensor, without loss in sensitivity. Additional to the C-V curves, the sensitivity of the CG-EISCAP chip to surface potential changes induced by biochemical reactions was simulated and the impact of different parameters such as the gate voltage, the insulator thickness and the doping concentration on the sensitivity has been discussed.
In conclusion, the results achieved in this work underline a great potential of CG-EISCAPs as an alternative transducer structure for the realization of multiplexed biochips for (quasi)simultaneous detection of multiple analytes without additional process complexity and with numerous possible applications. Although in this work, an array combining three CG-EISCAPs was modelled, the proposed approach may be extended to CG-EISCAP chips consisting of N sensors, as well as to other kinds of EIS-based biochemical sensors (e.g., light-addressable potentiometric sensors [50]). Funding: This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.