An Improved Voltage Clamp Circuit Suitable for Accurate Measurement of the Conduction Loss of Power Electronic Devices

Power electronic devices are essential components of high-capacity industrial converters. Accurate assessment of their power loss, including switching loss and conduction loss, is essential to improving electrothermal stability. To accurately calculate the conduction loss, a drain–source voltage clamp circuit is required to measure the on-state voltage. In this paper, the conventional drain–source voltage clamp circuit based on a transistor is comprehensively investigated by theoretical analysis, simulations, and experiments. It is demonstrated that the anti-parallel diodes and the gate-shunt capacitance of the conventional drain–source voltage clamp circuit have adverse impacts on the accuracy and security of the conduction loss measurement. Based on the above analysis, an improved drain–source voltage clamp circuit, derived from the conventional drain–source voltage clamp circuit, is proposed to solve the above problems. The operational advantages, physical structure, and design guidelines of the improved circuit are fully presented. In addition, to evaluate the influence of component parameters on circuit performance, this article comprehensively extracts three electrical quantities as judgment indicators. Based on the working mechanism of the improved circuit and the indicators mentioned above, general mathematical analysis and derivation are carried out to give guidelines for component selection. Finally, extensive experiments and detailed analyses are presented to validate the effectiveness of the proposed drain–source voltage clamp circuit. Compared with the conventional drain–source voltage clamp circuit, the improved drain–source voltage clamp circuit has higher measurement accuracy and working security when measuring conduction loss, and the proposed component selection method is verified to be reasonable and effective for better utilizing the clamp circuit.


Introduction
High-voltage, large-capacity power electronic conversion equipment dramatically improves the transmission capacity of the flexible AC/DC grid as well as the electric traction control ability [1]. As the voltage withstand ability and switching frequency of power semiconductor devices continue to increase, and the volume continues to decrease, power electronic converters have higher efficiency and power density [2][3][4]. However, converters face reliability challenges. The overheating failure of the internal power electronic devices is one of the main reasons for damage to the converter [5][6][7], and most heat comes from the power loss of power semiconductor devices. Imprecise power loss measurement will lead to the wrong design of the thermal management system (TMS), which will affect the reliability and cause premature failure of the equipment [8,9]. Accurately obtaining the power loss of the device is a crucial prerequisite for determining the thermal solution, which will affect the efficiency, cost, and power density of the entire system. ture, work principle, and drawbacks of the conventional DVCC are analyzed in detail. Then, the schematic and the advantages of the improved DVCC are presented. Furthermore, the influence of the components' parameters on the circuit performance of the improved DVCC is analyzed in Section 3. Here, component selection guidelines are also given. In Section 4, the measurement accuracy and work security improvement of the improved DVCC are verified through simulated and experimental comparisons with the conventional DVCC. Simultaneously, the effectiveness of the selection theory is also investigated and proven. Finally, Section 5 concludes this paper.

Design of the Improved DVCC
Compared with the existing DVCCs, which are mainly applied to the on-state resistance measurement of the DUT, more problems need to be considered when designing a DVCC suitable for conduction loss measurement. After the DUT is turned on, it will go through two typical states, enter the oscillation state (on-oscillation state), and gradually reach steady state (on-steady state). The measurement results of these existing DVCCs can well reflect the on-state voltage v ds_on_ste when the DUT is in the on-steady state. However, when measuring the conduction loss, in addition to the above-mentioned on-steady state voltage, the DVCC must be able to accurately measure the on-state voltage v ds_on_osc when the DUT is in the on-oscillation state. Any error at any stage will cause errors in the calculation of the device conduction loss.
In addition, many common problems need to be avoided in both on-state resistance and conduction loss measurement. First of all, the DVCCs cannot have measurement delays. Once the voltage data lag or lead the current data, errors will occur in the loss integral calculation. Secondly, power electronic devices, such as diodes, metal-oxidesemiconductor field-effect transistors (MOSFET), etc., are often introduced into DVCCs to realize the voltage clamping function. Due to the faster switching speed and higher operating voltage of the DUT, it is easy to make these auxiliary devices out of safe working conditions. Therefore, when designing a DVCC, it is necessary to focus on the security of these auxiliary devices.

The Structure and Working Principle of the Conventional DVCC
The schematic diagram of the conventional DVCC is shown in Figure 1. The auxiliary device MOSFET (M) is used to withstand the high off-state voltage of the DUT, thereby limiting the potential of the voltage measurement point A. The DC voltage supply V cc and the gate resistor R 2 are located at the gate of M, and together with the resistor R 3 , they control the turn-on and turn-off of M. The D and S terminals of the circuit are connected to the drain and source of the DUT, respectively, while the A and B terminals are used to measure output voltage (v out ).

Drawbacks of the Conventional DVCC
In view of the fact that the purpose of the conventional DVCC is to measure the onstate resistance, when it is applied to conduction loss measurement, there are some severe problems, which are further discussed in the following subsections.

Low Measurement Accuracy
To reduce the voltage negative overshoot between A and B when the DUT is turned on, the conventional DVCC connects the diodes D1 and D2 in reverse parallel between the When the DUT is in the off-state, D 3 is broken down, causing the current flowing through R 3 to increase sharply. At this time, the source potential of M rises, and the gatesource voltage v gs_M decreases. When v gs_M is less than the threshold voltage V th_M of M, M is turned off and shares most of the off-state voltage, limiting v out to a small voltage value. When the DUT is turned on, the source potential of M decreases, causing the v gs_M to become higher than V th_M , bringing the M into conduction. As a result, v out is equal to v ds_on .

Drawbacks of the Conventional DVCC
In view of the fact that the purpose of the conventional DVCC is to measure the on-state resistance, when it is applied to conduction loss measurement, there are some severe problems, which are further discussed in the following subsections.

Low Measurement Accuracy
To reduce the voltage negative overshoot between A and B when the DUT is turned on, the conventional DVCC connects the diodes D 1 and D 2 in reverse parallel between the measurement points A and B and utilizes their unidirectional conductivity characteristics to eliminate the voltage overshoot.
Assume that the forward voltage drops of diodes are V D1 and V D2 , respectively. During the on-oscillation state, if v ds_on_osc is greater than −(V D1 + V D2 ), D 1 and D 2 are reversely cut off. Therefore, v out = v ds_on_osc . Once v ds_on_osc is less than −(V D1 + V D2 ), D 1 and D 2 will immediately switch to the forward conduction state, and the output voltage will remain unchanged at −(V D1 + V D2 ), resulting in v out = v ds_on . The two diodes limit the negative voltage overshoot and do not affect the on-state resistance measurement. However, when measuring the conduction loss, the loss during oscillation cannot be ignored [28]. The conventional DVCC cannot measure v ds_on_osc accurately nor can it accurately measure the conduction loss.

Low Working Security
To reduce the current flowing through the DC voltage supply (V cc ) and ensure the safety of V cc , the conventional DVCC shown in Figure 1 has a capacitor C 0 connected in parallel to the gate of M [22]. However, the existence of C 0 seriously affects the work security of auxiliary device M. When the DUT is turned off, the drain-source voltage v ds and the current on R 3 increases sharply, which will cause an instantaneous negative overshoot V gs_M(max) at the gate-source of M. If V gs_M(max) exceeds the gate−source voltage withstand limit of M (V gs_limit ), M will be burned. If negative overshoot V gs_M(max) occurs at time t 0 , the gate−source voltage v gs_M of M will be a negative value in the time interval [t 0 − ∆t, t 0 + ∆t]. According to Figure 1, it can be known from KVL that during this period, v gs_M can be written as in Equation (1), and V gs_M(max) = v gs_M (t 0 ): where V D3 is the breakdown voltage of Zener diode D 3 ; i 2 and i 3 are the current flowing through R 2 and R 3 , respectively. Adding C 0 to the gate of M will reduce i 2 (t 0 ), which can protect V cc . However, since V gs_M(max) is negative, the decrease in i 2 (t 0 ) will cause the absolute value of V gs_M(max) to increase significantly, which will endanger the safety of the MOSFET. In contrast, the impulse current withstand capability of the widely used DC voltage supply can reach several amperes or tens of amperes. Even without C 0 , i 2 (t 0 ) is not enough to cause harm to V cc . Therefore, the benefit of C 0 is far less than the harm it causes.

Proposal of the Improved DVCC
The schematic of the improved DVCC for conduction loss measurement is described in Figure 2. By conducting two changes in the structure of the conventional DVCC, the problems existing in the conventional DVCC are solved.

Proposal of the Improved DVCC
The schematic of the improved DVCC for conduction loss measurement is described in Figure 2. By conducting two changes in the structure of the conventional DVCC, the problems existing in the conventional DVCC are solved. Firstly, to accurately measure vds_on_osc of the DUT, the improved DVCC removes antiparallel diodes (i.e., D1 and D2 in Figure 1) from the output voltage measurement point. Under this arrangement, the on-state voltage of the two stages, on-steady state and onoscillation state, both have high measurement accuracy. Furthermore, the calculation error of conduction loss is limited to a small value.
In addition, considering the harmfulness of C0 to the core device M, another improvement is to remove the gate-shunt capacitance (i.e., C0 in Figure 1). This measure dramatically improves the operating environment of M. In addition, there is no need to worry about the safety of Vcc. For typical DC sources, their impulse current tolerance often reaches several amps or tens of amps, while the maximum current flowing through Vcc is usually hundreds of milliamps. Therefore, the work safety of Vcc will not be threatened.

Component Selection
In Section 2, the pros of the improved DVCC and the cons of conventional DVCC were highlighted. In this section, the influence of component parameters on the performance of the improved DVCC is analyzed in detail. Furthermore, guidelines for component selection are given to utilize the improved circuit better.

Evaluation Indicators
Theoretically, there are three conditions that the circuit must meet to perform the functions of clamping and measuring normally, as listed below.
1. Ensure the security of core MOSFET (M); 2. M should be in the proper working state when the DUT is in the on-state; 3. M should be in the proper working state when the DUT is in the off-state.
Considering the above three restrictions, this article comprehensively extracts three electrical quantities as the judgment indicators of the circuit performance to guide component selection: 1. Gate−source voltage negative overshoot (Vgs_M(max)) of M, which is denoted as EI1. As indicated in Section 2, it is necessary to avoid Vgs_M(max) exceeding the gate-source tolerance of core M. Therefore, the low EI1 value is of greater significance for improving the security of M. 2. Gate−source voltage of M (vgs_M(on)) when the DUT is in the on-state, which is denoted as EI2. If the DUT is in the on-state, M should also be in the on-state to satisfy vout = vds_on. Therefore, the second evaluation indicator should meet EI2 > Vth_M. 3. Gate−source voltage of M (vgs_M(off)) when the DUT is in the off-state, which is denoted as EI3. When the DUT is in the off-state, the working state of M should also be consistent with the DUT to withstand high off-voltage and reduce the potential of the Firstly, to accurately measure v ds_on_osc of the DUT, the improved DVCC removes anti-parallel diodes (i.e., D 1 and D 2 in Figure 1) from the output voltage measurement point. Under this arrangement, the on-state voltage of the two stages, on-steady state and on-oscillation state, both have high measurement accuracy. Furthermore, the calculation error of conduction loss is limited to a small value.
In addition, considering the harmfulness of C 0 to the core device M, another improvement is to remove the gate-shunt capacitance (i.e., C 0 in Figure 1). This measure dramatically improves the operating environment of M. In addition, there is no need to worry about the safety of V cc . For typical DC sources, their impulse current tolerance often reaches several amps or tens of amps, while the maximum current flowing through V cc is usually hundreds of milliamps. Therefore, the work safety of V cc will not be threatened.

Component Selection
In Section 2, the pros of the improved DVCC and the cons of conventional DVCC were highlighted. In this section, the influence of component parameters on the performance of the improved DVCC is analyzed in detail. Furthermore, guidelines for component selection are given to utilize the improved circuit better.

Evaluation Indicators
Theoretically, there are three conditions that the circuit must meet to perform the functions of clamping and measuring normally, as listed below.
M should be in the proper working state when the DUT is in the on-state; 3.
M should be in the proper working state when the DUT is in the off-state.
Considering the above three restrictions, this article comprehensively extracts three electrical quantities as the judgment indicators of the circuit performance to guide component selection:

1.
Gate−source voltage negative overshoot (V gs_M(max) ) of M, which is denoted as EI 1 . As indicated in Section 2, it is necessary to avoid V gs_M(max) exceeding the gatesource tolerance of core M. Therefore, the low EI 1 value is of greater significance for improving the security of M.

2.
Gate−source voltage of M (v gs_M(on) ) when the DUT is in the on-state, which is denoted as EI 2 . If the DUT is in the on-state, M should also be in the on-state to satisfy v out = v ds_on . Therefore, the second evaluation indicator should meet EI 2 > V th_M .

3.
Gate−source voltage of M (v gs_M(off) ) when the DUT is in the off-state, which is denoted as EI 3 . When the DUT is in the off-state, the working state of M should also be consistent with the DUT to withstand high off-voltage and reduce the potential of the measurement point A. Under this condition, EI 3 should be less than V th_M , so that M can be turned off reliably [29].

Selection of MOSFET
Since the parameters of M are closely related to the safe operation of the entire circuit, criteria for selecting the subject are proposed based on the working principle of the improved DVCC.
As stated before, with the transitions of DUT from the on-state to the off-state, M also changes its state rapidly so as to prevent the continuous increase of the source current of M and prevent EI 1 from being too large. Similarly, when the DUT changes from the off-state to the on-state, M needs to be turned on immediately to avoid measurement delay. Therefore, it is recommended that the switching speed of M be consistent with or faster than DUT, which is the first criterion for the selection of M.
In addition, since the improved DVCC utilizes the high blocking voltage characteristic of M to exercise the clamping function, during the off-state of the DUT, the drain-source withstand voltage of M is almost the same as that of the DUT. To increase the operational reliability of M, it is advised that the blocking voltage level of M is consistent with or higher than the DUT, which is considered the second criterion.

Selection of DC Voltage Supply V cc and Zener Diode Breakdown Voltage
Since Zener diode D 3 is in the gate−source loop of M, EI 1 is one of the vital evaluation indicators for selecting V D3 . The influence of V D3 on the work security of M is analyzed in this subsection.
According to Figure 2, the gate−source negative overshoot of M can be expressed as follows: where I 2 and I 3 are the currents flowing through R 2 and R 3 at time t 0 , respectively. According to Equation (2), V D3 increases, and the absolute value of EI 1 increases accordingly. Based on the interpretation content of the first evaluation indicator, for high security of M, V D3 should be as small as possible.

Voltage Constraint for Effective Work
The DC voltage supply V cc and the Zener diode D 3 jointly control the turn-on and turn-off of M to make it follow the steps of the state change of DUT. Therefore, it can be seen that the values of v gs_M(on) and v gs_M(off) are closely related to V cc and V D3 . Based on the supplementary content when the second and third evaluation indicators are proposed, it can be estimated that V cc and V D3 have a mutually restrictive relationship. In this paper, this specific constraint is called the "voltage constraint for effective work (VCEW)" and is further discussed in the subsequent sections.
When the DUT is in the on-state, EI 2 can be expressed as in the equation below: where i 2_on is the current flowing through the resistor R 2 when the DUT is in the on-state. Since M is also in the on-state, i 2_on can be obtained as follows: where i g_M is the gate current of M. Therefore, Equation (3) can be simplified to If the working condition of the DUT is known, the maximum on-state voltage V on_max of the DUT is determined. At this time, the size of EI 2 depends on the value of the DC voltage supply (V cc ). To ensure that M is in the on-state, it should meet the following condition: When the DUT is in the off-state, EI 3 can be described as follows: where i 2_off and i 3_off are the currents flowing through R 2 and R 3 , respectively, when the DUT is in the off-state; V D3 is the voltage across the Zener diode D 3 . Since M is in the off-state, i 2_off and i 3_off can be obtained as follows: where i leak_M is the leakage current of M. Equation (7) is further simplified to When the DUT is in the off-state, D 3 has two possible scenarios [30]. If the leakage current of D 3 is more significant than M, D 3 is in the reverse cut-off state, and V D3 meets the condition: In this scenario, a voltage equilibrium will be established: as V cc changes, V D3 changes accordingly, so that EI 3 is always maintained at a voltage less than V th_M . According to Equation (11), when selecting V cc , its value should satisfy the following condition: In another scenario, if the leakage current of D 3 is less than M, D 3 is in the breakdown state and V D3 = V D3 . Obviously, in this circumstance, V cc is selected based on the below equation: Considering Equations (6), (12), and (13) and adding in a margin of error, Equation (14) is written to reveal the mechanism of VCEW.
3.4. Selection of Gate Resistance R 2 and Source Resistance R 3 3.4.1. Selection Principle of R 2 and R 3 R 2 and R 3 are located in different branches of the gate−source loop of M, so that they have the opposite effect on EI 1 (V gs_M(max) ). Therefore, by choosing appropriate R 2 and R 3 values, the gate−source voltage negative overshoot (V gs_M(max) ) of M can be suppressed as much as possible.
At t 0 , when the V gs_M(max) occurs, M has been completely turned off, and the improved DVCC can be equivalent to the course shown in Figure 3 [29].  According to Figure 3, the first evaluation indicator can be expressed as where Id_M is the drain current of M.
According to [29], at this time, Cg << Cs. The coefficient of the third term in Equation (15) is abbreviated as e + jf. Then, the real and imaginary parts of EI1 can be written as in Equations (17) and (18), respectively; Since the parasitic capacitance of MOSFET is pF level (10 −12 ), and the oscillation frequency of drain current is generally MHz level (10 6~1 0 8 ). Therefore, (Cg + Cs) >> (wCsCgR2 + wCsCgR3). Based on this, Equations (21) and (22) can be derived; According to Equation (22), |EI1| is positively correlated with R3 and negatively correlated with R2. Therefore, the selection guide for these two resistors is to increase R2 and decrease R3 as much as possible. It is worth noting that this increase or decrease is not unlimited, which is described in more detail in the following subsection.

Measurement Error Constraint
During the on-oscillation state, with R3 decreasing, the measurement accuracy of the on-state voltage vds_on_osc gradually decreases. To make the relative error of the vds_on_osc measurement less than r%, R3 cannot be too small. This paper refers to this constraint relationship as the "measurement error constraint" (MEC).
During the on-oscillation state, vds_on_osc can be described as follows: where vds_M is the drain-source voltage of M. According to Figure 3, the first evaluation indicator can be expressed as where I d_M is the drain current of M.
According to [29], at this time, C g << C s . The coefficient of the third term in Equation (15) is abbreviated as e + jf. Then, the real and imaginary parts of EI 1 can be written as in Equations (17) and (18), respectively; Since the parasitic capacitance of MOSFET is pF level (10 −12 ), and the oscillation frequency of drain current is generally MHz level (10 6~1 0 8 ). Therefore, (C g + C s ) >> (wC s C g R 2 + wC s C g R 3 ). Based on this, Equations (21) and (22) can be derived; According to Equation (22), |EI 1 | is positively correlated with R 3 and negatively correlated with R 2 . Therefore, the selection guide for these two resistors is to increase R 2 and decrease R 3 as much as possible. It is worth noting that this increase or decrease is not unlimited, which is described in more detail in the following subsection.

Measurement Error Constraint
During the on-oscillation state, with R 3 decreasing, the measurement accuracy of the on-state voltage v ds_on_osc gradually decreases. To make the relative error of the v ds_on_osc measurement less than r%, R 3 cannot be too small. This paper refers to this constraint relationship as the "measurement error constraint" (MEC).
During the on-oscillation state, v ds_on_osc can be described as follows: where v ds_M is the drain-source voltage of M. During this process, v ds_on_osc gradually shifts from the on-oscillation state to the on-steady state in the form of a second-order oscillation. According to the structure of the improved DVCC, D 3 is connected in reverse between A and B. Therefore, when v ds_on_osc > 0, D 3 is in the reverse cut-off state, and v out can be expressed as follows: where R D3_off is the equivalent resistance of D 3 when it is in the reverse cut-off state; R ds_M is the equivalent resistance of M. Since M has been fully turned on at this stage, R ds_M has the same value as the on-state resistance of M. In addition, considering that D 3 can be regarded as an open circuit at this time, the relationship between v out and v ds_on_osc can be expressed as follows: However, when v ds_on_osc < 0, D 3 is in the forward conduction state, and v out can be expressed as follows: where R D3_on is the equivalent resistance of D 3 when it is in the forward conduction state. In this case, it is essential that the resistance of R 3 not be too small, so that the measurement accuracy is not compromised due to the partial voltage of R ds_M . Therefore, restricted by MEC, R 3 needs to meet the following condition: Furthermore, Equation (27) is simplified to where r% is generally around 5%.

Switching Speed Constraint
R 2 is located at the gate of M. Therefore, when R 2 increases, the gate charging and discharging speed of the gate driver are slowed down accordingly [29]. In an attempt to ensure that the switching speed of M is not slower than that of the DUT, R 2 cannot be too large. This paper calls this constraint relationship the "switching speed constraint" (SSC).
In order to obtain the limit of R 2 , the influence of R 2 on the rising speed of v gs_M is simplified as the influence of R 2 on the charging time constant when M is turned on. According to Equations (5) and (10), when M is turned on, the amount of change in v gs_M is ( Therefore, restricted by SSC, R 2 needs to meet the following condition: (30) where V g_max is the gate−source voltage stability value of the DUT; R g and V th_DUT are the gate drive resistance and the threshold voltage of the DUT, respectively; and C gs_M and C gs_DUT are the gate−source parasitic capacitances of M and DUT, respectively.
Considering that V D3 ≤ V D3 , Equation (30) can be further simplified to

Simulation and Experimental Verification
This paper set up a test platform integrating conventional DVCC and improved DVCC, as shown in Figure 4, to evaluate the measurement accuracy and work safety of the improved DVCC and the correctness of the selection theory. The primary circuit of the test platform is a double pulse test circuit (DPTC), including a DUT, freewheeling diode D 0 , bus capacitor C bus , digital signal processing (DSP), and drive module V g . DSP is used to transmit drive signals to control the turn-on and turn-off of the DUT.
The voltage clamp circuit comprises a MOSFET (M), DC source V cc , gate resistance R 2 , source resistance R 3 , and Zener diode D 3 . In order to facilitate the comparison between the improved DVCC and conventional DVCC, the connectors for the gate-shunt capacitor C 0 and the anti-parallel diodes D 1 and D 2 are reserved.

Simulation and Experimental Verification
This paper set up a test platform integrating conventional DVCC and improved DVCC, as shown in Figure 4, to evaluate the measurement accuracy and work safety of the improved DVCC and the correctness of the selection theory. The primary circuit of the test platform is a double pulse test circuit (DPTC), including a DUT, freewheeling diode D0, bus capacitor Cbus, digital signal processing (DSP), and drive module Vg. DSP is used to transmit drive signals to control the turn-on and turn-off of the DUT.
The voltage clamp circuit comprises a MOSFET (M), DC source Vcc, gate resistance R2, source resistance R3, and Zener diode D3. In order to facilitate the comparison between the improved DVCC and conventional DVCC, the connectors for the gate-shunt capacitor C0 and the anti-parallel diodes D1 and D2 are reserved. The specific experimental conditions are listed in Table 1. Both the DUT and the auxiliary device M are the 1200 V/31.6 A SiC MOSFET produced by CREE, while the freewheeling diode D0 is the SiC Schottky diode of the unified manufacturer.  Figure 4, the corresponding equivalent simulation circuit is extracted, as shown in Figure 5. Inside the dotted frame on the right is the DVCC, while the double pulse circuit is in the dotted frame on the left, and its circuit components are shown in Table 2. The simulation models of DUT, M, and D0 are all from the semiconductor company that produces the device, and the parasitic parameters are extracted by finite element simulation software.

Symbol Parameters Lg1
Parasitic inductance of the gate of the DUT The specific experimental conditions are listed in Table 1. Both the DUT and the auxiliary device M are the 1200 V/31.6 A SiC MOSFET produced by CREE, while the freewheeling diode D 0 is the SiC Schottky diode of the unified manufacturer. According to the experimental platform shown in Figure 4, the corresponding equivalent simulation circuit is extracted, as shown in Figure 5. Inside the dotted frame on the right is the DVCC, while the double pulse circuit is in the dotted frame on the left, and its circuit components are shown in Table 2. The simulation models of DUT, M, and D 0 are all from the semiconductor company that produces the device, and the parasitic parameters are extracted by finite element simulation software.  Figure 5. Equivalent simulation circuit.

Quantitative Simulation Analysis
Since the oscilloscope cannot measure the accurate value of the on-state voltage vds_on, it is hard to quantitatively analyze the relative error between the output voltage vout and vds_on through experiments. Therefore, this work uses the simulation circuit shown in Figure 5 to compare the on-state voltage and conduction loss measurement accuracy between the conventional DVCC and the improved DVCC. Under the working condition that VDC is set to 500V, the simulation results are shown in Figure 6.

Quantitative Simulation Analysis
Since the oscilloscope cannot measure the accurate value of the on-state voltage v ds_on , it is hard to quantitatively analyze the relative error between the output voltage v out and v ds_on through experiments. Therefore, this work uses the simulation circuit shown in Figure 5 to compare the on-state voltage and conduction loss measurement accuracy between the conventional DVCC and the improved DVCC. Under the working condition that V DC is set to 500 V, the simulation results are shown in Figure 6. In Figure 6, vds is the voltage waveform measured directly at the drain and source of the DUT. When the DUT is in the on state, vds = vds_on. As shown in Figure 6c, the conventional DVCC cannot measure a voltage less than −1.7 V, while the improved DVCC solves this problem (see Figure 6d). Table 3 selects three measurement points, which are located at the moments when the first, second, and third negative peaks of the drain-source voltage of the DUT occur, to compare the vds (actual value) and the output voltage vout. As shown in Table 3, during the on-oscillation state, the max voltage measurement relative error of the conventional DVCC can reach up to 78.8%, while the error value of the improved DVCC is reduced to less than 17.6%. The comparison results of vds (actual value) and vout during the on-steady state are shown in Table 4, which shows that the relative errors of the on-steady state voltage measured by the conventional DVCC and the improved DVCC are both within 1%. Furthermore, the conduction loss measurement errors of the conventional DVCC and the improved DVCC, as shown in Table 5  In Figure 6, v ds is the voltage waveform measured directly at the drain and source of the DUT. When the DUT is in the on state, v ds = v ds_on . As shown in Figure 6c, the conventional DVCC cannot measure a voltage less than −1.7 V, while the improved DVCC solves this problem (see Figure 6d). Table 3 selects three measurement points, which are located at the moments when the first, second, and third negative peaks of the drainsource voltage of the DUT occur, to compare the v ds (actual value) and the output voltage v out . As shown in Table 3, during the on-oscillation state, the max voltage measurement relative error of the conventional DVCC can reach up to 78.8%, while the error value of the improved DVCC is reduced to less than 17.6%. The comparison results of v ds (actual value) and v out during the on-steady state are shown in Table 4, which shows that the relative errors of the on-steady state voltage measured by the conventional DVCC and the improved DVCC are both within 1%. Furthermore, the conduction loss measurement errors of the conventional DVCC and the improved DVCC, as shown in Table 5, are 6.42% and 0.78%, respectively, which proves the high accuracy of the conduction loss measurement of the improved circuit.   To more powerfully illustrate the reduction of conduction loss and on-state voltage measurement error, simulations under different voltages are supplemented. During the test, the V DC is set to 400 V and 600 V, respectively, and the measurement results are shown in Figure 7.  To more powerfully illustrate the reduction of conduction loss and on-state voltage measurement error, simulations under different voltages are supplemented. During the test, the VDC is set to 400 V and 600 V, respectively, and the measurement results are shown in Figure 7. The relative error between vds (actual value) and vout during the on-oscillation state is shown in Figure 7. Compared with the conventional DVCC, the measurement relative error of the improved DVCC is significantly reduced. When VDC is 400 V and 600 V, the maximum relative errors are reduced from 78.31% and 77.33% to 19.02% and 21.84%, respectively. Furthermore, by comparing the conduction loss value measured by the con-  The relative error between v ds (actual value) and v out during the on-oscillation state is shown in Figure 7. Compared with the conventional DVCC, the measurement relative error of the improved DVCC is significantly reduced. When V DC is 400 V and 600 V, the maximum relative errors are reduced from 78.31% and 77.33% to 19.02% and 21.84%, respectively. Furthermore, by comparing the conduction loss value measured by the conventional DVCC and the improved DVCC, it can be known that when the V DC is 400 V and 600 V, the relative errors are reduced from 6.60% and 6.85% to 1.07% and 1.65%, respectively, which is shown in Table 6.

Qualitative Experimental Verification
The comparative experiment of the on-oscillation state voltage measurement is carried out in this section. Under the same working condition, the conventional DVCC and improved DVCC are used to measure the on-state voltage of the DUT, respectively. The voltage negative overshoot measured by the two circuits is compared, and the result is shown in Figure 8. improved DVCC are used to measure the on-state voltage of the DUT, respectively. The voltage negative overshoot measured by the two circuits is compared, and the result is shown in Figure 8. It can be seen from Figure 8 that compared to the improved DVCC, the drain-source voltage negative overshoot measured by the conventional DVCC is significantly reduced. Under the test voltage conditions of 500 V, the measurement result of the voltage negative overshoot is reduced by 11.3 V, which is consistent with the theoretical analysis in Section 2.2.1 and the simulation verification in Section 4.2.1.

Comparison of Work Security of M in Conventional DVCC and Improved DVCC
The experiments are carried out utilizing the test platform shown in Figure 4, with the primary circuit (DPTC) operating conditions unchanged. Due to the presence of the gate-shunt capacitance, the gate-source voltage negative overshoot of M may exceed its tolerance limit. Therefore, the VDC is set to 400V to ensure the safety of M. The current waveform flowing through Vcc and the gate−source voltage waveform of M are shown in Figure 9. It can be seen from Figure 8 that compared to the improved DVCC, the drain-source voltage negative overshoot measured by the conventional DVCC is significantly reduced. Under the test voltage conditions of 500 V, the measurement result of the voltage negative overshoot is reduced by 11.3 V, which is consistent with the theoretical analysis in Section 2.2.1 and the simulation verification in Section 4.2.1.

Comparison of Work Security of M in Conventional DVCC and Improved DVCC
The experiments are carried out utilizing the test platform shown in Figure 4, with the primary circuit (DPTC) operating conditions unchanged. Due to the presence of the gate-shunt capacitance, the gate-source voltage negative overshoot of M may exceed its tolerance limit. Therefore, the V DC is set to 400 V to ensure the safety of M. The current waveform flowing through V cc and the gate−source voltage waveform of M are shown in Figure 9.

Comparison of Work Security of M in Conventional DVCC and Improved DVC
The experiments are carried out utilizing the test platform shown in Figure 4, w the primary circuit (DPTC) operating conditions unchanged. Due to the presence of gate-shunt capacitance, the gate-source voltage negative overshoot of M may exceed tolerance limit. Therefore, the VDC is set to 400V to ensure the safety of M. The curr waveform flowing through Vcc and the gate−source voltage waveform of M are show Figure 9. The improved DVCC reduces the absolute value of V gs_M(max) from 14.12 to 0.78 V but increases the max current flowing through V cc from 0.43 to 0.71 A. As seen, the increase in current can be ignored because it is still far less than the impulse tolerance of the DC voltage supply. However, according to the datasheet, the gate−source withstand voltage limit V gs_limit of M is only −10 V. Therefore, the reduction of V gs_M(max) from −14.12 to −0.78 V makes M out of unsafe conditions, which significantly improves the work security of M.

Work Security of M and V cc at Higher Voltages
To study the working safety of V cc and M in the improved DVCC under higher voltages (500 V, 600 V, 700 V, 800 V), related experiments are carried out. The circuit components are selected based on the selection theory proposed in this article to ensure the safety of the experiments. Since the target maximum experimental voltage is 800 V, V D3 is set to 7.5 V, V cc is set to 7 V, R 2 is selected to 50 Ω, and R 3 is selected to 5 Ω for the experiment. The results are shown in Figure 10. The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V but increases the max current flowing through Vcc from 0.43 to 0.71 A. As seen, the increase in current can be ignored because it is still far less than the impulse tolerance of the DC voltage supply. However, according to the datasheet, the gate−source withstand voltage limit Vgs_limit of M is only −10 V. Therefore, the reduction of Vgs_M(max) from −14.12 to −0.78 V makes M out of unsafe conditions, which significantly improves the work security of M.

Work Security of M and Vcc at Higher Voltages
To study the working safety of Vcc and M in the improved DVCC under higher voltages (500 V, 600 V, 700 V, 800 V), related experiments are carried out. The circuit components are selected based on the selection theory proposed in this article to ensure the safety of the experiments. Since the target maximum experimental voltage is 800 V, VD3 is set to 7.5 V, Vcc is set to 7 V, R2 is selected to 50 Ω, and R3 is selected to 5 Ω for the experiment. The results are shown in Figure 10. As shown in Figure 10, at higher voltages, the gate-source voltage negative overshoot of M (EI 1 ) is always within the maximum rating of the gate-source voltage of M. In addition, at the moment of turning off, the maximum current flowing through the DC source (V cc ) is about 0.8 A, which is much smaller than the impulse current tolerance of the DC source. Therefore, the improved circuit proposed in this article can still work effectively and safely under high-voltage conditions.

Selection Method of V cc and V D3
According to the working principle of the double pulse circuit and the device parameters of the DUT, when the off-state voltage of the DUT is 800 V, the maximum on-state voltage V on_max can reach 3.2 V. Based on the selection mechanism and detailed analyses in Section 3, set V cc to 7 V and V D3 to 7.5 V for the experiment. The results are depicted in Figure 11. As shown in Figure 11, under different voltages, when the DUT is in the on state, it always meets EI2 > Vth_M, ensuring that M is normally turned on. When the DUT is in the off state, it satisfies EI3 < Vth_M, so that M is also in the off state. The experimental results prove the rationality of the selection method of Vcc and VD3.

Selection Method of R2 and R3
According to Equations (28) and (31), R3 > 1.52 Ω and R2 < 55 Ω while meeting SSC and MEC. Using the controlled variable method, when Vcc, VD3, and R3 are determined, set R2 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. Figure 12a demonstrates the measured EI1 in the case of different R2. Moreover, when R2 is determined, set the resistance of R3 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI1 with R3 is shown in Figure 12b. As shown in Figure 11, under different voltages, when the DUT is in the on state, it always meets EI 2 > V th_M , ensuring that M is normally turned on. When the DUT is in the off state, it satisfies EI 3 < V th_M , so that M is also in the off state. The experimental results prove the rationality of the selection method of V cc and V D3 .

Selection Method of R 2 and R 3
According to Equations (28) and (31), R 3 > 1.52 Ω and R 2 < 55 Ω while meeting SSC and MEC. Using the controlled variable method, when V cc , V D3 , and R 3 are determined, set R 2 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. Figure 12a demonstrates the measured EI 1 in the case of different R 2 . Moreover, when R 2 is determined, set the resistance of R 3 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI 1 with R 3 is shown in Figure 12b.

Selection Method of R2 and R3
According to Equations (28) and (31), R3 > 1.52 Ω and R2 < 55 Ω while meeting SSC and MEC. Using the controlled variable method, when Vcc, VD3, and R3 are determined, set R2 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. Figure 12a demonstrates the measured EI1 in the case of different R2. Moreover, when R2 is determined, set the resistance of R3 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI1 with R3 is shown in Figure 12b.  As described in Figure 12, EI 1 decreases with the increase in R 2 , and it increases with the increase in R 3 . The experimental results effectively verify the correctness of the theoretical analysis indicated in Section 3. When choosing R 2 , the resistance should be as large as possible while meeting SSC. In contrast, when choosing R 3 , the resistance should be as small as possible while completing MEC.

Error Analysis
The size of the error in on-state voltage and conduction loss measurement, using the improved DVCC, is further analyzed to highlight the accuracy over different working conditions. Based on the circuit shown in Figure 5, the on-state voltage of the DUT is measured by the improved DVCC under the V DC of 300 V, 400 V, 500 V, 600 V, 700 V, and 800 V. Subsequently, utilizing the measured on-state voltage, the conduction loss is calculated. Furthermore, the measurement results of improved DVCC are compared with the actual value to get the relative error, which is shown in Figure 13. As described in Figure 12, EI1 decreases with the increase in R2, and it increases with the increase in R3. The experimental results effectively verify the correctness of the theoretical analysis indicated in Section 3. When choosing R2, the resistance should be as large as possible while meeting SSC. In contrast, when choosing R3, the resistance should be as small as possible while completing MEC.

Error Analysis
The size of the error in on-state voltage and conduction loss measurement, using the improved DVCC, is further analyzed to highlight the accuracy over different working conditions. Based on the circuit shown in Figure 5, the on-state voltage of the DUT is measured by the improved DVCC under the VDC of 300 V, 400 V, 500 V, 600 V, 700 V, and 800 V. Subsequently, utilizing the measured on-state voltage, the conduction loss is calculated. Furthermore, the measurement results of improved DVCC are compared with the actual value to get the relative error, which is shown in Figure 13. It can be seen from Figure 13 that when using the improved DVCC to measure the conduction loss of the DUT, the relative error between the measurement result and the actual value remains below 1.7%. In addition, at the moment of turning on, the measurement relative error of the first negative peak is kept within 25%. Moreover, in the onsteady state, the maximum relative error of the on-steady state voltage measurement is within 2.75%. The above data effectively prove the high measurement accuracy of the improved DVCC. It can be seen from Figure 13 that when using the improved DVCC to measure the conduction loss of the DUT, the relative error between the measurement result and the actual value remains below 1.7%. In addition, at the moment of turning on, the measurement relative error of the first negative peak is kept within 25%. Moreover, in the on-steady state, the maximum relative error of the on-steady state voltage measurement is within 2.75%. The above data effectively prove the high measurement accuracy of the improved DVCC.

Conclusions
An improved DVCC topology for measuring the conduction loss of power semiconductor devices is proposed and fully characterized in this article. The proposed DVCC, in comparison with the existing designs (conventional DVCC) through simulation and experimentation, shows better accuracy and higher security. During the on-oscillation state, the maximum relative error of the on-state voltage measurement decreased from 78.8% to 17.6%, and the on-state voltage measurement accuracy is greatly improved. Furthermore, the relative error of the total conduction loss measurement of the two on-state stages is reduced from 6.42% to 0.78%, which is one of the critical contributions of the proposed approach. Another key advantage of the improved DVCC is that it improves the working security of M, which is embodied in the reduction of the gate−source voltage negative overshoot of the auxiliary device MOSFET from −14.12 to 0.78 V. In addition, the influence of component parameters on the circuit performance of the improved DVCC is discussed, and three electrical quantities are extracted as the judgment indicators for the component selection, including the gate−source voltage negative overshoot (V gs_M(max) ) of M, the gate−source voltage v gs_M(on) of M when the DUT is in the on state, and the gate−source voltage v gs_M(off) of M when the DUT is in the off state. Finally, the component selection criteria are given and validated by experimental results. First, the switching speed and blocking voltage level of M should be consistent with or better than the DUT. Second, in the case of meeting VCEW, the breakdown voltage of the Zener diode (D 3 ) should be selected to be a small value. Third, under the conditions of fulfilling MEC and SSC, the selection guide for these two resistors is to increase R 2 and decrease R 3 as much as possible.
Funding: This work was supported by State Grid science and technology projects (Electrical characterization and screening method of press-pack IGBT chip (grant no. 5455GB190007).